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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] bcd1;
reg [7:0] bcd2;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                //$display("RESTART");
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                X <= 0;
                Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                //$display("A = %h result = %h", A, result);
                //$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
 
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
                        begin
                                //$display("A = %h result = %h", A, result);
                                //$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :
                        begin
                                alu_status <= STATUS;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 0;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
        bcd1      = A;
        bcd2      = alu_a;
        result    = alu_result;
        STATUS[N] = alu_status[N];
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
        STATUS[Z] = alu_status[Z];
        STATUS[N] = alu_status[N];
        STATUS[5] = alu_status[5];
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                BRK_IMP: begin
                        STATUS[B] = 1'b1;
                end
 
                // CLC - Clear Carry Flag
                CLC_IMP: begin
                        STATUS[C] = 1'b0;
                end
 
                // CLD - Clear Decimal Flag
                CLD_IMP: begin
                        STATUS[D] = 1'b0;
                end
 
                // CLI - Clear Interrupt Disable
                // TODO: verify if this should be supported by 6507
                CLI_IMP: begin
                        STATUS[I] = 1'b0;
                end
 
                // CLV - Clear Overflow Flag
                CLV_IMP: begin
                        STATUS[V] = 1'b0;
                end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                PLP_IMP, RTI_IMP: begin
                        STATUS = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        result = X;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        result = Y;
                end
 
                // SEC - Set Carry Flag
                SEC_IMP: begin
                        STATUS[C] = 1'b1;
                end
 
                // SED - Set Decimal Flag
                SED_IMP: begin
                        STATUS[D] = 1'b1;
                end
 
                // SEI - Set Interrupt Disable
                SEI_IMP: begin
                        STATUS[I] = 1'b1;
                end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        result = X + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        result = Y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        result = X - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        result = Y - 1;
                end
 
                // ADC - Add with carry
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        bcd1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (bcd1[7:4] > 9) begin
                                        bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        bcd2 = alu_a + 6;
                                end
                                if (bcd2[7:4] > 9) begin
                                        bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
                        //$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
                        //$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
                        {STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
                        if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
 
                        if (alu_status[D] == 1) begin
                                if (result[3:0] > 9) begin
                                        result = result[3:0] + 6; // A = A - 10 and A = A + 16
                                end
                                if (result[7:4] > 9) begin
                                        result = result[7:4] + 6; // A = A - 10 and A = A + 16
                                        STATUS[C] = 1;
                                end
                        end
                        //$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
                        //$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        result = A - alu_a;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a ;
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        bcd1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (bcd1[7:4] > 9) begin
                                        bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        bcd2 = alu_a + 6;
                                end
                                if (bcd2[7:4] > 9) begin
                                        bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
 
                        {STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];
                        if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        {STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right           
                ROR_ACC : begin
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        result = X - alu_a;
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        result = Y - alu_a;
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61			`reg [7:0] A;`
62			`reg [7:0] X;`
63			`reg [7:0] Y;`
64
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67			`reg [7:0] bcd1;`
68			`reg [7:0] bcd2;`
69
70			`include "t6507lp_package.v"
71
72			`always @ (posedge clk or negedge reset_n)`
73			`begin`
74			`if (reset_n == 0) begin`
75	150	gabrielosh	`//$display("RESTART");`
76	141	creep	`alu_result <= 0;`
77			`alu_status[C] <= 0;`
78			`alu_status[N] <= 0;`
79			`alu_status[V] <= 0;`
80	148	gabrielosh	`alu_status[5] <= 1;`
81	141	creep	`alu_status[Z] <= 1;`
82			`alu_status[I] <= 0;`
83			`alu_status[B] <= 0;`
84			`alu_status[D] <= 0;`
85			`A <= 0;`
86			`X <= 0;`
87			`Y <= 0;`
88			`alu_x <= 0;`
89			`alu_y <= 0;`
90			`end`
91			`else if ( alu_enable == 1 ) begin`
92	148	gabrielosh	`//$display("A = %h result = %h", A, result);`
93			`//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);`
94
95	141	creep	`case (alu_opcode)`
96			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
97			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
98			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
99			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
100			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
101			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
102			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :`
103			`begin`
104	149	gabrielosh	`//$display("A = %h result = %h", A, result);`
105	148	gabrielosh	`//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);`
106	141	creep	`A <= result;`
107			`alu_result <= result;`
108			`alu_status <= STATUS;`
109			`end`
110			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
111			`begin`
112			`X <= result;`
113			`alu_x <= result;`
114			`alu_status <= STATUS;`
115			`end`
116			`TXS_IMP :`
117			`begin`
118	148	gabrielosh	`X <= result;`
119			`alu_x <= result;`
120	141	creep	`end`
121			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
122			`begin`
123			`Y <= result;`
124			`alu_y <= result;`
125			`alu_status <= STATUS;`
126			`end`
127	148	gabrielosh	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
128			`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :`
129	141	creep	`begin`
130			`alu_status <= STATUS;`
131			`end`
132			`SEC_IMP :`
133			`begin`
134			`alu_status[C] <= 1;`
135			`end`
136			`SED_IMP :`
137			`begin`
138			`alu_status[D] <= 1;`
139			`end`
140			`SEI_IMP :`
141			`begin`
142			`alu_status[I] <= 1;`
143			`end`
144			`CLC_IMP :`
145			`begin`
146			`alu_status[C] <= 0;`
147			`end`
148			`CLD_IMP :`
149			`begin`
150			`alu_status[D] <= 0;`
151			`end`
152			`CLI_IMP :`
153			`begin`
154			`alu_status[I] <= 0;`
155			`end`
156			`CLV_IMP :`
157			`begin`
158			`alu_status[V] <= 0;`
159			`end`
160			`BRK_IMP :`
161			`begin`
162			`alu_status[B] <= 0;`
163			`end`
164			`PLP_IMP, RTI_IMP :`
165			`begin`
166	150	gabrielosh	`alu_status[C] <= alu_a[C];`
167			`alu_status[Z] <= alu_a[Z];`
168			`alu_status[I] <= alu_a[I];`
169			`alu_status[D] <= alu_a[D];`
170			`alu_status[B] <= alu_a[B];`
171			`alu_status[V] <= alu_a[V];`
172			`alu_status[N] <= alu_a[N];`
173	141	creep	`end`
174			`BIT_ZPG, BIT_ABS :`
175			`begin`
176			`alu_status[Z] <= STATUS[Z];`
177			`alu_status[V] <= alu_a[6];`
178			`alu_status[N] <= alu_a[7];`
179			`end`
180	148	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,`
181			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,`
182			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
183	141	creep	`begin`
184			`alu_result <= result;`
185			`alu_status <= STATUS;`
186			`end`
187			`default : begin`
188			`//$display("ERROR");`
189			`end`
190			`endcase`
191			`end`
192			`end`
193
194			`always @ (*) begin`
195			`bcd1 = A;`
196			`bcd2 = alu_a;`
197	150	gabrielosh	`result = alu_result;`
198			`STATUS[N] = alu_status[N];`
199			`STATUS[C] = alu_status[C];`
200			`STATUS[V] = alu_status[V];`
201			`STATUS[B] = alu_status[B];`
202			`STATUS[I] = alu_status[I];`
203			`STATUS[D] = alu_status[D];`
204			`STATUS[Z] = alu_status[Z];`
205			`STATUS[N] = alu_status[N];`
206			`STATUS[5] = alu_status[5];`
207	141	creep
208			`case (alu_opcode)`
209			`// BIT - Bit Test`
210			`BIT_ZPG, BIT_ABS: begin`
211			`result = A & alu_a;`
212			`end`
213
214			`// BRK - Force Interrupt`
215			`BRK_IMP: begin`
216			`STATUS[B] = 1'b1;`
217			`end`
218
219			`// CLC - Clear Carry Flag`
220			`CLC_IMP: begin`
221			`STATUS[C] = 1'b0;`
222			`end`
223
224			`// CLD - Clear Decimal Flag`
225			`CLD_IMP: begin`
226			`STATUS[D] = 1'b0;`
227			`end`
228
229			`// CLI - Clear Interrupt Disable`
230			`// TODO: verify if this should be supported by 6507`
231			`CLI_IMP: begin`
232			`STATUS[I] = 1'b0;`
233			`end`
234
235			`// CLV - Clear Overflow Flag`
236			`CLV_IMP: begin`
237			`STATUS[V] = 1'b0;`
238			`end`
239
240			`// NOP - No Operation`
241			`//NOP_IMP: begin`
242			`// Do nothing :-D`
243			`//end`
244
245			`// PLP - Pull Processor Status Register`
246			`PLP_IMP, RTI_IMP: begin`
247			`STATUS = alu_a;`
248			`end`
249
250			`// STA - Store Accumulator`
251			`// PHA - Push A`
252			`// TAX - Transfer Accumulator to X`
253			`// TAY - Transfer Accumulator to Y`
254			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
255			`result = A;`
256			`end`
257
258			`// STX - Store X Register`
259			`// TXA - Transfer X to Accumulator`
260			`// TXS - Transfer X to Stack pointer`
261			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
262			`result = X;`
263			`end`
264
265			`// STY - Store Y Register`
266			`// TYA - Transfer Y to Accumulator`
267			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
268			`result = Y;`
269			`end`
270
271			`// SEC - Set Carry Flag`
272			`SEC_IMP: begin`
273			`STATUS[C] = 1'b1;`
274			`end`
275
276			`// SED - Set Decimal Flag`
277			`SED_IMP: begin`
278			`STATUS[D] = 1'b1;`
279			`end`
280
281			`// SEI - Set Interrupt Disable`
282			`SEI_IMP: begin`
283			`STATUS[I] = 1'b1;`
284			`end`
285
286			`// INC - Increment memory`
287			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
288			`result = alu_a + 1;`
289			`end`
290
291			`// INX - Increment X Register`
292			`INX_IMP: begin`
293			`result = X + 1;`
294			`end`
295
296			`// INY - Increment Y Register`
297			`INY_IMP : begin`
298			`result = Y + 1;`
299			`end`
300
301			`// DEC - Decrement memory`
302			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
303			`result = alu_a - 1;`
304			`end`
305
306			`// DEX - Decrement X register`
307			`DEX_IMP: begin`
308			`result = X - 1;`
309			`end`
310
311			`// DEY - Decrement Y Register`
312			`DEY_IMP: begin`
313			`result = Y - 1;`
314			`end`
315
316			`// ADC - Add with carry`
317			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
318			`if (alu_status[D] == 1) begin`
319			`if (A[3:0] > 9) begin`
320			`bcd1 = A + 6; // A = A - 10 and A = A + 16`
321			`end`
322			`if (bcd1[7:4] > 9) begin`
323			`bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16`
324			`end`
325			`if (alu_a[3:0] > 9) begin`
326			`bcd2 = alu_a + 6;`
327			`end`
328			`if (bcd2[7:4] > 9) begin`
329			`bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16`
330			`end`
331			`end`
332	149	gabrielosh	`//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);`
333			`//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);`
334	141	creep	`{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];`
335			`if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))`
336			`STATUS[V] = 1;`
337			`else`
338			`STATUS[V] = 0;`
339
340			`if (alu_status[D] == 1) begin`
341			`if (result[3:0] > 9) begin`
342			`result = result[3:0] + 6; // A = A - 10 and A = A + 16`
343			`end`
344			`if (result[7:4] > 9) begin`
345			`result = result[7:4] + 6; // A = A - 10 and A = A + 16`
346			`STATUS[C] = 1;`
347			`end`
348			`end`
349	150	gabrielosh	`//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);`
350			`//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);`
351	141	creep	`end`
352
353			`// AND - Logical AND`
354			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
355			`result = A & alu_a;`
356			`end`
357
358			`// CMP - Compare`
359			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
360			`result = A - alu_a;`
361			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
362			`end`
363
364			`// EOR - Exclusive OR`
365			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
366			`result = A ^ alu_a ;`
367			`end`
368
369			`// LDA - Load Accumulator`
370			`// LDX - Load X Register`
371			`// LDY - Load Y Register`
372			`// TSX - Transfer Stack Pointer to X`
373			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
374			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
375			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
376			`TSX_IMP : begin`
377			`result = alu_a;`
378			`end`
379
380			`// ORA - Logical OR`
381			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
382			`result = A \| alu_a;`
383			`end`
384
385			`// SBC - Subtract with Carry`
386			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
387			`if (alu_status[D] == 1) begin`
388			`if (A[3:0] > 9) begin`
389			`bcd1 = A + 6; // A = A - 10 and A = A + 16`
390			`end`
391			`if (bcd1[7:4] > 9) begin`
392			`bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16`
393			`end`
394			`if (alu_a[3:0] > 9) begin`
395			`bcd2 = alu_a + 6;`
396			`end`
397			`if (bcd2[7:4] > 9) begin`
398			`bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16`
399			`end`
400			`end`
401
402			`{STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];`
403			`if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))`
404			`STATUS[V] = 1;`
405			`else`
406			`STATUS[V] = 0;`
407			`end`
408
409			`// ASL - Arithmetic Shift Left`
410			`ASL_ACC : begin`
411	145	gabrielosh	`//{STATUS[C],result} = A << 1;`
412			`{STATUS[C],result} = {A,1'b0};`
413	141	creep	`end`
414			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
415	145	gabrielosh	`//{STATUS[C],result} = alu_a << 1;`
416			`{STATUS[C],result} = {alu_a,1'b0};`
417	141	creep	`end`
418
419			`// LSR - Logical Shift Right`
420			`LSR_ACC: begin`
421	145	gabrielosh	`//{result, STATUS[C]} = A >> 1;`
422			`{result,STATUS[C]} = {1'b0,A};`
423	141	creep	`end`
424			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
425	145	gabrielosh	`//{result, STATUS[C]} = alu_a >> 1;`
426			`{result,STATUS[C]} = {1'b0,alu_a};`
427	141	creep	`end`
428
429			`// ROL - Rotate Left`
430			`ROL_ACC : begin`
431			`{STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?`
432			`end`
433			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
434			`{STATUS[C],result} = {alu_a,alu_status[C]};`
435			`end`
436
437			`// ROR - Rotate Right`
438			`ROR_ACC : begin`
439			`{result,STATUS[C]} = {alu_status[C],A};`
440			`end`
441			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
442			`{result, STATUS[C]} = {alu_status[C], alu_a};`
443			`end`
444
445			`// CPX - Compare X Register`
446			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
447			`result = X - alu_a;`
448			`STATUS[C] = (X >= alu_a) ? 1 : 0;`
449			`end`
450
451			`// CPY - Compare Y Register`
452			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
453			`result = Y - alu_a;`
454			`STATUS[C] = (Y >= alu_a) ? 1 : 0;`
455			`end`
456
457			`default: begin // NON-DEFAULT OPCODES FALL HERE`
458	142	gabrielosh	`end`
459	141	creep	`endcase`
460	142	gabrielosh	`STATUS[Z] = (result == 0) ? 1 : 0;`
461			`STATUS[N] = result[7];`
462	141	creep	`end`
463
464			`endmodule`
465

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