URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 159

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] op1;
reg [7:0] op2;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                X <= 0;
                Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
                        begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :
                        begin
                                alu_status <= STATUS;
                        end
                        PHA_IMP :
                        begin
                                alu_result <= result;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 1;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
        op1      = A;
        op2      = alu_a;
        result    = alu_result;
        STATUS[N] = alu_status[N];
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
        STATUS[Z] = alu_status[Z];
        STATUS[N] = alu_status[N];
        STATUS[5] = 1;
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                BRK_IMP: begin
                        STATUS[B] = 1'b1;
                end
 
                // CLC - Clear Carry Flag
                CLC_IMP: begin
                        STATUS[C] = 1'b0;
                end
 
                // CLD - Clear Decimal Flag
                CLD_IMP: begin
                        STATUS[D] = 1'b0;
                end
 
                // CLI - Clear Interrupt Disable
                CLI_IMP: begin
                        STATUS[I] = 1'b0;
                end
 
                // CLV - Clear Overflow Flag
                CLV_IMP: begin
                        STATUS[V] = 1'b0;
                end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                PLP_IMP, RTI_IMP: begin
                        STATUS = alu_a;
                end
 
                PLA_IMP : begin
                        result = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        result = X;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        result = Y;
                end
 
                // SEC - Set Carry Flag
                SEC_IMP: begin
                        STATUS[C] = 1'b1;
                end
 
                // SED - Set Decimal Flag
                SED_IMP: begin
                        STATUS[D] = 1'b1;
                end
 
                // SEI - Set Interrupt Disable
                SEI_IMP: begin
                        STATUS[I] = 1'b1;
                end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        result = X + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        result = Y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        result = X - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        result = Y - 1;
                end
 
                // ADC - Add with carry
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        op1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (op1[7:4] > 9) begin
                                        op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        op2 = alu_a + 6;
                                end
                                if (op2[7:4] > 9) begin
                                        op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
                        {STATUS[C],result} = op1 + op2 + alu_status[C];
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                        //$display("op1 + op2 + C = result + C (V)");
                        //$display("%d  + %d  + %b = %d + %b (%b)", op1, op2, alu_status[C],result,STATUS[C],STATUS[V]);
 
                        if (alu_status[D] == 1) begin
                                if (result[3:0] > 9) begin
                                        result = result[3:0] + 6; // A = A - 10 and A = A + 16
                                end
                                if (result[7:4] > 9) begin
                                        result = result[7:4] + 6; // A = A - 10 and A = A + 16
                                        STATUS[C] = 1;
                                end
                        end
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        result = A - alu_a;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a;
                        //$display("op1 ^ op2 = result");
                        //$display("%d  ^ %d  = %d", op1, op2, result);
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        op1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (op1[7:4] > 9) begin
                                        op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        op2 = alu_a + 6;
                                end
                                if (op2[7:4] > 9) begin
                                        op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
 
                        {STATUS[C],result} = op1 - op2 - ~alu_status[C];
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        {STATUS[C],result} = {A,alu_status[C]};
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right
                ROR_ACC : begin
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        result = X - alu_a;
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        result = Y - alu_a;
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2	152	gabrielosh	`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18	141	creep	`////////////////////////////////////////////////////////////////////////////`
19	152	gabrielosh	`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	141	creep	`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61			`reg [7:0] A;`
62			`reg [7:0] X;`
63			`reg [7:0] Y;`
64
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67	152	gabrielosh	`reg [7:0] op1;`
68			`reg [7:0] op2;`
69	141	creep
70			`include "t6507lp_package.v"
71
72			`always @ (posedge clk or negedge reset_n)`
73			`begin`
74			`if (reset_n == 0) begin`
75			`alu_result <= 0;`
76			`alu_status[C] <= 0;`
77			`alu_status[N] <= 0;`
78			`alu_status[V] <= 0;`
79	148	gabrielosh	`alu_status[5] <= 1;`
80	141	creep	`alu_status[Z] <= 1;`
81			`alu_status[I] <= 0;`
82			`alu_status[B] <= 0;`
83			`alu_status[D] <= 0;`
84			`A <= 0;`
85			`X <= 0;`
86			`Y <= 0;`
87			`alu_x <= 0;`
88			`alu_y <= 0;`
89			`end`
90			`else if ( alu_enable == 1 ) begin`
91			`case (alu_opcode)`
92			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
93			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
94			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
95			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
96			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
97			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
98			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :`
99			`begin`
100			`A <= result;`
101			`alu_result <= result;`
102			`alu_status <= STATUS;`
103			`end`
104			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
105			`begin`
106			`X <= result;`
107			`alu_x <= result;`
108			`alu_status <= STATUS;`
109			`end`
110			`TXS_IMP :`
111			`begin`
112	148	gabrielosh	`X <= result;`
113			`alu_x <= result;`
114	141	creep	`end`
115			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
116			`begin`
117			`Y <= result;`
118			`alu_y <= result;`
119			`alu_status <= STATUS;`
120			`end`
121	148	gabrielosh	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
122			`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :`
123	141	creep	`begin`
124			`alu_status <= STATUS;`
125			`end`
126	158	gabrielosh	`PHA_IMP :`
127			`begin`
128			`alu_result <= result;`
129			`end`
130	141	creep	`SEC_IMP :`
131			`begin`
132			`alu_status[C] <= 1;`
133			`end`
134			`SED_IMP :`
135			`begin`
136			`alu_status[D] <= 1;`
137			`end`
138			`SEI_IMP :`
139			`begin`
140			`alu_status[I] <= 1;`
141			`end`
142			`CLC_IMP :`
143			`begin`
144			`alu_status[C] <= 0;`
145			`end`
146			`CLD_IMP :`
147			`begin`
148			`alu_status[D] <= 0;`
149			`end`
150			`CLI_IMP :`
151			`begin`
152			`alu_status[I] <= 0;`
153			`end`
154			`CLV_IMP :`
155			`begin`
156			`alu_status[V] <= 0;`
157			`end`
158			`BRK_IMP :`
159			`begin`
160	154	gabrielosh	`alu_status[B] <= 1;`
161	141	creep	`end`
162			`PLP_IMP, RTI_IMP :`
163			`begin`
164	150	gabrielosh	`alu_status[C] <= alu_a[C];`
165			`alu_status[Z] <= alu_a[Z];`
166			`alu_status[I] <= alu_a[I];`
167			`alu_status[D] <= alu_a[D];`
168			`alu_status[B] <= alu_a[B];`
169			`alu_status[V] <= alu_a[V];`
170			`alu_status[N] <= alu_a[N];`
171	141	creep	`end`
172			`BIT_ZPG, BIT_ABS :`
173			`begin`
174			`alu_status[Z] <= STATUS[Z];`
175			`alu_status[V] <= alu_a[6];`
176			`alu_status[N] <= alu_a[7];`
177			`end`
178	148	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,`
179			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,`
180			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
181	141	creep	`begin`
182			`alu_result <= result;`
183			`alu_status <= STATUS;`
184			`end`
185			`default : begin`
186			`//$display("ERROR");`
187			`end`
188			`endcase`
189			`end`
190			`end`
191
192			`always @ (*) begin`
193	152	gabrielosh	`op1 = A;`
194			`op2 = alu_a;`
195	150	gabrielosh	`result = alu_result;`
196			`STATUS[N] = alu_status[N];`
197			`STATUS[C] = alu_status[C];`
198			`STATUS[V] = alu_status[V];`
199			`STATUS[B] = alu_status[B];`
200			`STATUS[I] = alu_status[I];`
201			`STATUS[D] = alu_status[D];`
202			`STATUS[Z] = alu_status[Z];`
203			`STATUS[N] = alu_status[N];`
204	151	gabrielosh	`STATUS[5] = 1;`
205	141	creep
206			`case (alu_opcode)`
207			`// BIT - Bit Test`
208			`BIT_ZPG, BIT_ABS: begin`
209			`result = A & alu_a;`
210			`end`
211
212			`// BRK - Force Interrupt`
213			`BRK_IMP: begin`
214			`STATUS[B] = 1'b1;`
215			`end`
216
217			`// CLC - Clear Carry Flag`
218			`CLC_IMP: begin`
219			`STATUS[C] = 1'b0;`
220			`end`
221
222			`// CLD - Clear Decimal Flag`
223			`CLD_IMP: begin`
224			`STATUS[D] = 1'b0;`
225			`end`
226
227			`// CLI - Clear Interrupt Disable`
228			`CLI_IMP: begin`
229			`STATUS[I] = 1'b0;`
230			`end`
231
232			`// CLV - Clear Overflow Flag`
233			`CLV_IMP: begin`
234			`STATUS[V] = 1'b0;`
235			`end`
236
237			`// NOP - No Operation`
238			`//NOP_IMP: begin`
239			`// Do nothing :-D`
240			`//end`
241
242			`// PLP - Pull Processor Status Register`
243			`PLP_IMP, RTI_IMP: begin`
244			`STATUS = alu_a;`
245			`end`
246	157	gabrielosh
247			`PLA_IMP : begin`
248			`result = alu_a;`
249			`end`
250	141	creep
251			`// STA - Store Accumulator`
252			`// PHA - Push A`
253			`// TAX - Transfer Accumulator to X`
254			`// TAY - Transfer Accumulator to Y`
255			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
256			`result = A;`
257			`end`
258
259			`// STX - Store X Register`
260			`// TXA - Transfer X to Accumulator`
261			`// TXS - Transfer X to Stack pointer`
262			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
263			`result = X;`
264			`end`
265
266			`// STY - Store Y Register`
267			`// TYA - Transfer Y to Accumulator`
268			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
269			`result = Y;`
270			`end`
271
272			`// SEC - Set Carry Flag`
273			`SEC_IMP: begin`
274			`STATUS[C] = 1'b1;`
275			`end`
276
277			`// SED - Set Decimal Flag`
278			`SED_IMP: begin`
279			`STATUS[D] = 1'b1;`
280			`end`
281
282			`// SEI - Set Interrupt Disable`
283			`SEI_IMP: begin`
284			`STATUS[I] = 1'b1;`
285			`end`
286
287			`// INC - Increment memory`
288			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
289			`result = alu_a + 1;`
290			`end`
291
292			`// INX - Increment X Register`
293			`INX_IMP: begin`
294			`result = X + 1;`
295			`end`
296
297			`// INY - Increment Y Register`
298			`INY_IMP : begin`
299			`result = Y + 1;`
300			`end`
301
302			`// DEC - Decrement memory`
303			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
304			`result = alu_a - 1;`
305			`end`
306
307			`// DEX - Decrement X register`
308			`DEX_IMP: begin`
309			`result = X - 1;`
310			`end`
311
312			`// DEY - Decrement Y Register`
313			`DEY_IMP: begin`
314			`result = Y - 1;`
315			`end`
316
317			`// ADC - Add with carry`
318			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
319			`if (alu_status[D] == 1) begin`
320			`if (A[3:0] > 9) begin`
321	152	gabrielosh	`op1 = A + 6; // A = A - 10 and A = A + 16`
322	141	creep	`end`
323	152	gabrielosh	`if (op1[7:4] > 9) begin`
324			`op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16`
325	141	creep	`end`
326			`if (alu_a[3:0] > 9) begin`
327	152	gabrielosh	`op2 = alu_a + 6;`
328	141	creep	`end`
329	152	gabrielosh	`if (op2[7:4] > 9) begin`
330			`op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16`
331	141	creep	`end`
332			`end`
333	152	gabrielosh	`{STATUS[C],result} = op1 + op2 + alu_status[C];`
334			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
335	141	creep	`STATUS[V] = 1;`
336			`else`
337			`STATUS[V] = 0;`
338	158	gabrielosh	`//$display("op1 + op2 + C = result + C (V)");`
339			`//$display("%d + %d + %b = %d + %b (%b)", op1, op2, alu_status[C],result,STATUS[C],STATUS[V]);`
340	141	creep
341			`if (alu_status[D] == 1) begin`
342			`if (result[3:0] > 9) begin`
343			`result = result[3:0] + 6; // A = A - 10 and A = A + 16`
344			`end`
345			`if (result[7:4] > 9) begin`
346			`result = result[7:4] + 6; // A = A - 10 and A = A + 16`
347			`STATUS[C] = 1;`
348			`end`
349			`end`
350			`end`
351
352			`// AND - Logical AND`
353			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
354			`result = A & alu_a;`
355			`end`
356
357			`// CMP - Compare`
358			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
359			`result = A - alu_a;`
360			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
361			`end`
362
363			`// EOR - Exclusive OR`
364			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
365	156	gabrielosh	`result = A ^ alu_a;`
366	158	gabrielosh	`//$display("op1 ^ op2 = result");`
367			`//$display("%d ^ %d = %d", op1, op2, result);`
368	141	creep	`end`
369
370			`// LDA - Load Accumulator`
371			`// LDX - Load X Register`
372			`// LDY - Load Y Register`
373			`// TSX - Transfer Stack Pointer to X`
374			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
375			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
376			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
377			`TSX_IMP : begin`
378			`result = alu_a;`
379			`end`
380
381			`// ORA - Logical OR`
382			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
383			`result = A \| alu_a;`
384			`end`
385
386			`// SBC - Subtract with Carry`
387			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
388			`if (alu_status[D] == 1) begin`
389			`if (A[3:0] > 9) begin`
390	152	gabrielosh	`op1 = A + 6; // A = A - 10 and A = A + 16`
391	141	creep	`end`
392	152	gabrielosh	`if (op1[7:4] > 9) begin`
393			`op1 = op1[7:4] + 6; // A = A - 10 and A = A + 16`
394	141	creep	`end`
395			`if (alu_a[3:0] > 9) begin`
396	152	gabrielosh	`op2 = alu_a + 6;`
397	141	creep	`end`
398	152	gabrielosh	`if (op2[7:4] > 9) begin`
399			`op2 = op2[7:4] + 6; // A = A - 10 and A = A + 16`
400	141	creep	`end`
401			`end`
402
403	152	gabrielosh	`{STATUS[C],result} = op1 - op2 - ~alu_status[C];`
404
405			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
406	141	creep	`STATUS[V] = 1;`
407			`else`
408			`STATUS[V] = 0;`
409			`end`
410
411			`// ASL - Arithmetic Shift Left`
412			`ASL_ACC : begin`
413	145	gabrielosh	`//{STATUS[C],result} = A << 1;`
414			`{STATUS[C],result} = {A,1'b0};`
415	141	creep	`end`
416			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
417	145	gabrielosh	`//{STATUS[C],result} = alu_a << 1;`
418			`{STATUS[C],result} = {alu_a,1'b0};`
419	141	creep	`end`
420
421			`// LSR - Logical Shift Right`
422			`LSR_ACC: begin`
423	145	gabrielosh	`//{result, STATUS[C]} = A >> 1;`
424			`{result,STATUS[C]} = {1'b0,A};`
425	141	creep	`end`
426			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
427	145	gabrielosh	`//{result, STATUS[C]} = alu_a >> 1;`
428			`{result,STATUS[C]} = {1'b0,alu_a};`
429	141	creep	`end`
430
431			`// ROL - Rotate Left`
432			`ROL_ACC : begin`
433	152	gabrielosh	`{STATUS[C],result} = {A,alu_status[C]};`
434	141	creep	`end`
435			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
436			`{STATUS[C],result} = {alu_a,alu_status[C]};`
437			`end`
438
439	152	gabrielosh	`// ROR - Rotate Right`
440	141	creep	`ROR_ACC : begin`
441			`{result,STATUS[C]} = {alu_status[C],A};`
442			`end`
443			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
444			`{result, STATUS[C]} = {alu_status[C], alu_a};`
445			`end`
446
447			`// CPX - Compare X Register`
448			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
449			`result = X - alu_a;`
450			`STATUS[C] = (X >= alu_a) ? 1 : 0;`
451			`end`
452
453			`// CPY - Compare Y Register`
454			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
455			`result = Y - alu_a;`
456			`STATUS[C] = (Y >= alu_a) ? 1 : 0;`
457			`end`
458
459			`default: begin // NON-DEFAULT OPCODES FALL HERE`
460	142	gabrielosh	`end`
461	141	creep	`endcase`
462	142	gabrielosh	`STATUS[Z] = (result == 0) ? 1 : 0;`
463			`STATUS[N] = result[7];`
464	141	creep	`end`
465
466			`endmodule`
467

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 159