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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
 
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                X <= 0;
                Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
                        begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :
                        begin
                                alu_status <= STATUS;
                        end
                        PHA_IMP :
                        begin
                                alu_result <= result;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 1;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
        op1      = A;
        op2      = alu_a;
        result    = alu_result;
        STATUS[N] = alu_status[N];
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
        STATUS[Z] = alu_status[Z];
        STATUS[N] = alu_status[N];
        STATUS[5] = 1;
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                BRK_IMP: begin
                        STATUS[B] = 1'b1;
                end
 
                // CLC - Clear Carry Flag
                CLC_IMP: begin
                        STATUS[C] = 1'b0;
                end
 
                // CLD - Clear Decimal Flag
                CLD_IMP: begin
                        STATUS[D] = 1'b0;
                end
 
                // CLI - Clear Interrupt Disable
                CLI_IMP: begin
                        STATUS[I] = 1'b0;
                end
 
                // CLV - Clear Overflow Flag
                CLV_IMP: begin
                        STATUS[V] = 1'b0;
                end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                PLP_IMP, RTI_IMP: begin
                        STATUS = alu_a;
                end
 
                PLA_IMP : begin
                        result = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        result = X;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        result = Y;
                end
 
                // SEC - Set Carry Flag
                SEC_IMP: begin
                        STATUS[C] = 1'b1;
                end
 
                // SED - Set Decimal Flag
                SED_IMP: begin
                        STATUS[D] = 1'b1;
                end
 
                // SEI - Set Interrupt Disable
                SEI_IMP: begin
                        STATUS[I] = 1'b1;
                end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        result = X + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        result = Y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        result = X - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        result = Y - 1;
                end
 
                // ADC - Add with carry
                // TODO: verify synthesis for % operand
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                        end
                        else
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        result = A - alu_a;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a;
                        //$display("op1 ^ op2 = result");
                        //$display("%d  ^ %d  = %d", op1, op2, result);
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
/*                      if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdl = bcdl - 10; // A = A - 10 and A = A + 16
                                        bcdh = bcdh + 1; // A = A - 10 and A = A + 16
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh - 10;
                                end
                                result = {bcdh[3:0],bcdl[3:0]};
                        end
                        else begin
                                {STATUS[C],result} = op1 - op2 - ~alu_status[C];
                        end
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                                if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                        end
                        else
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
*/
                        if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                        end
                        else
                                {STATUS[C],result} = op1 - op2 - ~alu_status[C];
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
 
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        {STATUS[C],result} = {A,alu_status[C]};
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right
                ROR_ACC : begin
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        result = X - alu_a;
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        result = Y - alu_a;
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2	152	gabrielosh	`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18	141	creep	`////////////////////////////////////////////////////////////////////////////`
19	152	gabrielosh	`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	141	creep	`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61			`reg [7:0] A;`
62			`reg [7:0] X;`
63			`reg [7:0] Y;`
64
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67	152	gabrielosh	`reg [7:0] op1;`
68			`reg [7:0] op2;`
69	161	gabrielosh	`reg [7:0] bcdl;`
70			`reg [7:0] bcdh;`
71	141	creep
72	161	gabrielosh
73	141	creep	`include "t6507lp_package.v"
74
75			`always @ (posedge clk or negedge reset_n)`
76			`begin`
77			`if (reset_n == 0) begin`
78			`alu_result <= 0;`
79			`alu_status[C] <= 0;`
80			`alu_status[N] <= 0;`
81			`alu_status[V] <= 0;`
82	148	gabrielosh	`alu_status[5] <= 1;`
83	141	creep	`alu_status[Z] <= 1;`
84			`alu_status[I] <= 0;`
85			`alu_status[B] <= 0;`
86			`alu_status[D] <= 0;`
87			`A <= 0;`
88			`X <= 0;`
89			`Y <= 0;`
90			`alu_x <= 0;`
91			`alu_y <= 0;`
92			`end`
93			`else if ( alu_enable == 1 ) begin`
94			`case (alu_opcode)`
95			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
96			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
97			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
98			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
99			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
100			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
101			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :`
102			`begin`
103			`A <= result;`
104			`alu_result <= result;`
105			`alu_status <= STATUS;`
106			`end`
107			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
108			`begin`
109			`X <= result;`
110			`alu_x <= result;`
111			`alu_status <= STATUS;`
112			`end`
113			`TXS_IMP :`
114			`begin`
115	148	gabrielosh	`X <= result;`
116			`alu_x <= result;`
117	141	creep	`end`
118			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
119			`begin`
120			`Y <= result;`
121			`alu_y <= result;`
122			`alu_status <= STATUS;`
123			`end`
124	148	gabrielosh	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
125			`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :`
126	141	creep	`begin`
127			`alu_status <= STATUS;`
128			`end`
129	158	gabrielosh	`PHA_IMP :`
130			`begin`
131			`alu_result <= result;`
132			`end`
133	141	creep	`SEC_IMP :`
134			`begin`
135			`alu_status[C] <= 1;`
136			`end`
137			`SED_IMP :`
138			`begin`
139			`alu_status[D] <= 1;`
140			`end`
141			`SEI_IMP :`
142			`begin`
143			`alu_status[I] <= 1;`
144			`end`
145			`CLC_IMP :`
146			`begin`
147			`alu_status[C] <= 0;`
148			`end`
149			`CLD_IMP :`
150			`begin`
151			`alu_status[D] <= 0;`
152			`end`
153			`CLI_IMP :`
154			`begin`
155			`alu_status[I] <= 0;`
156			`end`
157			`CLV_IMP :`
158			`begin`
159			`alu_status[V] <= 0;`
160			`end`
161			`BRK_IMP :`
162			`begin`
163	154	gabrielosh	`alu_status[B] <= 1;`
164	141	creep	`end`
165			`PLP_IMP, RTI_IMP :`
166			`begin`
167	150	gabrielosh	`alu_status[C] <= alu_a[C];`
168			`alu_status[Z] <= alu_a[Z];`
169			`alu_status[I] <= alu_a[I];`
170			`alu_status[D] <= alu_a[D];`
171			`alu_status[B] <= alu_a[B];`
172			`alu_status[V] <= alu_a[V];`
173			`alu_status[N] <= alu_a[N];`
174	141	creep	`end`
175			`BIT_ZPG, BIT_ABS :`
176			`begin`
177			`alu_status[Z] <= STATUS[Z];`
178			`alu_status[V] <= alu_a[6];`
179			`alu_status[N] <= alu_a[7];`
180			`end`
181	148	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,`
182			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,`
183			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
184	141	creep	`begin`
185			`alu_result <= result;`
186			`alu_status <= STATUS;`
187			`end`
188			`default : begin`
189			`//$display("ERROR");`
190			`end`
191			`endcase`
192			`end`
193			`end`
194
195			`always @ (*) begin`
196	152	gabrielosh	`op1 = A;`
197			`op2 = alu_a;`
198	150	gabrielosh	`result = alu_result;`
199			`STATUS[N] = alu_status[N];`
200			`STATUS[C] = alu_status[C];`
201			`STATUS[V] = alu_status[V];`
202			`STATUS[B] = alu_status[B];`
203			`STATUS[I] = alu_status[I];`
204			`STATUS[D] = alu_status[D];`
205			`STATUS[Z] = alu_status[Z];`
206			`STATUS[N] = alu_status[N];`
207	151	gabrielosh	`STATUS[5] = 1;`
208	141	creep
209			`case (alu_opcode)`
210			`// BIT - Bit Test`
211			`BIT_ZPG, BIT_ABS: begin`
212			`result = A & alu_a;`
213			`end`
214
215			`// BRK - Force Interrupt`
216			`BRK_IMP: begin`
217			`STATUS[B] = 1'b1;`
218			`end`
219
220			`// CLC - Clear Carry Flag`
221			`CLC_IMP: begin`
222			`STATUS[C] = 1'b0;`
223			`end`
224
225			`// CLD - Clear Decimal Flag`
226			`CLD_IMP: begin`
227			`STATUS[D] = 1'b0;`
228			`end`
229
230			`// CLI - Clear Interrupt Disable`
231			`CLI_IMP: begin`
232			`STATUS[I] = 1'b0;`
233			`end`
234
235			`// CLV - Clear Overflow Flag`
236			`CLV_IMP: begin`
237			`STATUS[V] = 1'b0;`
238			`end`
239
240			`// NOP - No Operation`
241			`//NOP_IMP: begin`
242			`// Do nothing :-D`
243			`//end`
244
245			`// PLP - Pull Processor Status Register`
246			`PLP_IMP, RTI_IMP: begin`
247			`STATUS = alu_a;`
248			`end`
249	157	gabrielosh
250			`PLA_IMP : begin`
251			`result = alu_a;`
252			`end`
253	141	creep
254			`// STA - Store Accumulator`
255			`// PHA - Push A`
256			`// TAX - Transfer Accumulator to X`
257			`// TAY - Transfer Accumulator to Y`
258			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
259			`result = A;`
260			`end`
261
262			`// STX - Store X Register`
263			`// TXA - Transfer X to Accumulator`
264			`// TXS - Transfer X to Stack pointer`
265			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
266			`result = X;`
267			`end`
268
269			`// STY - Store Y Register`
270			`// TYA - Transfer Y to Accumulator`
271			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
272			`result = Y;`
273			`end`
274
275			`// SEC - Set Carry Flag`
276			`SEC_IMP: begin`
277			`STATUS[C] = 1'b1;`
278			`end`
279
280			`// SED - Set Decimal Flag`
281			`SED_IMP: begin`
282			`STATUS[D] = 1'b1;`
283			`end`
284
285			`// SEI - Set Interrupt Disable`
286			`SEI_IMP: begin`
287			`STATUS[I] = 1'b1;`
288			`end`
289
290			`// INC - Increment memory`
291			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
292			`result = alu_a + 1;`
293			`end`
294
295			`// INX - Increment X Register`
296			`INX_IMP: begin`
297			`result = X + 1;`
298			`end`
299
300			`// INY - Increment Y Register`
301			`INY_IMP : begin`
302			`result = Y + 1;`
303			`end`
304
305			`// DEC - Decrement memory`
306			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
307			`result = alu_a - 1;`
308			`end`
309
310			`// DEX - Decrement X register`
311			`DEX_IMP: begin`
312			`result = X - 1;`
313			`end`
314
315			`// DEY - Decrement Y Register`
316			`DEY_IMP: begin`
317			`result = Y - 1;`
318			`end`
319
320			`// ADC - Add with carry`
321	162	gabrielosh	`// TODO: verify synthesis for % operand`
322	141	creep	`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
323			`if (alu_status[D] == 1) begin`
324	161	gabrielosh	`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
325			`bcdh = A[7:4] + alu_a[7:4];`
326			`if (bcdl > 9) begin`
327	162	gabrielosh	`bcdh = bcdh + bcdl[5:4];`
328			`bcdl = bcdl % 10;`
329	141	creep	`end`
330	161	gabrielosh	`if (bcdh > 9) begin`
331			`STATUS[C] = 1;`
332	162	gabrielosh	`bcdh = bcdh % 10;`
333	161	gabrielosh	`end`
334	141	creep	`end`
335	162	gabrielosh	`else`
336	161	gabrielosh	`{STATUS[C],result} = op1 + op2 + alu_status[C];`
337	162	gabrielosh
338	152	gabrielosh	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
339	141	creep	`STATUS[V] = 1;`
340			`else`
341			`STATUS[V] = 0;`
342			`end`
343
344			`// AND - Logical AND`
345			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
346			`result = A & alu_a;`
347			`end`
348
349			`// CMP - Compare`
350			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
351			`result = A - alu_a;`
352			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
353			`end`
354
355			`// EOR - Exclusive OR`
356			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
357	156	gabrielosh	`result = A ^ alu_a;`
358	158	gabrielosh	`//$display("op1 ^ op2 = result");`
359			`//$display("%d ^ %d = %d", op1, op2, result);`
360	141	creep	`end`
361
362			`// LDA - Load Accumulator`
363			`// LDX - Load X Register`
364			`// LDY - Load Y Register`
365			`// TSX - Transfer Stack Pointer to X`
366			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
367			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
368			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
369			`TSX_IMP : begin`
370			`result = alu_a;`
371			`end`
372
373			`// ORA - Logical OR`
374			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
375			`result = A \| alu_a;`
376			`end`
377
378			`// SBC - Subtract with Carry`
379			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
380	162	gabrielosh	`/* if (alu_status[D] == 1) begin`
381	161	gabrielosh	`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
382			`bcdh = A[7:4] + alu_a[7:4];`
383			`if (bcdl > 9) begin`
384			`bcdl = bcdl - 10; // A = A - 10 and A = A + 16`
385			`bcdh = bcdh + 1; // A = A - 10 and A = A + 16`
386	141	creep	`end`
387	161	gabrielosh	`if (bcdh > 9) begin`
388			`STATUS[C] = 1;`
389			`bcdh = bcdh - 10;`
390	141	creep	`end`
391	161	gabrielosh	`result = {bcdh[3:0],bcdl[3:0]};`
392	141	creep	`end`
393	161	gabrielosh	`else begin`
394			`{STATUS[C],result} = op1 - op2 - ~alu_status[C];`
395			`end`
396	152	gabrielosh	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
397	141	creep	`STATUS[V] = 1;`
398			`else`
399			`STATUS[V] = 0;`
400	162	gabrielosh	`if (alu_status[D] == 1) begin`
401			`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
402			`bcdh = A[7:4] + alu_a[7:4];`
403			`if (bcdl > 9) begin`
404			`bcdh = bcdh + bcdl[5:4];`
405			`bcdl = bcdl % 10;`
406			`end`
407			`if (bcdh > 9) begin`
408			`STATUS[C] = 1;`
409			`bcdh = bcdh % 10;`
410			`end`
411			`end`
412			`else`
413			`{STATUS[C],result} = op1 + op2 + alu_status[C];`
414
415			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
416			`STATUS[V] = 1;`
417			`else`
418			`STATUS[V] = 0;`
419			`*/`
420			`if (alu_status[D] == 1) begin`
421			`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
422			`bcdh = A[7:4] + alu_a[7:4];`
423			`if (bcdl > 9) begin`
424			`bcdh = bcdh + bcdl[5:4];`
425			`bcdl = bcdl % 10;`
426			`end`
427			`if (bcdh > 9) begin`
428			`STATUS[C] = 1;`
429			`bcdh = bcdh % 10;`
430			`end`
431			`end`
432			`else`
433			`{STATUS[C],result} = op1 - op2 - ~alu_status[C];`
434
435			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
436			`STATUS[V] = 1;`
437			`else`
438			`STATUS[V] = 0;`
439
440	141	creep	`end`
441
442			`// ASL - Arithmetic Shift Left`
443			`ASL_ACC : begin`
444	145	gabrielosh	`//{STATUS[C],result} = A << 1;`
445			`{STATUS[C],result} = {A,1'b0};`
446	141	creep	`end`
447			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
448	145	gabrielosh	`//{STATUS[C],result} = alu_a << 1;`
449			`{STATUS[C],result} = {alu_a,1'b0};`
450	141	creep	`end`
451
452			`// LSR - Logical Shift Right`
453			`LSR_ACC: begin`
454	145	gabrielosh	`//{result, STATUS[C]} = A >> 1;`
455			`{result,STATUS[C]} = {1'b0,A};`
456	141	creep	`end`
457			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
458	145	gabrielosh	`//{result, STATUS[C]} = alu_a >> 1;`
459			`{result,STATUS[C]} = {1'b0,alu_a};`
460	141	creep	`end`
461
462			`// ROL - Rotate Left`
463			`ROL_ACC : begin`
464	152	gabrielosh	`{STATUS[C],result} = {A,alu_status[C]};`
465	141	creep	`end`
466			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
467			`{STATUS[C],result} = {alu_a,alu_status[C]};`
468			`end`
469
470	152	gabrielosh	`// ROR - Rotate Right`
471	141	creep	`ROR_ACC : begin`
472			`{result,STATUS[C]} = {alu_status[C],A};`
473			`end`
474			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
475			`{result, STATUS[C]} = {alu_status[C], alu_a};`
476			`end`
477
478			`// CPX - Compare X Register`
479			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
480			`result = X - alu_a;`
481			`STATUS[C] = (X >= alu_a) ? 1 : 0;`
482			`end`
483
484			`// CPY - Compare Y Register`
485			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
486			`result = Y - alu_a;`
487			`STATUS[C] = (Y >= alu_a) ? 1 : 0;`
488			`end`
489
490			`default: begin // NON-DEFAULT OPCODES FALL HERE`
491	142	gabrielosh	`end`
492	141	creep	`endcase`
493	142	gabrielosh	`STATUS[Z] = (result == 0) ? 1 : 0;`
494			`STATUS[N] = result[7];`
495	141	creep	`end`
496
497			`endmodule`
498

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