URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 166

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                X <= 0;
                Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
                        begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
                        begin
                                alu_status <= STATUS;
                        end
                        PHA_IMP :
                        begin
                                alu_result <= result;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 1;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        PHP_IMP : begin
                        end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
        op1      = A;
        op2      = alu_a;
        result    = alu_result;
        STATUS[N] = alu_status[N];
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
        STATUS[Z] = alu_status[Z];
        STATUS[N] = alu_status[N];
        STATUS[5] = 1;
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                BRK_IMP: begin
                        STATUS[B] = 1'b1;
                end
 
                // CLC - Clear Carry Flag
                CLC_IMP: begin
                        STATUS[C] = 1'b0;
                end
 
                // CLD - Clear Decimal Flag
                CLD_IMP: begin
                        STATUS[D] = 1'b0;
                end
 
                // CLI - Clear Interrupt Disable
                CLI_IMP: begin
                        STATUS[I] = 1'b0;
                end
 
                // CLV - Clear Overflow Flag
                CLV_IMP: begin
                        STATUS[V] = 1'b0;
                end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                PLP_IMP, RTI_IMP: begin
                        STATUS = alu_a;
                end
 
                PLA_IMP : begin
                        result = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        result = X;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        result = Y;
                end
 
                // SEC - Set Carry Flag
                SEC_IMP: begin
                        STATUS[C] = 1'b1;
                end
 
                // SED - Set Decimal Flag
                SED_IMP: begin
                        STATUS[D] = 1'b1;
                end
 
                // SEI - Set Interrupt Disable
                SEI_IMP: begin
                        STATUS[I] = 1'b1;
                end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        result = X + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        result = Y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        result = X - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        result = Y - 1;
                end
 
                // ADC - Add with carry
                // TODO: verify synthesis for % operand
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                $display("MODO DECIMAL");
                                AL = A[3:0] + alu_a[3:0] + alu_status[C];
                                AH = A[7:4] + alu_a[7:4];
                                $display("AL = %h", AL);
                                $display("AH = %h", AH);
                                if (AL > 9) begin
                                        bcdh = AH + (AL / 10);
                                        bcdl = AL % 10;
                                end
                                if (AH > 9) begin
                                        STATUS[C] = 1;
                                        bcdh2 = bcdh % 10;
                                end
                                $display("bcdh = %h", bcdh);
                                $display("bcdl = %h", bcdl);
                                result = {bcdh2[3:0],bcdl[3:0]};
                                $display("result = %h", result);
                        end
                        else begin
                                $display("MODO NORMAL");
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
                        end
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        result = A - alu_a;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a;
                        //$display("op1 ^ op2 = result");
                        //$display("%d  ^ %d  = %d", op1, op2, result);
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
/*                      if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdl = bcdl - 10; // A = A - 10 and A = A + 16
                                        bcdh = bcdh + 1; // A = A - 10 and A = A + 16
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh - 10;
                                end
                                result = {bcdh[3:0],bcdl[3:0]};
                        end
                        else begin
                                {STATUS[C],result} = op1 - op2 - ~alu_status[C];
                        end
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                                if (alu_status[D] == 1) begin
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
                                bcdh = A[7:4] + alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                        end
                        else
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
*/
                        if (alu_status[D] == 1) begin
                                bcdl = A[3:0] - alu_a[3:0] - ~alu_status[C];
                                bcdh = A[7:4] - alu_a[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                                result = {bcdh[3:0],bcdl[3:0]};
                        end
                        else
                                {STATUS[C],result} = op1 - op2 - ( 1 - alu_status[C] );
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
 
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        {STATUS[C],result} = {A,alu_status[C]};
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right
                ROR_ACC : begin
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        result = X - alu_a;
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        result = Y - alu_a;
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2	152	gabrielosh	`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18	141	creep	`////////////////////////////////////////////////////////////////////////////`
19	152	gabrielosh	`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	141	creep	`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61			`reg [7:0] A;`
62			`reg [7:0] X;`
63			`reg [7:0] Y;`
64
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67	152	gabrielosh	`reg [7:0] op1;`
68			`reg [7:0] op2;`
69	161	gabrielosh	`reg [7:0] bcdl;`
70			`reg [7:0] bcdh;`
71	164	gabrielosh	`reg [7:0] bcdh2;`
72			`reg [7:0] AL;`
73			`reg [7:0] AH;`
74	141	creep
75			`include "t6507lp_package.v"
76
77			`always @ (posedge clk or negedge reset_n)`
78			`begin`
79			`if (reset_n == 0) begin`
80			`alu_result <= 0;`
81			`alu_status[C] <= 0;`
82			`alu_status[N] <= 0;`
83			`alu_status[V] <= 0;`
84	148	gabrielosh	`alu_status[5] <= 1;`
85	141	creep	`alu_status[Z] <= 1;`
86			`alu_status[I] <= 0;`
87			`alu_status[B] <= 0;`
88			`alu_status[D] <= 0;`
89			`A <= 0;`
90			`X <= 0;`
91			`Y <= 0;`
92			`alu_x <= 0;`
93			`alu_y <= 0;`
94			`end`
95			`else if ( alu_enable == 1 ) begin`
96			`case (alu_opcode)`
97			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
98			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
99			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
100			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
101			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
102			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
103			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :`
104			`begin`
105			`A <= result;`
106			`alu_result <= result;`
107			`alu_status <= STATUS;`
108			`end`
109			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
110			`begin`
111			`X <= result;`
112			`alu_x <= result;`
113			`alu_status <= STATUS;`
114			`end`
115			`TXS_IMP :`
116			`begin`
117	148	gabrielosh	`X <= result;`
118			`alu_x <= result;`
119	141	creep	`end`
120			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
121			`begin`
122			`Y <= result;`
123			`alu_y <= result;`
124			`alu_status <= STATUS;`
125			`end`
126	148	gabrielosh	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
127	165	gabrielosh	`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :`
128	141	creep	`begin`
129			`alu_status <= STATUS;`
130			`end`
131	158	gabrielosh	`PHA_IMP :`
132			`begin`
133			`alu_result <= result;`
134			`end`
135	141	creep	`SEC_IMP :`
136			`begin`
137			`alu_status[C] <= 1;`
138			`end`
139			`SED_IMP :`
140			`begin`
141			`alu_status[D] <= 1;`
142			`end`
143			`SEI_IMP :`
144			`begin`
145			`alu_status[I] <= 1;`
146			`end`
147			`CLC_IMP :`
148			`begin`
149			`alu_status[C] <= 0;`
150			`end`
151			`CLD_IMP :`
152			`begin`
153			`alu_status[D] <= 0;`
154			`end`
155			`CLI_IMP :`
156			`begin`
157			`alu_status[I] <= 0;`
158			`end`
159			`CLV_IMP :`
160			`begin`
161			`alu_status[V] <= 0;`
162			`end`
163			`BRK_IMP :`
164			`begin`
165	154	gabrielosh	`alu_status[B] <= 1;`
166	141	creep	`end`
167			`PLP_IMP, RTI_IMP :`
168			`begin`
169	150	gabrielosh	`alu_status[C] <= alu_a[C];`
170			`alu_status[Z] <= alu_a[Z];`
171			`alu_status[I] <= alu_a[I];`
172			`alu_status[D] <= alu_a[D];`
173			`alu_status[B] <= alu_a[B];`
174			`alu_status[V] <= alu_a[V];`
175			`alu_status[N] <= alu_a[N];`
176	141	creep	`end`
177			`BIT_ZPG, BIT_ABS :`
178			`begin`
179			`alu_status[Z] <= STATUS[Z];`
180			`alu_status[V] <= alu_a[6];`
181			`alu_status[N] <= alu_a[7];`
182			`end`
183	148	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,`
184			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,`
185			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
186	141	creep	`begin`
187			`alu_result <= result;`
188			`alu_status <= STATUS;`
189			`end`
190	165	gabrielosh	`PHP_IMP : begin`
191			`end`
192	141	creep	`default : begin`
193			`//$display("ERROR");`
194			`end`
195			`endcase`
196			`end`
197			`end`
198
199			`always @ (*) begin`
200	152	gabrielosh	`op1 = A;`
201			`op2 = alu_a;`
202	150	gabrielosh	`result = alu_result;`
203			`STATUS[N] = alu_status[N];`
204			`STATUS[C] = alu_status[C];`
205			`STATUS[V] = alu_status[V];`
206			`STATUS[B] = alu_status[B];`
207			`STATUS[I] = alu_status[I];`
208			`STATUS[D] = alu_status[D];`
209			`STATUS[Z] = alu_status[Z];`
210			`STATUS[N] = alu_status[N];`
211	151	gabrielosh	`STATUS[5] = 1;`
212	141	creep
213			`case (alu_opcode)`
214			`// BIT - Bit Test`
215			`BIT_ZPG, BIT_ABS: begin`
216			`result = A & alu_a;`
217			`end`
218
219			`// BRK - Force Interrupt`
220			`BRK_IMP: begin`
221			`STATUS[B] = 1'b1;`
222			`end`
223
224			`// CLC - Clear Carry Flag`
225			`CLC_IMP: begin`
226			`STATUS[C] = 1'b0;`
227			`end`
228
229			`// CLD - Clear Decimal Flag`
230			`CLD_IMP: begin`
231			`STATUS[D] = 1'b0;`
232			`end`
233
234			`// CLI - Clear Interrupt Disable`
235			`CLI_IMP: begin`
236			`STATUS[I] = 1'b0;`
237			`end`
238
239			`// CLV - Clear Overflow Flag`
240			`CLV_IMP: begin`
241			`STATUS[V] = 1'b0;`
242			`end`
243
244			`// NOP - No Operation`
245			`//NOP_IMP: begin`
246			`// Do nothing :-D`
247			`//end`
248
249			`// PLP - Pull Processor Status Register`
250			`PLP_IMP, RTI_IMP: begin`
251			`STATUS = alu_a;`
252			`end`
253	157	gabrielosh
254			`PLA_IMP : begin`
255			`result = alu_a;`
256			`end`
257	141	creep
258			`// STA - Store Accumulator`
259			`// PHA - Push A`
260			`// TAX - Transfer Accumulator to X`
261			`// TAY - Transfer Accumulator to Y`
262			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
263			`result = A;`
264			`end`
265
266			`// STX - Store X Register`
267			`// TXA - Transfer X to Accumulator`
268			`// TXS - Transfer X to Stack pointer`
269			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
270			`result = X;`
271			`end`
272
273			`// STY - Store Y Register`
274			`// TYA - Transfer Y to Accumulator`
275			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
276			`result = Y;`
277			`end`
278
279			`// SEC - Set Carry Flag`
280			`SEC_IMP: begin`
281			`STATUS[C] = 1'b1;`
282			`end`
283
284			`// SED - Set Decimal Flag`
285			`SED_IMP: begin`
286			`STATUS[D] = 1'b1;`
287			`end`
288
289			`// SEI - Set Interrupt Disable`
290			`SEI_IMP: begin`
291			`STATUS[I] = 1'b1;`
292			`end`
293
294			`// INC - Increment memory`
295			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
296			`result = alu_a + 1;`
297			`end`
298
299			`// INX - Increment X Register`
300			`INX_IMP: begin`
301			`result = X + 1;`
302			`end`
303
304			`// INY - Increment Y Register`
305			`INY_IMP : begin`
306			`result = Y + 1;`
307			`end`
308
309			`// DEC - Decrement memory`
310			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
311			`result = alu_a - 1;`
312			`end`
313
314			`// DEX - Decrement X register`
315			`DEX_IMP: begin`
316			`result = X - 1;`
317			`end`
318
319			`// DEY - Decrement Y Register`
320			`DEY_IMP: begin`
321			`result = Y - 1;`
322			`end`
323
324			`// ADC - Add with carry`
325	162	gabrielosh	`// TODO: verify synthesis for % operand`
326	141	creep	`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
327			`if (alu_status[D] == 1) begin`
328	165	gabrielosh	`$display("MODO DECIMAL");`
329	164	gabrielosh	`AL = A[3:0] + alu_a[3:0] + alu_status[C];`
330			`AH = A[7:4] + alu_a[7:4];`
331	165	gabrielosh	`$display("AL = %h", AL);`
332			`$display("AH = %h", AH);`
333	164	gabrielosh	`if (AL > 9) begin`
334			`bcdh = AH + (AL / 10);`
335			`bcdl = AL % 10;`
336	141	creep	`end`
337	164	gabrielosh	`if (AH > 9) begin`
338	161	gabrielosh	`STATUS[C] = 1;`
339	164	gabrielosh	`bcdh2 = bcdh % 10;`
340	161	gabrielosh	`end`
341	165	gabrielosh	`$display("bcdh = %h", bcdh);`
342			`$display("bcdl = %h", bcdl);`
343	164	gabrielosh	`result = {bcdh2[3:0],bcdl[3:0]};`
344	165	gabrielosh	`$display("result = %h", result);`
345	141	creep	`end`
346	165	gabrielosh	`else begin`
347			`$display("MODO NORMAL");`
348	161	gabrielosh	`{STATUS[C],result} = op1 + op2 + alu_status[C];`
349	165	gabrielosh	`end`
350	162	gabrielosh
351	152	gabrielosh	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
352	141	creep	`STATUS[V] = 1;`
353			`else`
354			`STATUS[V] = 0;`
355			`end`
356
357			`// AND - Logical AND`
358			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
359			`result = A & alu_a;`
360			`end`
361
362			`// CMP - Compare`
363			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
364			`result = A - alu_a;`
365			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
366			`end`
367
368			`// EOR - Exclusive OR`
369			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
370	156	gabrielosh	`result = A ^ alu_a;`
371	158	gabrielosh	`//$display("op1 ^ op2 = result");`
372			`//$display("%d ^ %d = %d", op1, op2, result);`
373	141	creep	`end`
374
375			`// LDA - Load Accumulator`
376			`// LDX - Load X Register`
377			`// LDY - Load Y Register`
378			`// TSX - Transfer Stack Pointer to X`
379			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
380			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
381			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
382			`TSX_IMP : begin`
383			`result = alu_a;`
384			`end`
385
386			`// ORA - Logical OR`
387			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
388			`result = A \| alu_a;`
389			`end`
390
391			`// SBC - Subtract with Carry`
392			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
393	162	gabrielosh	`/* if (alu_status[D] == 1) begin`
394	161	gabrielosh	`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
395			`bcdh = A[7:4] + alu_a[7:4];`
396			`if (bcdl > 9) begin`
397			`bcdl = bcdl - 10; // A = A - 10 and A = A + 16`
398			`bcdh = bcdh + 1; // A = A - 10 and A = A + 16`
399	141	creep	`end`
400	161	gabrielosh	`if (bcdh > 9) begin`
401			`STATUS[C] = 1;`
402			`bcdh = bcdh - 10;`
403	141	creep	`end`
404	161	gabrielosh	`result = {bcdh[3:0],bcdl[3:0]};`
405	141	creep	`end`
406	161	gabrielosh	`else begin`
407			`{STATUS[C],result} = op1 - op2 - ~alu_status[C];`
408			`end`
409	152	gabrielosh	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
410	141	creep	`STATUS[V] = 1;`
411			`else`
412			`STATUS[V] = 0;`
413	162	gabrielosh	`if (alu_status[D] == 1) begin`
414			`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
415			`bcdh = A[7:4] + alu_a[7:4];`
416			`if (bcdl > 9) begin`
417			`bcdh = bcdh + bcdl[5:4];`
418			`bcdl = bcdl % 10;`
419			`end`
420			`if (bcdh > 9) begin`
421			`STATUS[C] = 1;`
422			`bcdh = bcdh % 10;`
423			`end`
424			`end`
425			`else`
426			`{STATUS[C],result} = op1 + op2 + alu_status[C];`
427
428			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
429			`STATUS[V] = 1;`
430			`else`
431			`STATUS[V] = 0;`
432			`*/`
433			`if (alu_status[D] == 1) begin`
434	163	gabrielosh	`bcdl = A[3:0] - alu_a[3:0] - ~alu_status[C];`
435			`bcdh = A[7:4] - alu_a[7:4];`
436	162	gabrielosh	`if (bcdl > 9) begin`
437			`bcdh = bcdh + bcdl[5:4];`
438			`bcdl = bcdl % 10;`
439			`end`
440			`if (bcdh > 9) begin`
441			`STATUS[C] = 1;`
442			`bcdh = bcdh % 10;`
443			`end`
444	163	gabrielosh	`result = {bcdh[3:0],bcdl[3:0]};`
445	162	gabrielosh	`end`
446			`else`
447	166	gabrielosh	`{STATUS[C],result} = op1 - op2 - ( 1 - alu_status[C] );`
448	162	gabrielosh
449			`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
450			`STATUS[V] = 1;`
451			`else`
452			`STATUS[V] = 0;`
453
454	141	creep	`end`
455
456			`// ASL - Arithmetic Shift Left`
457			`ASL_ACC : begin`
458	145	gabrielosh	`//{STATUS[C],result} = A << 1;`
459			`{STATUS[C],result} = {A,1'b0};`
460	141	creep	`end`
461			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
462	145	gabrielosh	`//{STATUS[C],result} = alu_a << 1;`
463			`{STATUS[C],result} = {alu_a,1'b0};`
464	141	creep	`end`
465
466			`// LSR - Logical Shift Right`
467			`LSR_ACC: begin`
468	145	gabrielosh	`//{result, STATUS[C]} = A >> 1;`
469			`{result,STATUS[C]} = {1'b0,A};`
470	141	creep	`end`
471			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
472	145	gabrielosh	`//{result, STATUS[C]} = alu_a >> 1;`
473			`{result,STATUS[C]} = {1'b0,alu_a};`
474	141	creep	`end`
475
476			`// ROL - Rotate Left`
477			`ROL_ACC : begin`
478	152	gabrielosh	`{STATUS[C],result} = {A,alu_status[C]};`
479	141	creep	`end`
480			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
481			`{STATUS[C],result} = {alu_a,alu_status[C]};`
482			`end`
483
484	152	gabrielosh	`// ROR - Rotate Right`
485	141	creep	`ROR_ACC : begin`
486			`{result,STATUS[C]} = {alu_status[C],A};`
487			`end`
488			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
489			`{result, STATUS[C]} = {alu_status[C], alu_a};`
490			`end`
491
492			`// CPX - Compare X Register`
493			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
494			`result = X - alu_a;`
495			`STATUS[C] = (X >= alu_a) ? 1 : 0;`
496			`end`
497
498			`// CPY - Compare Y Register`
499			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
500			`result = Y - alu_a;`

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 166