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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 169

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1 141 creep
////////////////////////////////////////////////////////////////////////////
2 152 gabrielosh
////                                                                    ////
3
//// T6507LP IP Core                                                    ////
4
////                                                                    ////
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//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
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////                                                                    ////
8
//// Description                                                        ////
9
//// 6507 ALU                                                           ////
10
////                                                                    ////
11
//// To Do:                                                             ////
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//// - Search for TODO                                                  ////
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////                                                                    ////
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//// Author(s):                                                         ////
15
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
17
////                                                                    ////
18 141 creep
////////////////////////////////////////////////////////////////////////////
19 152 gabrielosh
////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
21
////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
25
//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
27
//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
37
//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
43 141 creep
////////////////////////////////////////////////////////////////////////////
44
 
45
`include "timescale.v"
46
 
47
// TODO: verify code identation
48
 
49
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
50
 
51
input wire       clk;
52
input wire       reset_n;
53
input wire       alu_enable;
54
input wire [7:0] alu_opcode;
55
input wire [7:0] alu_a;
56
output reg [7:0] alu_result;
57
output reg [7:0] alu_status;
58
output reg [7:0] alu_x;
59
output reg [7:0] alu_y;
60
 
61
reg [7:0] A;
62
reg [7:0] X;
63
reg [7:0] Y;
64
 
65
reg [7:0] STATUS;
66
reg [7:0] result;
67 152 gabrielosh
reg [7:0] op1;
68
reg [7:0] op2;
69 161 gabrielosh
reg [7:0] bcdl;
70
reg [7:0] bcdh;
71 164 gabrielosh
reg [7:0] bcdh2;
72
reg [7:0] AL;
73
reg [7:0] AH;
74 141 creep
 
75
`include "t6507lp_package.v"
76
 
77
always @ (posedge clk or negedge reset_n)
78
begin
79
        if (reset_n == 0) begin
80
                alu_result <= 0;
81
                alu_status[C] <= 0;
82
                alu_status[N] <= 0;
83
                alu_status[V] <= 0;
84 148 gabrielosh
                alu_status[5] <= 1;
85 141 creep
                alu_status[Z] <= 1;
86
                alu_status[I] <= 0;
87
                alu_status[B] <= 0;
88
                alu_status[D] <= 0;
89
                A <= 0;
90
                X <= 0;
91
                Y <= 0;
92
                alu_x <= 0;
93
                alu_y <= 0;
94
        end
95
        else if ( alu_enable == 1 ) begin
96
                case (alu_opcode)
97
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
98
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
99
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
100
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
101
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
102
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
103
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
104
                        begin
105
                                A          <= result;
106
                                alu_result <= result;
107
                                alu_status <= STATUS;
108
                        end
109
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
110
                        begin
111
                                X          <= result;
112
                                alu_x      <= result;
113
                                alu_status <= STATUS;
114
                        end
115
                        TXS_IMP :
116
                        begin
117 148 gabrielosh
                                X          <= result;
118
                                alu_x      <= result;
119 141 creep
                        end
120
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
121
                        begin
122
                                Y          <= result;
123
                                alu_y      <= result;
124
                                alu_status <= STATUS;
125
                        end
126 148 gabrielosh
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
127 165 gabrielosh
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
128 141 creep
                        begin
129
                                alu_status <= STATUS;
130
                        end
131 158 gabrielosh
                        PHA_IMP :
132
                        begin
133
                                alu_result <= result;
134
                        end
135 141 creep
                        SEC_IMP :
136
                        begin
137
                                alu_status[C] <= 1;
138
                        end
139
                        SED_IMP :
140
                        begin
141
                                alu_status[D] <= 1;
142
                        end
143
                        SEI_IMP :
144
                        begin
145
                                alu_status[I] <= 1;
146
                        end
147
                        CLC_IMP :
148
                        begin
149
                                alu_status[C] <= 0;
150
                        end
151
                        CLD_IMP :
152
                        begin
153
                                alu_status[D] <= 0;
154
                        end
155
                        CLI_IMP :
156
                        begin
157
                                alu_status[I] <= 0;
158
                        end
159
                        CLV_IMP :
160
                        begin
161
                                alu_status[V] <= 0;
162
                        end
163
                        BRK_IMP :
164
                        begin
165 154 gabrielosh
                                alu_status[B] <= 1;
166 141 creep
                        end
167 168 gabrielosh
                        PLP_IMP : //, RTI_IMP :
168 141 creep
                        begin
169 150 gabrielosh
                                alu_status[C] <= alu_a[C];
170
                                alu_status[Z] <= alu_a[Z];
171
                                alu_status[I] <= alu_a[I];
172
                                alu_status[D] <= alu_a[D];
173
                                alu_status[B] <= alu_a[B];
174
                                alu_status[V] <= alu_a[V];
175
                                alu_status[N] <= alu_a[N];
176 141 creep
                        end
177
                        BIT_ZPG, BIT_ABS :
178
                        begin
179
                                alu_status[Z] <= STATUS[Z];
180
                                alu_status[V] <= alu_a[6];
181
                                alu_status[N] <= alu_a[7];
182
                        end
183 148 gabrielosh
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
184
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
185
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
186 141 creep
                        begin
187
                                alu_result <= result;
188
                                alu_status <= STATUS;
189
                        end
190 165 gabrielosh
                        PHP_IMP : begin
191
                        end
192 141 creep
                        default : begin
193
                                //$display("ERROR");
194
                        end
195
                endcase
196
        end
197
end
198
 
199
always @ (*) begin
200 152 gabrielosh
        op1      = A;
201
        op2      = alu_a;
202 150 gabrielosh
        result    = alu_result;
203
        STATUS[N] = alu_status[N];
204
        STATUS[C] = alu_status[C];
205
        STATUS[V] = alu_status[V];
206
        STATUS[B] = alu_status[B];
207
        STATUS[I] = alu_status[I];
208
        STATUS[D] = alu_status[D];
209
        STATUS[Z] = alu_status[Z];
210
        STATUS[N] = alu_status[N];
211 151 gabrielosh
        STATUS[5] = 1;
212 141 creep
 
213
        case (alu_opcode)
214
                // BIT - Bit Test
215
                BIT_ZPG, BIT_ABS: begin
216
                        result = A & alu_a;
217
                end
218
 
219
                // BRK - Force Interrupt
220
                BRK_IMP: begin
221
                        STATUS[B] = 1'b1;
222
                end
223
 
224
                // CLC - Clear Carry Flag
225
                CLC_IMP: begin
226
                        STATUS[C] = 1'b0;
227
                end
228
 
229
                // CLD - Clear Decimal Flag
230
                CLD_IMP: begin
231
                        STATUS[D] = 1'b0;
232
                end
233
 
234
                // CLI - Clear Interrupt Disable
235
                CLI_IMP: begin
236
                        STATUS[I] = 1'b0;
237
                end
238
 
239
                // CLV - Clear Overflow Flag
240
                CLV_IMP: begin
241
                        STATUS[V] = 1'b0;
242
                end
243
 
244
                // NOP - No Operation
245
                //NOP_IMP: begin
246
                        // Do nothing :-D
247
                //end
248
 
249
                // PLP - Pull Processor Status Register
250 168 gabrielosh
                PLP_IMP : begin //, RTI_IMP: begin
251 141 creep
                        STATUS = alu_a;
252
                end
253 157 gabrielosh
 
254
                PLA_IMP : begin
255
                        result = alu_a;
256
                end
257 141 creep
 
258
                // STA - Store Accumulator
259
                // PHA - Push A
260
                // TAX - Transfer Accumulator to X
261
                // TAY - Transfer Accumulator to Y
262
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
263
                        result = A;
264
                end
265
 
266
                // STX - Store X Register
267
                // TXA - Transfer X to Accumulator
268
                // TXS - Transfer X to Stack pointer
269
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
270
                        result = X;
271
                end
272
 
273
                // STY - Store Y Register
274
                // TYA - Transfer Y to Accumulator
275
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
276
                        result = Y;
277
                end
278
 
279
                // SEC - Set Carry Flag
280
                SEC_IMP: begin
281
                        STATUS[C] = 1'b1;
282
                end
283
 
284
                // SED - Set Decimal Flag
285
                SED_IMP: begin
286
                        STATUS[D] = 1'b1;
287
                end
288
 
289
                // SEI - Set Interrupt Disable
290
                SEI_IMP: begin
291
                        STATUS[I] = 1'b1;
292
                end
293
 
294
                // INC - Increment memory
295
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
296
                        result = alu_a + 1;
297
                end
298
 
299
                // INX - Increment X Register
300
                INX_IMP: begin
301
                        result = X + 1;
302
                end
303
 
304
                // INY - Increment Y Register
305
                INY_IMP : begin
306
                        result = Y + 1;
307
                end
308
 
309
                // DEC - Decrement memory
310
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
311
                        result = alu_a - 1;
312
                end
313
 
314
                // DEX - Decrement X register
315
                DEX_IMP: begin
316
                        result = X - 1;
317
                end
318
 
319
                // DEY - Decrement Y Register
320
                DEY_IMP: begin
321
                        result = Y - 1;
322
                end
323
 
324
                // ADC - Add with carry
325 162 gabrielosh
                // TODO: verify synthesis for % operand
326 141 creep
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
327
                        if (alu_status[D] == 1) begin
328 169 gabrielosh
<<<<<<< .mine
329
<<<<<<< .mine
330
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
331
                                bcdh = A[7:4] + alu_a[7:4];
332
 
333
                                $write("1: bcdl %d bcdh %d\n", bcdl, bcdh);
334
 
335
                                if (bcdl > 9) begin
336
                                        //$write("\n %d \n", bcdl[6:4]);
337
                                        bcdh = bcdh + bcdl[5:4];
338
                                        bcdl = bcdl % 10;
339
=======
340
=======
341 165 gabrielosh
                                $display("MODO DECIMAL");
342 169 gabrielosh
>>>>>>> .r165
343 164 gabrielosh
                                AL = A[3:0] + alu_a[3:0] + alu_status[C];
344
                                AH = A[7:4] + alu_a[7:4];
345 165 gabrielosh
                                $display("AL = %h", AL);
346
                                $display("AH = %h", AH);
347 164 gabrielosh
                                if (AL > 9) begin
348
                                        bcdh = AH + (AL / 10);
349
                                        bcdl = AL % 10;
350 169 gabrielosh
>>>>>>> .r164
351 141 creep
                                end
352 164 gabrielosh
                                if (AH > 9) begin
353 161 gabrielosh
                                        STATUS[C] = 1;
354 164 gabrielosh
                                        bcdh2 = bcdh % 10;
355 161 gabrielosh
                                end
356 169 gabrielosh
<<<<<<< .mine
357
<<<<<<< .mine
358
 
359
                                //$write("bcdl %d bcdh %d\n", bcdl, bcdh);
360
 
361
 
362
                                result = {bcdh[3:0],bcdl[3:0]};
363
=======
364
=======
365 165 gabrielosh
                                $display("bcdh = %h", bcdh);
366
                                $display("bcdl = %h", bcdl);
367 169 gabrielosh
>>>>>>> .r165
368 164 gabrielosh
                                result = {bcdh2[3:0],bcdl[3:0]};
369 169 gabrielosh
<<<<<<< .mine
370
>>>>>>> .r164
371
=======
372 165 gabrielosh
                                $display("result = %h", result);
373 169 gabrielosh
>>>>>>> .r165
374 141 creep
                        end
375 165 gabrielosh
                        else begin
376
                                $display("MODO NORMAL");
377 161 gabrielosh
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
378 165 gabrielosh
                        end
379 162 gabrielosh
 
380 152 gabrielosh
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
381 141 creep
                                STATUS[V] = 1;
382
                        else
383
                                STATUS[V] = 0;
384
                end
385
 
386
                // AND - Logical AND
387
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
388
                        result = A & alu_a;
389
                end
390
 
391
                // CMP - Compare
392
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
393
                        result = A - alu_a;
394
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
395
                end
396
 
397
                // EOR - Exclusive OR
398
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
399 156 gabrielosh
                        result = A ^ alu_a;
400 158 gabrielosh
                        //$display("op1 ^ op2 = result");
401
                        //$display("%d  ^ %d  = %d", op1, op2, result);
402 141 creep
                end
403
 
404
                // LDA - Load Accumulator
405
                // LDX - Load X Register
406
                // LDY - Load Y Register
407
                // TSX - Transfer Stack Pointer to X
408
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
409
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
410
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
411
                TSX_IMP : begin
412
                        result = alu_a;
413
                end
414
 
415
                // ORA - Logical OR
416
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
417
                        result = A | alu_a;
418
                end
419
 
420
                // SBC - Subtract with Carry
421
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
422 162 gabrielosh
/*                      if (alu_status[D] == 1) begin
423 161 gabrielosh
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
424
                                bcdh = A[7:4] + alu_a[7:4];
425
                                if (bcdl > 9) begin
426
                                        bcdl = bcdl - 10; // A = A - 10 and A = A + 16
427
                                        bcdh = bcdh + 1; // A = A - 10 and A = A + 16
428 141 creep
                                end
429 161 gabrielosh
                                if (bcdh > 9) begin
430
                                        STATUS[C] = 1;
431
                                        bcdh = bcdh - 10;
432 141 creep
                                end
433 161 gabrielosh
                                result = {bcdh[3:0],bcdl[3:0]};
434 141 creep
                        end
435 161 gabrielosh
                        else begin
436
                                {STATUS[C],result} = op1 - op2 - ~alu_status[C];
437
                        end
438 152 gabrielosh
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
439 141 creep
                                STATUS[V] = 1;
440
                        else
441
                                STATUS[V] = 0;
442 162 gabrielosh
                                if (alu_status[D] == 1) begin
443
                                bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
444
                                bcdh = A[7:4] + alu_a[7:4];
445
                                if (bcdl > 9) begin
446
                                        bcdh = bcdh + bcdl[5:4];
447
                                        bcdl = bcdl % 10;
448
                                end
449
                                if (bcdh > 9) begin
450
                                        STATUS[C] = 1;
451
                                        bcdh = bcdh % 10;
452
                                end
453
                        end
454
                        else
455
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
456
 
457
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
458
                                STATUS[V] = 1;
459
                        else
460
                                STATUS[V] = 0;
461
*/
462
                        if (alu_status[D] == 1) begin
463 167 gabrielosh
                                bcdl = A[3:0] - alu_a[3:0] - ( 1 - alu_status[C] );
464 163 gabrielosh
                                bcdh = A[7:4] - alu_a[7:4];
465 162 gabrielosh
                                if (bcdl > 9) begin
466
                                        bcdh = bcdh + bcdl[5:4];
467
                                        bcdl = bcdl % 10;
468
                                end
469
                                if (bcdh > 9) begin
470
                                        STATUS[C] = 1;
471
                                        bcdh = bcdh % 10;
472
                                end
473 163 gabrielosh
                                result = {bcdh[3:0],bcdl[3:0]};
474 162 gabrielosh
                        end
475
                        else
476 166 gabrielosh
                                {STATUS[C],result} = op1 - op2 - ( 1 - alu_status[C] );
477 162 gabrielosh
 
478
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
479
                                STATUS[V] = 1;
480
                        else
481
                                STATUS[V] = 0;
482
 
483 141 creep
                end
484
 
485
                // ASL - Arithmetic Shift Left
486
                ASL_ACC : begin
487 145 gabrielosh
                        //{STATUS[C],result} = A << 1;
488
                        {STATUS[C],result} = {A,1'b0};
489 141 creep
                end
490
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
491 145 gabrielosh
                        //{STATUS[C],result} = alu_a << 1;
492
                        {STATUS[C],result} = {alu_a,1'b0};
493 141 creep
                end
494
 
495
                // LSR - Logical Shift Right
496
                LSR_ACC: begin
497 145 gabrielosh
                        //{result, STATUS[C]} = A >> 1;
498
                        {result,STATUS[C]} = {1'b0,A};
499 141 creep
                end
500
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
501 145 gabrielosh
                        //{result, STATUS[C]} = alu_a >> 1;
502
                        {result,STATUS[C]} = {1'b0,alu_a};
503 141 creep
                end
504
 
505
                // ROL - Rotate Left
506
                ROL_ACC : begin
507 152 gabrielosh
                        {STATUS[C],result} = {A,alu_status[C]};
508 141 creep
                end
509
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
510
                        {STATUS[C],result} = {alu_a,alu_status[C]};
511
                end
512
 
513 152 gabrielosh
                // ROR - Rotate Right
514 141 creep
                ROR_ACC : begin
515
                        {result,STATUS[C]} = {alu_status[C],A};
516
                end
517
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
518
                        {result, STATUS[C]} = {alu_status[C], alu_a};
519
                end
520
 
521
                // CPX - Compare X Register
522
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
523
                        result = X - alu_a;
524
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
525
                end
526
 
527
                // CPY - Compare Y Register
528
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
529
                        result = Y - alu_a;
530
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
531
                end
532
 
533
                default: begin // NON-DEFAULT OPCODES FALL HERE
534 142 gabrielosh
                end
535 141 creep
        endcase
536 142 gabrielosh
        STATUS[Z] = (result == 0) ? 1 : 0;
537
        STATUS[N] = result[7];
538 141 creep
end
539
 
540
endmodule
541
 

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