URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 184

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
//reg [7:0] X;
//reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
//reg C_aux;
reg sign;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                //X <= 0;
                //Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP :
                        begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                //X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                //X          <= result;
                                alu_x      <= result;
                        end
                        TXA_IMP, TYA_IMP :
                        begin
                                A          <= result;
                                alu_status <= STATUS;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                //Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
                        begin
                                alu_status <= STATUS;
                        end
                        PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                                alu_result <= result;
                        end
                        STX_ZPG, STX_ZPY, STX_ABS : begin
                                alu_x <= result;
                        end
                        STY_ZPG, STY_ZPX, STY_ABS : begin
                                alu_y <= result;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 1;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                                alu_status[5] <= 1;
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        //PHP_IMP : begin
                        //end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
if (alu_enable == 1) begin
        //op1      = A;
        op1      = A;
        op2      = alu_a;
        result    = alu_result;
        STATUS[N] = alu_status[N];
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
        STATUS[Z] = alu_status[Z];
        STATUS[5] = 1;
 
        bcdl = 0;
        bcdh = 0;
        bcdh2 = 0;
        AL = 0;
        AH = 0;
        sign = op2[7];
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        //result = A & alu_a;
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                //BRK_IMP: begin
                //      STATUS[B] = 1'b1;
                //end
 
                // CLC - Clear Carry Flag
                //CLC_IMP: begin
                //      STATUS[C] = 1'b0;
                //end
 
                // CLD - Clear Decimal Flag
                //CLD_IMP: begin
                //      STATUS[D] = 1'b0;
                //end
 
                // CLI - Clear Interrupt Disable
                //CLI_IMP: begin
                //      STATUS[I] = 1'b0;
                //end
 
                // CLV - Clear Overflow Flag
                //CLV_IMP: begin
                //      STATUS[V] = 1'b0;
                //end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                // RTI - Return from Interrupt
                //PLP_IMP, RTI_IMP: begin
                //      STATUS = alu_a;
                //end
 
                PLA_IMP : begin
                        result = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        //result = A;
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        //result = X;
                        result = alu_x;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        //result = Y;
                        result = alu_y;
                end
 
                // SEC - Set Carry Flag
                //SEC_IMP: begin
                //      STATUS[C] = 1'b1;
                //end
 
                // SED - Set Decimal Flag
                //SED_IMP: begin
                //      STATUS[D] = 1'b1;
                //end
 
                // SEI - Set Interrupt Disable
                //SEI_IMP: begin
                //      STATUS[I] = 1'b1;
                //end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        //result = X + 1;
                        result = alu_x + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        //result = Y + 1;
                        result = alu_y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        //result = X - 1;
                        result = alu_x - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        //result = Y - 1;
                        result = alu_y - 1;
                end
 
                // ADC - Add with carry
                // TODO: verify synthesis for % operand
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                //$display("MODO DECIMAL");
                                //AL = A[3:0] + alu_a[3:0] + alu_status[C];
                                AL = op1[3:0] + op2[3:0] + alu_status[C];
                                //AH = A[7:4] + alu_a[7:4];
                                AH = op1[7:4] + op2[7:4];
                                $display("AL = %d", AL);
                                $display("AH = %d", AH);
                                if (AL > 9) begin
                                        bcdh = AH + (AL / 10);
                                        bcdl = AL % 10;
                                end
                                else begin
                                        bcdh = AH;
                                        bcdl = AL;
                                end
 
                                // ok
 
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh2 = bcdh % 10;
                                end
                                else begin
                                        STATUS[C] = 0;
                                        bcdh2 = bcdh;
                                end
                                //$display("bcdh2 = %d", bcdh2);
                                //$display("bcdl = %d", bcdl);
                                result = {bcdh2[3:0],bcdl[3:0]};
                        end
                        else begin
                                //$display("MODO NORMAL");
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
                        end
 
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        //result = A & alu_a;
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        //result = A - alu_a;
                        result = A - alu_a;
                        //STATUS[C] = (A >= alu_a) ? 1 : 0;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a;
                        //result = A ^ alu_a;
                        //$display("op1 ^ op2 = result");
                        //$display("%d  ^ %d  = %d", op1, op2, result);
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        //result = A | alu_a;
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
                        if (alu_status[D] == 1) begin
/*                              //AL = A[3:0] + alu_a[3:0] + alu_status[C];
                                AL = op1[3:0] + op2[3:0] + alu_status[C];
                                //AH = A[7:4] + alu_a[7:4];
                                AH = op1[7:4] + op2[7:4];
                                if (AL > 9) begin
                                        bcdh = AH + (AL / 10);
                                        bcdl = AL % 10;
                                end
                                else begin
                                        bcdh = AH;
                                        bcdl = AL;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh2 = bcdh % 10;
                                end
                                else begin
                                        STATUS[C] = 0;
                                        bcdh2 = bcdh;
                                end
                                result = {bcdh2[3:0],bcdl[3:0]};*/
        //C := P_In(Flag_C) or not Op(0);
                                AL = {op1[3:0],alu_status[C]} - {op2[3:0],1'b1};
                                AH = {op1[7:4],1'b0} - {op2[7:4],AL[5]};
 
                                if (AL[5] == 1) begin
                                        bcdl[5:1] = AL[5:1] - 6;
                                end
                                AH = {op1[7:4],1'b0} - {op2[7:4],bcdl[6]};
                                if (AH[5] == 1) begin
                                        bcdh[5:1] = AH[5:1] - 6;
                                end
                                result = {bcdh[4:1],bcdl[4:1]};
                                STATUS[C] = ~result[7];
                        end
                        else begin
                                op2 = ~op2;
                                //$display("MODO NORMAL");
                                result = op1 + op2 + alu_status[C];
                                STATUS[C] = ~result[7];
                        end
/*                      if (alu_status[D] == 1) begin
                                bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
                                bcdh = op1[7:4] - op2[7:4];
                                if (bcdl > 9) begin
                                        bcdh = bcdh + bcdl[5:4];
                                        bcdl = bcdl % 10;
                                end
                                if (bcdh > 9) begin
                                        STATUS[C] = 1;
                                        bcdh = bcdh % 10;
                                end
                                result = {bcdh[3:0],bcdl[3:0]};
                        end
                        else begin
                                op2 = ~alu_a;
                                result = op1 + op2 + alu_status[C];
                                STATUS[C] = ~result[7];
                        end
*/
 
                        if ((op1[7] == sign) && (op1[7] != result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
 
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        //{STATUS[C],result} = {A,1'b0};
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        //{result,STATUS[C]} = {1'b0,A};
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        //{STATUS[C],result} = {A,alu_status[C]};
                        {STATUS[C],result} = {A,alu_status[C]};
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right
                ROR_ACC : begin
                        //{result,STATUS[C]} = {alu_status[C],A};
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        //result = X - alu_a;
                        result = alu_x - alu_a;
                        //STATUS[C] = (X >= alu_a) ? 1 : 0;
                        STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        //result = Y - alu_a;
                        result = alu_y - alu_a;
                        //STATUS[C] = (Y >= alu_a) ? 1 : 0;
                        STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
end
endmodule
 

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2	152	gabrielosh	`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18	141	creep	`////////////////////////////////////////////////////////////////////////////`
19	152	gabrielosh	`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	141	creep	`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61	183	gabrielosh	`reg [7:0] A;`
62	181	gabrielosh	`//reg [7:0] X;`
63			`//reg [7:0] Y;`
64	141	creep
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67	152	gabrielosh	`reg [7:0] op1;`
68			`reg [7:0] op2;`
69	161	gabrielosh	`reg [7:0] bcdl;`
70			`reg [7:0] bcdh;`
71	164	gabrielosh	`reg [7:0] bcdh2;`
72			`reg [7:0] AL;`
73			`reg [7:0] AH;`
74	181	gabrielosh	`//reg C_aux;`
75	173	gabrielosh	`reg sign;`
76	141	creep
77			`include "t6507lp_package.v"
78
79			`always @ (posedge clk or negedge reset_n)`
80			`begin`
81			`if (reset_n == 0) begin`
82			`alu_result <= 0;`
83			`alu_status[C] <= 0;`
84			`alu_status[N] <= 0;`
85			`alu_status[V] <= 0;`
86	148	gabrielosh	`alu_status[5] <= 1;`
87	141	creep	`alu_status[Z] <= 1;`
88			`alu_status[I] <= 0;`
89			`alu_status[B] <= 0;`
90			`alu_status[D] <= 0;`
91	183	gabrielosh	`A <= 0;`
92	181	gabrielosh	`//X <= 0;`
93			`//Y <= 0;`
94	141	creep	`alu_x <= 0;`
95			`alu_y <= 0;`
96			`end`
97			`else if ( alu_enable == 1 ) begin`
98			`case (alu_opcode)`
99			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
100			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
101			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
102			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
103			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
104			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
105	184	gabrielosh	`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP :`
106	141	creep	`begin`
107	183	gabrielosh	`A <= result;`
108	141	creep	`alu_result <= result;`
109			`alu_status <= STATUS;`
110			`end`
111			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
112			`begin`
113	181	gabrielosh	`//X <= result;`
114	141	creep	`alu_x <= result;`
115			`alu_status <= STATUS;`
116			`end`
117			`TXS_IMP :`
118			`begin`
119	181	gabrielosh	`//X <= result;`
120	148	gabrielosh	`alu_x <= result;`
121	141	creep	`end`
122	184	gabrielosh	`TXA_IMP, TYA_IMP :`
123			`begin`
124			`A <= result;`
125			`alu_status <= STATUS;`
126			`end`
127	141	creep	`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
128			`begin`
129	181	gabrielosh	`//Y <= result;`
130	141	creep	`alu_y <= result;`
131			`alu_status <= STATUS;`
132			`end`
133	148	gabrielosh	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,`
134	165	gabrielosh	`CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :`
135	141	creep	`begin`
136			`alu_status <= STATUS;`
137			`end`
138	178	gabrielosh	`PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
139	158	gabrielosh	`alu_result <= result;`
140			`end`
141	178	gabrielosh	`STX_ZPG, STX_ZPY, STX_ABS : begin`
142			`alu_x <= result;`
143			`end`
144			`STY_ZPG, STY_ZPX, STY_ABS : begin`
145			`alu_y <= result;`
146			`end`
147	141	creep	`SEC_IMP :`
148			`begin`
149			`alu_status[C] <= 1;`
150			`end`
151			`SED_IMP :`
152			`begin`
153			`alu_status[D] <= 1;`
154			`end`
155			`SEI_IMP :`
156			`begin`
157			`alu_status[I] <= 1;`
158			`end`
159			`CLC_IMP :`
160			`begin`
161			`alu_status[C] <= 0;`
162			`end`
163			`CLD_IMP :`
164			`begin`
165			`alu_status[D] <= 0;`
166			`end`
167			`CLI_IMP :`
168			`begin`
169			`alu_status[I] <= 0;`
170			`end`
171			`CLV_IMP :`
172			`begin`
173			`alu_status[V] <= 0;`
174			`end`
175			`BRK_IMP :`
176			`begin`
177	154	gabrielosh	`alu_status[B] <= 1;`
178	141	creep	`end`
179	171	creep	`PLP_IMP, RTI_IMP :`
180	141	creep	`begin`
181	175	gabrielosh	`alu_status[C] <= alu_a[C];`
182			`alu_status[Z] <= alu_a[Z];`
183			`alu_status[I] <= alu_a[I];`
184			`alu_status[D] <= alu_a[D];`
185			`alu_status[B] <= alu_a[B];`
186			`alu_status[V] <= alu_a[V];`
187			`alu_status[N] <= alu_a[N];`
188	173	gabrielosh	`alu_status[5] <= 1;`
189	141	creep	`end`
190			`BIT_ZPG, BIT_ABS :`
191			`begin`
192			`alu_status[Z] <= STATUS[Z];`
193			`alu_status[V] <= alu_a[6];`
194			`alu_status[N] <= alu_a[7];`
195			`end`
196	148	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,`
197			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,`
198			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
199	141	creep	`begin`
200			`alu_result <= result;`
201			`alu_status <= STATUS;`
202			`end`
203	173	gabrielosh	`//PHP_IMP : begin`
204			`//end`
205	141	creep	`default : begin`
206			`//$display("ERROR");`
207			`end`
208			`endcase`
209			`end`
210			`end`
211
212			`always @ (*) begin`
213	175	gabrielosh	`if (alu_enable == 1) begin`
214	181	gabrielosh	`//op1 = A;`
215	183	gabrielosh	`op1 = A;`
216	152	gabrielosh	`op2 = alu_a;`
217	150	gabrielosh	`result = alu_result;`
218			`STATUS[N] = alu_status[N];`
219			`STATUS[C] = alu_status[C];`
220			`STATUS[V] = alu_status[V];`
221			`STATUS[B] = alu_status[B];`
222			`STATUS[I] = alu_status[I];`
223			`STATUS[D] = alu_status[D];`
224			`STATUS[Z] = alu_status[Z];`
225	151	gabrielosh	`STATUS[5] = 1;`
226	141	creep
227	171	creep	`bcdl = 0;`
228			`bcdh = 0;`
229			`bcdh2 = 0;`
230			`AL = 0;`
231			`AH = 0;`
232	173	gabrielosh	`sign = op2[7];`
233	171	creep
234	141	creep	`case (alu_opcode)`
235			`// BIT - Bit Test`
236			`BIT_ZPG, BIT_ABS: begin`
237	181	gabrielosh	`//result = A & alu_a;`
238	183	gabrielosh	`result = A & alu_a;`
239	141	creep	`end`
240
241			`// BRK - Force Interrupt`
242	181	gabrielosh	`//BRK_IMP: begin`
243			`// STATUS[B] = 1'b1;`
244			`//end`
245	141	creep
246			`// CLC - Clear Carry Flag`
247	181	gabrielosh	`//CLC_IMP: begin`
248			`// STATUS[C] = 1'b0;`
249			`//end`
250	141	creep
251			`// CLD - Clear Decimal Flag`
252	181	gabrielosh	`//CLD_IMP: begin`
253			`// STATUS[D] = 1'b0;`
254			`//end`
255	141	creep
256			`// CLI - Clear Interrupt Disable`
257	181	gabrielosh	`//CLI_IMP: begin`
258			`// STATUS[I] = 1'b0;`
259			`//end`
260	141	creep
261			`// CLV - Clear Overflow Flag`
262	181	gabrielosh	`//CLV_IMP: begin`
263			`// STATUS[V] = 1'b0;`
264			`//end`
265	141	creep
266			`// NOP - No Operation`
267			`//NOP_IMP: begin`
268			`// Do nothing :-D`
269			`//end`
270
271			`// PLP - Pull Processor Status Register`
272	175	gabrielosh	`// RTI - Return from Interrupt`
273	176	gabrielosh	`//PLP_IMP, RTI_IMP: begin`
274			`// STATUS = alu_a;`
275			`//end`
276	157	gabrielosh
277			`PLA_IMP : begin`
278			`result = alu_a;`
279			`end`
280	141	creep
281			`// STA - Store Accumulator`
282			`// PHA - Push A`
283			`// TAX - Transfer Accumulator to X`
284			`// TAY - Transfer Accumulator to Y`
285			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
286	181	gabrielosh	`//result = A;`
287	183	gabrielosh	`result = A;`
288	141	creep	`end`
289
290			`// STX - Store X Register`
291			`// TXA - Transfer X to Accumulator`
292			`// TXS - Transfer X to Stack pointer`
293			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
294	181	gabrielosh	`//result = X;`
295			`result = alu_x;`
296	141	creep	`end`
297
298			`// STY - Store Y Register`
299			`// TYA - Transfer Y to Accumulator`
300			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
301	181	gabrielosh	`//result = Y;`
302			`result = alu_y;`
303	141	creep	`end`
304
305			`// SEC - Set Carry Flag`
306	181	gabrielosh	`//SEC_IMP: begin`
307			`// STATUS[C] = 1'b1;`
308			`//end`
309	141	creep
310			`// SED - Set Decimal Flag`
311	181	gabrielosh	`//SED_IMP: begin`
312			`// STATUS[D] = 1'b1;`
313			`//end`
314	141	creep
315			`// SEI - Set Interrupt Disable`
316	181	gabrielosh	`//SEI_IMP: begin`
317			`// STATUS[I] = 1'b1;`
318			`//end`
319	141	creep
320			`// INC - Increment memory`
321			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
322			`result = alu_a + 1;`
323			`end`
324
325			`// INX - Increment X Register`
326			`INX_IMP: begin`
327	181	gabrielosh	`//result = X + 1;`
328			`result = alu_x + 1;`
329	141	creep	`end`
330
331			`// INY - Increment Y Register`
332			`INY_IMP : begin`
333	181	gabrielosh	`//result = Y + 1;`
334			`result = alu_y + 1;`
335	141	creep	`end`
336
337			`// DEC - Decrement memory`
338			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
339			`result = alu_a - 1;`
340			`end`
341
342			`// DEX - Decrement X register`
343			`DEX_IMP: begin`
344	181	gabrielosh	`//result = X - 1;`
345			`result = alu_x - 1;`
346	141	creep	`end`
347
348			`// DEY - Decrement Y Register`
349			`DEY_IMP: begin`
350	181	gabrielosh	`//result = Y - 1;`
351			`result = alu_y - 1;`
352	141	creep	`end`
353
354			`// ADC - Add with carry`
355	162	gabrielosh	`// TODO: verify synthesis for % operand`
356	141	creep	`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
357			`if (alu_status[D] == 1) begin`
358	171	creep	`//$display("MODO DECIMAL");`
359	181	gabrielosh	`//AL = A[3:0] + alu_a[3:0] + alu_status[C];`
360			`AL = op1[3:0] + op2[3:0] + alu_status[C];`
361			`//AH = A[7:4] + alu_a[7:4];`
362			`AH = op1[7:4] + op2[7:4];`
363			`$display("AL = %d", AL);`
364			`$display("AH = %d", AH);`
365	164	gabrielosh	`if (AL > 9) begin`
366			`bcdh = AH + (AL / 10);`
367			`bcdl = AL % 10;`
368	141	creep	`end`
369	171	creep	`else begin`
370			`bcdh = AH;`
371			`bcdl = AL;`
372			`end`
373
374			`// ok`
375
376			`if (bcdh > 9) begin`
377	161	gabrielosh	`STATUS[C] = 1;`
378	164	gabrielosh	`bcdh2 = bcdh % 10;`
379	161	gabrielosh	`end`
380	171	creep	`else begin`
381			`STATUS[C] = 0;`
382			`bcdh2 = bcdh;`
383			`end`
384			`//$display("bcdh2 = %d", bcdh2);`
385			`//$display("bcdl = %d", bcdl);`
386	164	gabrielosh	`result = {bcdh2[3:0],bcdl[3:0]};`
387	141	creep	`end`
388	165	gabrielosh	`else begin`
389	171	creep	`//$display("MODO NORMAL");`
390	161	gabrielosh	`{STATUS[C],result} = op1 + op2 + alu_status[C];`
391	165	gabrielosh	`end`
392	162	gabrielosh
393	152	gabrielosh	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
394	141	creep	`STATUS[V] = 1;`
395			`else`
396			`STATUS[V] = 0;`
397			`end`
398
399			`// AND - Logical AND`
400			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
401	181	gabrielosh	`//result = A & alu_a;`
402	183	gabrielosh	`result = A & alu_a;`
403	141	creep	`end`
404
405			`// CMP - Compare`
406			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
407	181	gabrielosh	`//result = A - alu_a;`
408	183	gabrielosh	`result = A - alu_a;`
409	181	gabrielosh	`//STATUS[C] = (A >= alu_a) ? 1 : 0;`
410	183	gabrielosh	`STATUS[C] = (A >= alu_a) ? 1 : 0;`
411	141	creep	`end`
412
413			`// EOR - Exclusive OR`
414			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
415	183	gabrielosh	`result = A ^ alu_a;`
416	181	gabrielosh	`//result = A ^ alu_a;`
417	158	gabrielosh	`//$display("op1 ^ op2 = result");`
418			`//$display("%d ^ %d = %d", op1, op2, result);`
419	141	creep	`end`
420
421			`// LDA - Load Accumulator`
422			`// LDX - Load X Register`
423			`// LDY - Load Y Register`
424			`// TSX - Transfer Stack Pointer to X`
425			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
426			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
427			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
428			`TSX_IMP : begin`
429			`result = alu_a;`
430			`end`
431
432			`// ORA - Logical OR`
433			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
434	181	gabrielosh	`//result = A \| alu_a;`
435	183	gabrielosh	`result = A \| alu_a;`
436	141	creep	`end`
437
438			`// SBC - Subtract with Carry`
439			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
440	174	gabrielosh	`if (alu_status[D] == 1) begin`
441	183	gabrielosh	`/* //AL = A[3:0] + alu_a[3:0] + alu_status[C];`
442	181	gabrielosh	`AL = op1[3:0] + op2[3:0] + alu_status[C];`
443			`//AH = A[7:4] + alu_a[7:4];`
444			`AH = op1[7:4] + op2[7:4];`
445	179	gabrielosh	`if (AL > 9) begin`
446			`bcdh = AH + (AL / 10);`
447			`bcdl = AL % 10;`
448			`end`
449			`else begin`
450			`bcdh = AH;`
451			`bcdl = AL;`
452			`end`
453			`if (bcdh > 9) begin`
454			`STATUS[C] = 1;`
455			`bcdh2 = bcdh % 10;`
456			`end`
457			`else begin`
458			`STATUS[C] = 0;`
459			`bcdh2 = bcdh;`
460			`end`
461	183	gabrielosh	`result = {bcdh2[3:0],bcdl[3:0]};*/`
462			`//C := P_In(Flag_C) or not Op(0);`
463			`AL = {op1[3:0],alu_status[C]} - {op2[3:0],1'b1};`
464			`AH = {op1[7:4],1'b0} - {op2[7:4],AL[5]};`
465
466			`if (AL[5] == 1) begin`
467			`bcdl[5:1] = AL[5:1] - 6;`
468			`end`
469			`AH = {op1[7:4],1'b0} - {op2[7:4],bcdl[6]};`
470			`if (AH[5] == 1) begin`
471			`bcdh[5:1] = AH[5:1] - 6;`
472			`end`
473			`result = {bcdh[4:1],bcdl[4:1]};`
474			`STATUS[C] = ~result[7];`
475	179	gabrielosh	`end`
476			`else begin`
477	183	gabrielosh	`op2 = ~op2;`
478	179	gabrielosh	`//$display("MODO NORMAL");`
479	181	gabrielosh	`result = op1 + op2 + alu_status[C];`
480			`STATUS[C] = ~result[7];`
481	179	gabrielosh	`end`
482			`/* if (alu_status[D] == 1) begin`
483	178	gabrielosh	`bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);`
484			`bcdh = op1[7:4] - op2[7:4];`
485	162	gabrielosh	`if (bcdl > 9) begin`
486			`bcdh = bcdh + bcdl[5:4];`
487			`bcdl = bcdl % 10;`
488			`end`
489			`if (bcdh > 9) begin`
490			`STATUS[C] = 1;`
491			`bcdh = bcdh % 10;`
492			`end`
493	163	gabrielosh	`result = {bcdh[3:0],bcdl[3:0]};`
494	162	gabrielosh	`end`
495	173	gabrielosh	`else begin`
496	178	gabrielosh	`op2 = ~alu_a;`
497			`result = op1 + op2 + alu_status[C];`
498	174	gabrielosh	`STATUS[C] = ~result[7];`
499	173	gabrielosh	`end`
500	179	gabrielosh	`*/`

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 184