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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module t6507lp_alu(
        clk,
        reset_n,
        alu_enable,
        alu_result,
        alu_status,
        alu_opcode,
        alu_a,
        alu_x,
        alu_y
);
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
reg C_aux;
reg sign;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[5] <= 1;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
                        ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
                        AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,
                        EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS,
                        ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC,
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY,
                        SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP : begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP,
                        TSX_IMP, INX_IMP, DEX_IMP : begin
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP : begin
                                alu_x      <= result;
                        end
                        TXA_IMP, TYA_IMP : begin
                                A          <= result;
                                alu_status <= STATUS;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP,
                        INY_IMP, DEY_IMP : begin
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY,
                        CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
                        CPY_ZPG, CPY_ABS : begin
                                alu_status <= STATUS;
                        end
                        PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY,
                        STA_IDX, STA_IDY : begin
                                alu_result <= result;
                        end
                        STX_ZPG, STX_ZPY, STX_ABS : begin
                                alu_x <= result;
                        end
                        STY_ZPG, STY_ZPX, STY_ABS : begin
                                alu_y <= result;
                        end
                        SEC_IMP : begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP : begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP : begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP : begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP : begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP : begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP : begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP : begin
                                alu_status[B] <= 1;
                        end
                        PLP_IMP, RTI_IMP : begin
                                alu_status[C] <= alu_a[C];
                                alu_status[Z] <= alu_a[Z];
                                alu_status[I] <= alu_a[I];
                                alu_status[D] <= alu_a[D];
                                alu_status[B] <= alu_a[B];
                                alu_status[V] <= alu_a[V];
                                alu_status[N] <= alu_a[N];
                                alu_status[5] <= 1;
                        end
                        BIT_ZPG, BIT_ABS : begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX,
                        DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX,
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX,
                        ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        default : begin
                        end
                endcase
        end
end
 
always @ (*) begin
        if (alu_enable == 1) begin
                op1       = A;
                op2       = alu_a;
                result    = A;
                STATUS[N] = alu_status[N];
                STATUS[C] = alu_status[C];
                STATUS[V] = alu_status[V];
                STATUS[B] = alu_status[B];
                STATUS[I] = alu_status[I];
                STATUS[D] = alu_status[D];
                STATUS[Z] = alu_status[Z];
                STATUS[5] = 1;
 
                bcdl = 0;
                bcdh = 0;
                bcdh2 = 0;
                AL = 0;
                AH = 0;
                sign = op2[7];
 
                case (alu_opcode)
                        // BIT - Bit Test
                        BIT_ZPG, BIT_ABS: begin
                                result = A & alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // PLA - Pull Accumulator
                        PLA_IMP : begin
                                result = alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // TAX - Transfer Accumulator to X
                        // TAY - Transfer Accumulator to Y
                        // PHA - Push Accumulator
                        // STA - Store Accumulator
                        TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
                        STA_ABY, STA_IDX, STA_IDY : begin
                                result = A;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // STX - Store X Register
                        // TXA - Transfer X to Accumulator
                        // TXS - Transfer X to Stack pointer
                        STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                                result = alu_x;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // STY - Store Y Register
                        // TYA - Transfer Y to Accumulator
                        STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                                result = alu_y;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // INC - Increment memory
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                                result = alu_a + 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // INX - Increment X Register
                        INX_IMP: begin
                                result = alu_x + 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // INY - Increment Y Register
                        INY_IMP : begin
                                result = alu_y + 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // DEC - Decrement memory
                        DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                                result = alu_a - 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // DEX - Decrement X register
                        DEX_IMP: begin
                                result = alu_x - 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // DEY - Decrement Y Register
                        DEY_IMP: begin
                                result = alu_y - 1;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // ADC - Add with carry
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
                        ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                                if (!alu_status[D]) begin
                                        {STATUS[C],result} = op1 + op2 + alu_status[C];
                                        STATUS[N] = result[7];
                                        STATUS[Z] = (result == 0) ? 1 : 0;
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;
                                end
                                else begin
                                        AL = op1[3:0] + op2[3:0] + alu_status[C];
                                        AH = op1[7:4] + op2[7:4];
                                        STATUS[Z] = (AL == 0 && AH == 0) ? 1 : 0;
                                        if (AL > 9) begin
                                                bcdl = AL - 6;
                                                bcdh = AH + 1;
                                        end
                                        else begin
                                                bcdl = AL;
                                                bcdh = AH;
                                        end
                                        STATUS[N] = bcdh[3];
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1 : 0;
                                        if (bcdh > 9) begin
                                                bcdh2 = bcdh + 6;
                                        end
                                        else begin
                                                bcdh2 = bcdh;
                                        end
                                        STATUS[C] = bcdh2[4] || bcdh2[5];
                                        result = {bcdh2[3:0],bcdl[3:0]};
                                end
                        end
 
                        // AND - Logical AND
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
                        AND_IDY : begin
                                result = A & alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // CMP - Compare
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
                        CMP_IDY : begin
                                result = A - alu_a;
                                STATUS[C] = (A >= alu_a) ? 1 : 0;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // EOR - Exclusive OR
                        EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
                        EOR_IDX, EOR_IDY : begin
                                result = A ^ alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // LDA - Load Accumulator
                        // LDX - Load X Register
                        // LDY - Load Y Register
                        // TSX - Transfer Stack Pointer to X
                        LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
                        LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
                        LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
                                result = alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // ORA - Logical OR
                        ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
                        ORA_IDY : begin
                                result = A | alu_a;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // SBC - Subtract with Carry
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
                        SBC_IDY : begin
                                result = op1 - op2 - (1 - alu_status[C]);
                                STATUS[N] = result[7];
                                STATUS[V] = ((op1[7] == op2[7]) && (op1[7] == result[7])) ? 1 : 0;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[C] = ~result[7];
                                if (alu_status[D]) begin
                                        AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
                                        AH = op1[7:4] - op2[7:4];
                                        if (AL[4]) begin
                                                bcdl = AL - 6;
                                                bcdh = AH - 1;
                                        end
                                        else begin
                                                bcdl = AL;
                                                bcdh = AH;
                                        end
                                        if (bcdh[4]) begin
                                                bcdh2 = bcdh - 6;
                                        end
                                        else begin
                                                bcdh2 = bcdh;
                                        end
                                        result = {bcdh2[3:0],bcdl[3:0]};
                                end
                        end
 
                        // ASL - Arithmetic Shift Left
                        ASL_ACC : begin
                                {STATUS[C],result} = {A,1'b0};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                                {STATUS[C],result} = {alu_a,1'b0};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // LSR - Logical Shift Right
                        LSR_ACC: begin
                                {result,STATUS[C]} = {1'b0,A};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                                {result,STATUS[C]} = {1'b0,alu_a};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // ROL - Rotate Left
                        ROL_ACC : begin
                                {STATUS[C],result} = {A,alu_status[C]};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                                {STATUS[C],result} = {alu_a,alu_status[C]};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // ROR - Rotate Right
                        ROR_ACC : begin
                                {result,STATUS[C]} = {alu_status[C],A};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
                        ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                                {result, STATUS[C]} = {alu_status[C], alu_a};
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // CPX - Compare X Register
                        CPX_IMM, CPX_ZPG, CPX_ABS : begin
                                result = alu_x - alu_a;
                                STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        // CPY - Compare Y Register
                        CPY_IMM, CPY_ZPG, CPY_ABS : begin
                                result = alu_y - alu_a;
                                STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
                                STATUS[Z] = (result == 0) ? 1 : 0;
                                STATUS[N] = result[7];
                        end
 
                        default: begin
                        end
                endcase
        end
end
endmodule

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2	152	gabrielosh	`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18	141	creep	`////////////////////////////////////////////////////////////////////////////`
19	152	gabrielosh	`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	141	creep	`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	224	creep	`module t6507lp_alu(`
48			`clk,`
49			`reset_n,`
50			`alu_enable,`
51			`alu_result,`
52			`alu_status,`
53			`alu_opcode,`
54			`alu_a,`
55			`alu_x,`
56			`alu_y`
57			`);`
58	141	creep
59			`input wire clk;`
60			`input wire reset_n;`
61			`input wire alu_enable;`
62			`input wire [7:0] alu_opcode;`
63			`input wire [7:0] alu_a;`
64			`output reg [7:0] alu_result;`
65			`output reg [7:0] alu_status;`
66			`output reg [7:0] alu_x;`
67			`output reg [7:0] alu_y;`
68
69	183	gabrielosh	`reg [7:0] A;`
70	141	creep	`reg [7:0] STATUS;`
71			`reg [7:0] result;`
72	152	gabrielosh	`reg [7:0] op1;`
73			`reg [7:0] op2;`
74	161	gabrielosh	`reg [7:0] bcdl;`
75			`reg [7:0] bcdh;`
76	164	gabrielosh	`reg [7:0] bcdh2;`
77			`reg [7:0] AL;`
78			`reg [7:0] AH;`
79	186	gabrielosh	`reg C_aux;`
80	173	gabrielosh	`reg sign;`
81	141	creep
82			`include "t6507lp_package.v"
83
84			`always @ (posedge clk or negedge reset_n)`
85			`begin`
86			`if (reset_n == 0) begin`
87			`alu_result <= 0;`
88			`alu_status[C] <= 0;`
89			`alu_status[N] <= 0;`
90			`alu_status[V] <= 0;`
91	148	gabrielosh	`alu_status[5] <= 1;`
92	141	creep	`alu_status[Z] <= 1;`
93			`alu_status[I] <= 0;`
94			`alu_status[B] <= 0;`
95			`alu_status[D] <= 0;`
96	183	gabrielosh	`A <= 0;`
97	141	creep	`alu_x <= 0;`
98			`alu_y <= 0;`
99			`end`
100			`else if ( alu_enable == 1 ) begin`
101			`case (alu_opcode)`
102	224	creep	`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,`
103			`ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,`
104			`AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,`
105			`EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
106			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS,`
107			`ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC,`
108			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY,`
109			`SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
110			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP : begin`
111	183	gabrielosh	`A <= result;`
112	141	creep	`alu_result <= result;`
113			`alu_status <= STATUS;`
114			`end`
115	224	creep	`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP,`
116			`TSX_IMP, INX_IMP, DEX_IMP : begin`
117	141	creep	`alu_x <= result;`
118			`alu_status <= STATUS;`
119			`end`
120	224	creep	`TXS_IMP : begin`
121	148	gabrielosh	`alu_x <= result;`
122	141	creep	`end`
123	224	creep	`TXA_IMP, TYA_IMP : begin`
124	184	gabrielosh	`A <= result;`
125			`alu_status <= STATUS;`
126			`end`
127	224	creep	`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP,`
128			`INY_IMP, DEY_IMP : begin`
129	141	creep	`alu_y <= result;`
130			`alu_status <= STATUS;`
131			`end`
132	224	creep	`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY,`
133			`CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,`
134			`CPY_ZPG, CPY_ABS : begin`
135	141	creep	`alu_status <= STATUS;`
136			`end`
137	224	creep	`PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY,`
138			`STA_IDX, STA_IDY : begin`
139	158	gabrielosh	`alu_result <= result;`
140			`end`
141	178	gabrielosh	`STX_ZPG, STX_ZPY, STX_ABS : begin`
142			`alu_x <= result;`
143			`end`
144			`STY_ZPG, STY_ZPX, STY_ABS : begin`
145			`alu_y <= result;`
146			`end`
147	224	creep	`SEC_IMP : begin`
148	141	creep	`alu_status[C] <= 1;`
149			`end`
150	224	creep	`SED_IMP : begin`
151	141	creep	`alu_status[D] <= 1;`
152			`end`
153	224	creep	`SEI_IMP : begin`
154	141	creep	`alu_status[I] <= 1;`
155			`end`
156	224	creep	`CLC_IMP : begin`
157	141	creep	`alu_status[C] <= 0;`
158			`end`
159	224	creep	`CLD_IMP : begin`
160	141	creep	`alu_status[D] <= 0;`
161			`end`
162	224	creep	`CLI_IMP : begin`
163	141	creep	`alu_status[I] <= 0;`
164			`end`
165	224	creep	`CLV_IMP : begin`
166	141	creep	`alu_status[V] <= 0;`
167			`end`
168	224	creep	`BRK_IMP : begin`
169	154	gabrielosh	`alu_status[B] <= 1;`
170	141	creep	`end`
171	224	creep	`PLP_IMP, RTI_IMP : begin`
172	175	gabrielosh	`alu_status[C] <= alu_a[C];`
173			`alu_status[Z] <= alu_a[Z];`
174			`alu_status[I] <= alu_a[I];`
175			`alu_status[D] <= alu_a[D];`
176			`alu_status[B] <= alu_a[B];`
177			`alu_status[V] <= alu_a[V];`
178			`alu_status[N] <= alu_a[N];`
179	173	gabrielosh	`alu_status[5] <= 1;`
180	141	creep	`end`
181	224	creep	`BIT_ZPG, BIT_ABS : begin`
182	141	creep	`alu_status[Z] <= STATUS[Z];`
183			`alu_status[V] <= alu_a[6];`
184			`alu_status[N] <= alu_a[7];`
185			`end`
186	224	creep	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX,`
187			`DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX,`
188			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX,`
189			`ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :`
190	141	creep	`begin`
191			`alu_result <= result;`
192			`alu_status <= STATUS;`
193			`end`
194			`default : begin`
195			`end`
196			`endcase`
197			`end`
198			`end`
199
200			`always @ (*) begin`
201	224	creep	`if (alu_enable == 1) begin`
202			`op1 = A;`
203			`op2 = alu_a;`
204			`result = A;`
205			`STATUS[N] = alu_status[N];`
206			`STATUS[C] = alu_status[C];`
207			`STATUS[V] = alu_status[V];`
208			`STATUS[B] = alu_status[B];`
209			`STATUS[I] = alu_status[I];`
210			`STATUS[D] = alu_status[D];`
211			`STATUS[Z] = alu_status[Z];`
212			`STATUS[5] = 1;`
213	141	creep
214	224	creep	`bcdl = 0;`
215			`bcdh = 0;`
216			`bcdh2 = 0;`
217			`AL = 0;`
218			`AH = 0;`
219			`sign = op2[7];`
220
221			`case (alu_opcode)`
222			`// BIT - Bit Test`
223			`BIT_ZPG, BIT_ABS: begin`
224			`result = A & alu_a;`
225			`STATUS[Z] = (result == 0) ? 1 : 0;`
226			`STATUS[N] = result[7];`
227	141	creep	`end`
228	224	creep
229			`// PLA - Pull Accumulator`
230			`PLA_IMP : begin`
231			`result = alu_a;`
232			`STATUS[Z] = (result == 0) ? 1 : 0;`
233			`STATUS[N] = result[7];`
234	165	gabrielosh	`end`
235	224	creep
236			`// TAX - Transfer Accumulator to X`
237			`// TAY - Transfer Accumulator to Y`
238			`// PHA - Push Accumulator`
239			`// STA - Store Accumulator`
240			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,`
241			`STA_ABY, STA_IDX, STA_IDY : begin`
242			`result = A;`
243			`STATUS[Z] = (result == 0) ? 1 : 0;`
244			`STATUS[N] = result[7];`
245			`end`
246
247			`// STX - Store X Register`
248			`// TXA - Transfer X to Accumulator`
249			`// TXS - Transfer X to Stack pointer`
250			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
251			`result = alu_x;`
252			`STATUS[Z] = (result == 0) ? 1 : 0;`
253			`STATUS[N] = result[7];`
254			`end`
255
256			`// STY - Store Y Register`
257			`// TYA - Transfer Y to Accumulator`
258			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
259			`result = alu_y;`
260			`STATUS[Z] = (result == 0) ? 1 : 0;`
261			`STATUS[N] = result[7];`
262			`end`
263
264			`// INC - Increment memory`
265			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
266			`result = alu_a + 1;`
267			`STATUS[Z] = (result == 0) ? 1 : 0;`
268			`STATUS[N] = result[7];`
269			`end`
270
271			`// INX - Increment X Register`
272			`INX_IMP: begin`
273			`result = alu_x + 1;`
274			`STATUS[Z] = (result == 0) ? 1 : 0;`
275			`STATUS[N] = result[7];`
276			`end`
277
278			`// INY - Increment Y Register`
279			`INY_IMP : begin`
280			`result = alu_y + 1;`
281			`STATUS[Z] = (result == 0) ? 1 : 0;`
282			`STATUS[N] = result[7];`
283			`end`
284
285			`// DEC - Decrement memory`
286			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
287			`result = alu_a - 1;`
288			`STATUS[Z] = (result == 0) ? 1 : 0;`
289			`STATUS[N] = result[7];`
290			`end`
291
292			`// DEX - Decrement X register`
293			`DEX_IMP: begin`
294			`result = alu_x - 1;`
295			`STATUS[Z] = (result == 0) ? 1 : 0;`
296			`STATUS[N] = result[7];`
297			`end`
298
299			`// DEY - Decrement Y Register`
300			`DEY_IMP: begin`
301			`result = alu_y - 1;`
302			`STATUS[Z] = (result == 0) ? 1 : 0;`
303			`STATUS[N] = result[7];`
304			`end`
305
306			`// ADC - Add with carry`
307			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,`
308			`ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
309			`if (!alu_status[D]) begin`
310			`{STATUS[C],result} = op1 + op2 + alu_status[C];`
311			`STATUS[N] = result[7];`
312			`STATUS[Z] = (result == 0) ? 1 : 0;`
313			`STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;`
314	179	gabrielosh	`end`
315			`else begin`
316	224	creep	`AL = op1[3:0] + op2[3:0] + alu_status[C];`
317			`AH = op1[7:4] + op2[7:4];`
318			`STATUS[Z] = (AL == 0 && AH == 0) ? 1 : 0;`
319			`if (AL > 9) begin`
320			`bcdl = AL - 6;`
321			`bcdh = AH + 1;`
322			`end`
323			`else begin`
324			`bcdl = AL;`
325			`bcdh = AH;`
326			`end`
327			`STATUS[N] = bcdh[3];`
328			`STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1 : 0;`
329			`if (bcdh > 9) begin`
330			`bcdh2 = bcdh + 6;`
331			`end`
332			`else begin`
333			`bcdh2 = bcdh;`
334			`end`
335			`STATUS[C] = bcdh2[4] \|\| bcdh2[5];`
336			`result = {bcdh2[3:0],bcdl[3:0]};`
337	179	gabrielosh	`end`
338			`end`
339	224	creep
340			`// AND - Logical AND`
341			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,`
342			`AND_IDY : begin`
343			`result = A & alu_a;`
344			`STATUS[Z] = (result == 0) ? 1 : 0;`
345			`STATUS[N] = result[7];`
346	179	gabrielosh	`end`
347	224	creep
348			`// CMP - Compare`
349			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,`
350			`CMP_IDY : begin`
351			`result = A - alu_a;`
352			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
353			`STATUS[Z] = (result == 0) ? 1 : 0;`
354			`STATUS[N] = result[7];`
355	162	gabrielosh	`end`
356	224	creep
357			`// EOR - Exclusive OR`
358			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,`
359			`EOR_IDX, EOR_IDY : begin`
360			`result = A ^ alu_a;`
361			`STATUS[Z] = (result == 0) ? 1 : 0;`
362			`STATUS[N] = result[7];`
363			`end`
364
365			`// LDA - Load Accumulator`
366			`// LDX - Load X Register`
367			`// LDY - Load Y Register`
368			`// TSX - Transfer Stack Pointer to X`
369			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,`
370			`LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,`
371			`LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin`
372			`result = alu_a;`
373			`STATUS[Z] = (result == 0) ? 1 : 0;`
374			`STATUS[N] = result[7];`
375			`end`
376
377			`// ORA - Logical OR`
378			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,`
379			`ORA_IDY : begin`
380			`result = A \| alu_a;`
381			`STATUS[Z] = (result == 0) ? 1 : 0;`
382			`STATUS[N] = result[7];`
383			`end`
384
385			`// SBC - Subtract with Carry`
386			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,`
387			`SBC_IDY : begin`
388			`result = op1 - op2 - (1 - alu_status[C]);`
389			`STATUS[N] = result[7];`
390			`STATUS[V] = ((op1[7] == op2[7]) && (op1[7] == result[7])) ? 1 : 0;`
391			`STATUS[Z] = (result == 0) ? 1 : 0;`
392	174	gabrielosh	`STATUS[C] = ~result[7];`
393	224	creep	`if (alu_status[D]) begin`
394			`AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);`
395			`AH = op1[7:4] - op2[7:4];`
396			`if (AL[4]) begin`
397			`bcdl = AL - 6;`
398			`bcdh = AH - 1;`
399			`end`
400			`else begin`
401			`bcdl = AL;`
402			`bcdh = AH;`
403			`end`
404			`if (bcdh[4]) begin`
405			`bcdh2 = bcdh - 6;`
406			`end`
407			`else begin`
408			`bcdh2 = bcdh;`
409			`end`
410			`result = {bcdh2[3:0],bcdl[3:0]};`
411			`end`
412	173	gabrielosh	`end`
413	224	creep
414			`// ASL - Arithmetic Shift Left`
415			`ASL_ACC : begin`
416			`{STATUS[C],result} = {A,1'b0};`
417			`STATUS[Z] = (result == 0) ? 1 : 0;`
418			`STATUS[N] = result[7];`
419			`end`
420			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
421			`{STATUS[C],result} = {alu_a,1'b0};`
422			`STATUS[Z] = (result == 0) ? 1 : 0;`
423			`STATUS[N] = result[7];`
424			`end`
425
426			`// LSR - Logical Shift Right`
427			`LSR_ACC: begin`
428			`{result,STATUS[C]} = {1'b0,A};`
429			`STATUS[Z] = (result == 0) ? 1 : 0;`
430			`STATUS[N] = result[7];`
431			`end`
432			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
433			`{result,STATUS[C]} = {1'b0,alu_a};`
434			`STATUS[Z] = (result == 0) ? 1 : 0;`
435			`STATUS[N] = result[7];`
436			`end`
437
438			`// ROL - Rotate Left`
439			`ROL_ACC : begin`
440			`{STATUS[C],result} = {A,alu_status[C]};`
441			`STATUS[Z] = (result == 0) ? 1 : 0;`
442			`STATUS[N] = result[7];`
443			`end`
444			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
445			`{STATUS[C],result} = {alu_a,alu_status[C]};`
446			`STATUS[Z] = (result == 0) ? 1 : 0;`
447			`STATUS[N] = result[7];`
448			`end`
449
450			`// ROR - Rotate Right`
451			`ROR_ACC : begin`
452			`{result,STATUS[C]} = {alu_status[C],A};`
453			`STATUS[Z] = (result == 0) ? 1 : 0;`
454			`STATUS[N] = result[7];`
455			`end`
456			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
457			`{result, STATUS[C]} = {alu_status[C], alu_a};`
458			`STATUS[Z] = (result == 0) ? 1 : 0;`
459			`STATUS[N] = result[7];`
460			`end`
461
462			`// CPX - Compare X Register`
463			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
464			`result = alu_x - alu_a;`
465			`STATUS[C] = (alu_x >= alu_a) ? 1 : 0;`
466			`STATUS[Z] = (result == 0) ? 1 : 0;`
467			`STATUS[N] = result[7];`
468			`end`
469
470			`// CPY - Compare Y Register`
471			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
472			`result = alu_y - alu_a;`
473			`STATUS[C] = (alu_y >= alu_a) ? 1 : 0;`
474			`STATUS[Z] = (result == 0) ? 1 : 0;`
475			`STATUS[N] = result[7];`
476			`end`
477
478			`default: begin`
479			`end`
480			`endcase`
481			`end`
482	141	creep	`end`
483			`endmodule`

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