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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 234

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1 141 creep
////////////////////////////////////////////////////////////////////////////
2 152 gabrielosh
////                                                                    ////
3
//// T6507LP IP Core                                                    ////
4
////                                                                    ////
5
//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
7
////                                                                    ////
8
//// Description                                                        ////
9
//// 6507 ALU                                                           ////
10
////                                                                    ////
11
//// To Do:                                                             ////
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//// - Search for TODO                                                  ////
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////                                                                    ////
14
//// Author(s):                                                         ////
15
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
18 141 creep
////////////////////////////////////////////////////////////////////////////
19 152 gabrielosh
////                                                                    ////
20
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
21
////                                                                    ////
22
//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
24
//// removed from the file and that any derivative work contains        ////
25
//// the original copyright notice and the associated disclaimer.       ////
26
////                                                                    ////
27
//// This source file is free software; you can redistribute it         ////
28
//// and/or modify it under the terms of the GNU Lesser General         ////
29
//// Public License as published by the Free Software Foundation;       ////
30
//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
33
//// This source is distributed in the hope that it will be             ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
36
//// PURPOSE. See the GNU Lesser General Public License for more        ////
37
//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
40
//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
42
////                                                                    ////
43 141 creep
////////////////////////////////////////////////////////////////////////////
44
 
45
`include "timescale.v"
46
 
47 224 creep
module t6507lp_alu(
48
        clk,
49
        reset_n,
50
        alu_enable,
51
        alu_result,
52
        alu_status,
53
        alu_opcode,
54
        alu_a,
55
        alu_x,
56
        alu_y
57
);
58 141 creep
 
59
input wire       clk;
60
input wire       reset_n;
61
input wire       alu_enable;
62
input wire [7:0] alu_opcode;
63
input wire [7:0] alu_a;
64
output reg [7:0] alu_result;
65
output reg [7:0] alu_status;
66
output reg [7:0] alu_x;
67
output reg [7:0] alu_y;
68
 
69 183 gabrielosh
reg [7:0] A;
70 141 creep
reg [7:0] STATUS;
71 233 creep
reg [9:0] result;
72 152 gabrielosh
reg [7:0] op1;
73
reg [7:0] op2;
74 161 gabrielosh
reg [7:0] bcdl;
75
reg [7:0] bcdh;
76 164 gabrielosh
reg [7:0] bcdh2;
77
reg [7:0] AL;
78
reg [7:0] AH;
79 186 gabrielosh
reg C_aux;
80 173 gabrielosh
reg sign;
81 141 creep
 
82
`include "t6507lp_package.v"
83
 
84
always @ (posedge clk or negedge reset_n)
85
begin
86
        if (reset_n == 0) begin
87
                alu_result <= 0;
88
                alu_status[C] <= 0;
89
                alu_status[N] <= 0;
90
                alu_status[V] <= 0;
91 148 gabrielosh
                alu_status[5] <= 1;
92 141 creep
                alu_status[Z] <= 1;
93
                alu_status[I] <= 0;
94
                alu_status[B] <= 0;
95
                alu_status[D] <= 0;
96 183 gabrielosh
                A <= 0;
97 141 creep
                alu_x <= 0;
98
                alu_y <= 0;
99
        end
100
        else if ( alu_enable == 1 ) begin
101
                case (alu_opcode)
102 224 creep
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
103
                        ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
104
                        AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,
105
                        EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
106
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS,
107
                        ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC,
108
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY,
109
                        SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
110
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP : begin
111 233 creep
                                A          <= result[7:0];
112
                                alu_result <= result[7:0];
113 141 creep
                                alu_status <= STATUS;
114
                        end
115 224 creep
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP,
116
                        TSX_IMP, INX_IMP, DEX_IMP : begin
117 233 creep
                                alu_x      <= result[7:0];
118 141 creep
                                alu_status <= STATUS;
119
                        end
120 224 creep
                        TXS_IMP : begin
121 233 creep
                                alu_x      <= result[7:0];
122 141 creep
                        end
123 224 creep
                        TXA_IMP, TYA_IMP : begin
124 233 creep
                                A          <= result[7:0];
125 184 gabrielosh
                                alu_status <= STATUS;
126
                        end
127 224 creep
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP,
128
                        INY_IMP, DEY_IMP : begin
129 233 creep
                                alu_y      <= result[7:0];
130 141 creep
                                alu_status <= STATUS;
131
                        end
132 224 creep
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY,
133
                        CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
134
                        CPY_ZPG, CPY_ABS : begin
135 141 creep
                                alu_status <= STATUS;
136
                        end
137 224 creep
                        PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY,
138
                        STA_IDX, STA_IDY : begin
139 233 creep
                                alu_result <= result[7:0];
140 158 gabrielosh
                        end
141 178 gabrielosh
                        STX_ZPG, STX_ZPY, STX_ABS : begin
142 233 creep
                                alu_x <= result[7:0];
143 178 gabrielosh
                        end
144
                        STY_ZPG, STY_ZPX, STY_ABS : begin
145 233 creep
                                alu_y <= result[7:0];
146 178 gabrielosh
                        end
147 224 creep
                        SEC_IMP : begin
148 141 creep
                                alu_status[C] <= 1;
149
                        end
150 224 creep
                        SED_IMP : begin
151 141 creep
                                alu_status[D] <= 1;
152
                        end
153 224 creep
                        SEI_IMP : begin
154 141 creep
                                alu_status[I] <= 1;
155
                        end
156 224 creep
                        CLC_IMP : begin
157 141 creep
                                alu_status[C] <= 0;
158
                        end
159 224 creep
                        CLD_IMP : begin
160 141 creep
                                alu_status[D] <= 0;
161
                        end
162 224 creep
                        CLI_IMP : begin
163 141 creep
                                alu_status[I] <= 0;
164
                        end
165 224 creep
                        CLV_IMP : begin
166 141 creep
                                alu_status[V] <= 0;
167
                        end
168 224 creep
                        BRK_IMP : begin
169 154 gabrielosh
                                alu_status[B] <= 1;
170 141 creep
                        end
171 224 creep
                        PLP_IMP, RTI_IMP : begin
172 175 gabrielosh
                                alu_status[C] <= alu_a[C];
173
                                alu_status[Z] <= alu_a[Z];
174
                                alu_status[I] <= alu_a[I];
175
                                alu_status[D] <= alu_a[D];
176
                                alu_status[B] <= alu_a[B];
177
                                alu_status[V] <= alu_a[V];
178
                                alu_status[N] <= alu_a[N];
179 173 gabrielosh
                                alu_status[5] <= 1;
180 141 creep
                        end
181 224 creep
                        BIT_ZPG, BIT_ABS : begin
182 141 creep
                                alu_status[Z] <= STATUS[Z];
183
                                alu_status[V] <= alu_a[6];
184
                                alu_status[N] <= alu_a[7];
185
                        end
186 224 creep
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX,
187
                        DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX,
188
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX,
189
                        ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
190 141 creep
                        begin
191 233 creep
                                alu_result <= result[7:0];
192 141 creep
                                alu_status <= STATUS;
193
                        end
194
                        default : begin
195
                        end
196
                endcase
197
        end
198
end
199
 
200
always @ (*) begin
201 224 creep
        if (alu_enable == 1) begin
202
                op1       = A;
203
                op2       = alu_a;
204 233 creep
                result    = A[7:0];
205
                result[9:8] = 0;
206 224 creep
                STATUS[N] = alu_status[N];
207
                STATUS[C] = alu_status[C];
208
                STATUS[V] = alu_status[V];
209
                STATUS[B] = alu_status[B];
210
                STATUS[I] = alu_status[I];
211
                STATUS[D] = alu_status[D];
212
                STATUS[Z] = alu_status[Z];
213
                STATUS[5] = 1;
214 141 creep
 
215 224 creep
                bcdl = 0;
216
                bcdh = 0;
217
                bcdh2 = 0;
218
                AL = 0;
219
                AH = 0;
220
                sign = op2[7];
221
 
222
                case (alu_opcode)
223
                        // BIT - Bit Test
224
                        BIT_ZPG, BIT_ABS: begin
225 233 creep
                                result[7:0] = A & alu_a;
226 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
227
                                STATUS[N] = result[7];
228 141 creep
                        end
229 224 creep
 
230
                        // PLA - Pull Accumulator
231
                        PLA_IMP : begin
232 233 creep
                                result[7:0] = alu_a;
233 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
234
                                STATUS[N] = result[7];
235 165 gabrielosh
                        end
236 224 creep
 
237
                        // TAX - Transfer Accumulator to X
238
                        // TAY - Transfer Accumulator to Y
239
                        // PHA - Push Accumulator
240
                        // STA - Store Accumulator
241
                        TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
242
                        STA_ABY, STA_IDX, STA_IDY : begin
243 233 creep
                                result[7:0] = A;
244 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
245
                                STATUS[N] = result[7];
246
                        end
247
 
248
                        // STX - Store X Register
249
                        // TXA - Transfer X to Accumulator
250
                        // TXS - Transfer X to Stack pointer
251
                        STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
252 233 creep
                                result[7:0] = alu_x;
253 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
254
                                STATUS[N] = result[7];
255
                        end
256
 
257
                        // STY - Store Y Register
258
                        // TYA - Transfer Y to Accumulator
259
                        STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
260 233 creep
                                result[7:0] = alu_y;
261 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
262
                                STATUS[N] = result[7];
263
                        end
264
 
265
                        // INC - Increment memory
266
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
267 233 creep
                                result[7:0] = alu_a + 1;
268 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
269
                                STATUS[N] = result[7];
270
                        end
271
 
272
                        // INX - Increment X Register
273
                        INX_IMP: begin
274 233 creep
                                result[7:0] = alu_x + 1;
275 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
276
                                STATUS[N] = result[7];
277
                        end
278
 
279
                        // INY - Increment Y Register
280
                        INY_IMP : begin
281 233 creep
                                result[7:0] = alu_y + 1;
282 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
283
                                STATUS[N] = result[7];
284
                        end
285
 
286
                        // DEC - Decrement memory
287
                        DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
288 233 creep
                                result[7:0] = alu_a - 1;
289 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
290
                                STATUS[N] = result[7];
291
                        end
292
 
293
                        // DEX - Decrement X register
294
                        DEX_IMP: begin
295 233 creep
                                result[7:0] = alu_x - 1;
296 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
297
                                STATUS[N] = result[7];
298
                        end
299
 
300
                        // DEY - Decrement Y Register
301
                        DEY_IMP: begin
302 233 creep
                                result[7:0] = alu_y - 1;
303 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
304
                                STATUS[N] = result[7];
305
                        end
306
 
307
                        // ADC - Add with carry
308
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
309
                        ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
310
                                if (!alu_status[D]) begin
311 233 creep
                                        result = op1 + op2 + alu_status[C];
312 224 creep
                                        STATUS[N] = result[7];
313
                                        STATUS[Z] = (result == 0) ? 1 : 0;
314
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;
315 233 creep
                                        STATUS[C] = result[8];
316 179 gabrielosh
                                end
317
                                else begin
318 224 creep
                                        AL = op1[3:0] + op2[3:0] + alu_status[C];
319
                                        AH = op1[7:4] + op2[7:4];
320
                                        STATUS[Z] = (AL == 0 && AH == 0) ? 1 : 0;
321
                                        if (AL > 9) begin
322 234 creep
                                                bcdl = AL + 6;
323 224 creep
                                                bcdh = AH + 1;
324
                                        end
325
                                        else begin
326
                                                bcdl = AL;
327
                                                bcdh = AH;
328
                                        end
329
                                        STATUS[N] = bcdh[3];
330
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1 : 0;
331
                                        if (bcdh > 9) begin
332
                                                bcdh2 = bcdh + 6;
333
                                        end
334
                                        else begin
335
                                                bcdh2 = bcdh;
336
                                        end
337
                                        STATUS[C] = bcdh2[4] || bcdh2[5];
338 233 creep
                                        result[7:0] = {bcdh2[3:0],bcdl[3:0]};
339 179 gabrielosh
                                end
340
                        end
341 224 creep
 
342
                        // AND - Logical AND
343
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
344
                        AND_IDY : begin
345 233 creep
                                result[7:0] = A & alu_a;
346 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
347
                                STATUS[N] = result[7];
348 179 gabrielosh
                        end
349 224 creep
 
350
                        // CMP - Compare
351
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
352
                        CMP_IDY : begin
353 233 creep
                                result[7:0] = A - alu_a;
354 224 creep
                                STATUS[C] = (A >= alu_a) ? 1 : 0;
355
                                STATUS[Z] = (result == 0) ? 1 : 0;
356
                                STATUS[N] = result[7];
357 162 gabrielosh
                        end
358 224 creep
 
359
                        // EOR - Exclusive OR
360
                        EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
361
                        EOR_IDX, EOR_IDY : begin
362 233 creep
                                result[7:0] = A ^ alu_a;
363 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
364
                                STATUS[N] = result[7];
365
                        end
366
 
367
                        // LDA - Load Accumulator
368
                        // LDX - Load X Register
369
                        // LDY - Load Y Register
370
                        // TSX - Transfer Stack Pointer to X
371
                        LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
372
                        LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
373
                        LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
374 233 creep
                                result[7:0] = alu_a;
375 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
376
                                STATUS[N] = result[7];
377
                        end
378
 
379
                        // ORA - Logical OR
380
                        ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
381
                        ORA_IDY : begin
382 233 creep
                                result[7:0] = A | alu_a;
383 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
384
                                STATUS[N] = result[7];
385
                        end
386
 
387
                        // SBC - Subtract with Carry
388
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
389
                        SBC_IDY : begin
390
                                result = op1 - op2 - (1 - alu_status[C]);
391
                                STATUS[N] = result[7];
392 233 creep
                                STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1 : 0;
393 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
394 233 creep
                                STATUS[C] = ~(result[8] || result[9]);
395 224 creep
                                if (alu_status[D]) begin
396
                                        AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
397
                                        AH = op1[7:4] - op2[7:4];
398
                                        if (AL[4]) begin
399
                                                bcdl = AL - 6;
400
                                                bcdh = AH - 1;
401
                                        end
402
                                        else begin
403
                                                bcdl = AL;
404
                                                bcdh = AH;
405
                                        end
406
                                        if (bcdh[4]) begin
407
                                                bcdh2 = bcdh - 6;
408
                                        end
409
                                        else begin
410
                                                bcdh2 = bcdh;
411
                                        end
412 233 creep
                                        result[7:0] = {bcdh2[3:0],bcdl[3:0]};
413 224 creep
                                end
414 173 gabrielosh
                        end
415 224 creep
 
416
                        // ASL - Arithmetic Shift Left
417
                        ASL_ACC : begin
418 233 creep
                                {STATUS[C],result[7:0]} = {A,1'b0};
419 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
420
                                STATUS[N] = result[7];
421
                        end
422
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
423 233 creep
                                {STATUS[C],result[7:0]} = {alu_a,1'b0};
424 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
425
                                STATUS[N] = result[7];
426
                        end
427
 
428
                        // LSR - Logical Shift Right
429
                        LSR_ACC: begin
430 233 creep
                                {result[7:0],STATUS[C]} = {1'b0,A};
431 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
432
                                STATUS[N] = result[7];
433
                        end
434
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
435 233 creep
                                {result[7:0],STATUS[C]} = {1'b0,alu_a};
436 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
437
                                STATUS[N] = result[7];
438
                        end
439
 
440
                        // ROL - Rotate Left
441
                        ROL_ACC : begin
442 233 creep
                                {STATUS[C],result[7:0]} = {A,alu_status[C]};
443 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
444
                                STATUS[N] = result[7];
445
                        end
446
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
447 233 creep
                                {STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
448 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
449
                                STATUS[N] = result[7];
450
                        end
451
 
452
                        // ROR - Rotate Right
453
                        ROR_ACC : begin
454 233 creep
                                {result[7:0],STATUS[C]} = {alu_status[C],A};
455 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
456
                                STATUS[N] = result[7];
457
                        end
458
                        ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
459 233 creep
                                {result[7:0], STATUS[C]} = {alu_status[C], alu_a};
460 224 creep
                                STATUS[Z] = (result == 0) ? 1 : 0;
461
                                STATUS[N] = result[7];
462
                        end
463
 
464
                        // CPX - Compare X Register
465
                        CPX_IMM, CPX_ZPG, CPX_ABS : begin
466 233 creep
                                result[7:0] = alu_x - alu_a;
467 224 creep
                                STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
468
                                STATUS[Z] = (result == 0) ? 1 : 0;
469
                                STATUS[N] = result[7];
470
                        end
471
 
472
                        // CPY - Compare Y Register
473
                        CPY_IMM, CPY_ZPG, CPY_ABS : begin
474 233 creep
                                result[7:0] = alu_y - alu_a;
475 224 creep
                                STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
476
                                STATUS[Z] = (result == 0) ? 1 : 0;
477
                                STATUS[N] = result[7];
478
                        end
479
 
480
                        default: begin
481
                        end
482
                endcase
483
        end
484 141 creep
end
485
endmodule

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