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127 |
gabrielosh |
`include "timescale.v"
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136 |
gabrielosh |
module t6507lp_alu_tb;
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127 |
gabrielosh |
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136 |
gabrielosh |
`include "t6507lp_package.v"
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127 |
gabrielosh |
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136 |
gabrielosh |
reg clk;
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7 |
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reg reset;
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reg alu_enable;
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wire [7:0] alu_result;
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10 |
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wire [7:0] alu_status;
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reg [7:0] alu_opcode;
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reg [7:0] alu_a;
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wire [7:0] alu_x;
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wire [7:0] alu_y;
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reg [31:0] i;
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127 |
gabrielosh |
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reg [7:0] alu_result_expected;
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reg [7:0] alu_status_expected;
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reg [7:0] alu_x_expected;
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reg [7:0] alu_y_expected;
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reg c_aux;
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reg [7:0] temp;
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136 |
gabrielosh |
t6507lp_alu DUT (
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.clk (clk),
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.reset_n (reset_n),
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127 |
gabrielosh |
.alu_enable (alu_enable),
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.alu_result (alu_result),
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.alu_status (alu_status),
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.alu_opcode (alu_opcode),
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.alu_a (alu_a),
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.alu_x (alu_x),
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.alu_y (alu_y)
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);
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localparam period = 10;
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task check;
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begin
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$display(" RESULTS EXPECTED");
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$display("alu_result %h %h ", alu_result, alu_result_expected);
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$display("alu_status %b %b ", alu_status, alu_status_expected);
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$display("alu_x %h %h ", alu_x, alu_x_expected );
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$display("alu_y %h %h ", alu_y, alu_y_expected );
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if ((alu_result_expected != alu_result) || (alu_status_expected != alu_status) || (alu_x_expected != alu_x) || (alu_y_expected != alu_y))
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begin
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$display("ERROR at instruction %h",alu_opcode);
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$finish;
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end
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else
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begin
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$display("Instruction %h... OK!", alu_opcode);
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end
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end
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endtask
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always begin
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gabrielosh |
#(period/2) clk = ~clk;
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127 |
gabrielosh |
end
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initial
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begin
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// Reset
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136 |
gabrielosh |
clk = 0;
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reset_n = 0;
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127 |
gabrielosh |
@(negedge clk_i);
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@(negedge clk_i);
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136 |
gabrielosh |
reset_n = 1;
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127 |
gabrielosh |
alu_enable = 1;
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alu_result_expected = 8'h00;
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alu_status_expected = 8'b00100010;
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alu_x_expected = 8'h00;
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alu_y_expected = 8'h00;
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// LDA
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alu_a = 0;
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alu_opcode = LDA_IMM;
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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@(negedge clk_i);
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alu_result_expected = 8'h00;
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// NV1BDIZC
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alu_status_expected = 8'b00100010;
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check();
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// ADC
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alu_opcode = ADC_IMM;
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alu_a = 1;
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for (i = 0; i < 1000; i = i + 1)
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begin
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@(negedge clk_i);
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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{alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
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alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
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alu_status_expected[N] = alu_result_expected[7];
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alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
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check();
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end
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// SBC
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alu_opcode = SBC_IMM;
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for (i = 0; i < 1000; i = i + 1)
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begin
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@(negedge clk_i);
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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{alu_status_expected[C], alu_result_expected} = alu_result_expected - alu_a - ~alu_status_expected[C];
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alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
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alu_status_expected[N] = alu_result_expected[7];
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alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
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check();
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end
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// LDA
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alu_opcode = LDA_IMM;
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for (i = 0; i < 1000; i = i + 1)
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begin
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alu_a = i;
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@(negedge clk_i);
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alu_result_expected = i;
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alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
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alu_status_expected[N] = alu_result_expected[7];
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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// LDX
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alu_opcode = LDX_IMM;
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for (i = 0; i < 1000; i = i + 1)
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begin
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alu_a = i;
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@(negedge clk_i);
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alu_x_expected = i;
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//alu_result_expected = i;
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alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
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alu_status_expected[N] = alu_x_expected[7];
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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// LDY
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alu_opcode = LDY_IMM;
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for (i = 0; i < 1001; i = i + 1)
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begin
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alu_a = i;
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@(negedge clk_i);
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alu_y_expected = i;
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//alu_result_expected = i;
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alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
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alu_status_expected[N] = alu_y_expected[7];
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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// STA
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alu_opcode = STA_ABS;
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for (i = 0; i < 1000; i = i + 1)
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begin
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alu_a = i;
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@(negedge clk_i);
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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// STX
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alu_opcode = STX_ABS;
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for (i = 0; i < 1000; i = i + 1)
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begin
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alu_a = i;
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@(negedge clk_i);
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//alu_result_expected = i;
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//alu_x_expected = i;
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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// STY
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alu_opcode = STY_ABS;
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for (i = 0; i < 1000; i = i + 1)
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196 |
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begin
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197 |
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alu_a = i;
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@(negedge clk_i);
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//alu_result_expected = i;
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200 |
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//alu_y_expected = i;
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201 |
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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203 |
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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check();
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end
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206 |
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// CMP
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208 |
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alu_opcode = CMP_IMM;
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209 |
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for (i = 0; i < 1000; i = i + 1)
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210 |
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begin
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211 |
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alu_a = i;
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@(negedge clk_i);
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213 |
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temp = alu_result_expected - alu_a;
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alu_status_expected[Z] = (temp == 0) ? 1 : 0;
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alu_status_expected[N] = temp[7];
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216 |
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alu_status_expected[C] = (alu_result_expected >= alu_a) ? 1 : 0;
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217 |
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//alu_result_expected = i;
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218 |
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//alu_y_expected = i;
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219 |
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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220 |
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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221 |
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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222 |
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check();
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223 |
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end
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224 |
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225 |
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// CPX
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226 |
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alu_opcode = CPX_IMM;
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227 |
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for (i = 0; i < 1000; i = i + 1)
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228 |
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begin
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229 |
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alu_a = i;
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230 |
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@(negedge clk_i);
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231 |
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temp = alu_x_expected - alu_a;
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232 |
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alu_status_expected[Z] = (temp == 0) ? 1 : 0;
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233 |
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alu_status_expected[N] = temp[7];
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234 |
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alu_status_expected[C] = (alu_x_expected >= alu_a) ? 1 : 0;
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235 |
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//alu_result_expected = i;
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236 |
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//alu_y_expected = i;
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237 |
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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238 |
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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239 |
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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240 |
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check();
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241 |
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end
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242 |
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243 |
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// CPY
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244 |
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alu_opcode = CPY_IMM;
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245 |
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for (i = 0; i < 1000; i = i + 1)
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246 |
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begin
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247 |
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alu_a = i;
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248 |
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@(negedge clk_i);
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249 |
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temp = alu_y_expected - alu_a;
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250 |
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alu_status_expected[Z] = (temp == 0) ? 1 : 0;
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251 |
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alu_status_expected[N] = temp[7];
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252 |
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alu_status_expected[C] = (alu_y_expected >= alu_a) ? 1 : 0;
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253 |
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//alu_result_expected = i;
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254 |
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//alu_y_expected = i;
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255 |
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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256 |
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
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257 |
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//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
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258 |
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check();
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259 |
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end
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260 |
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261 |
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262 |
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// AND
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263 |
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alu_opcode = AND_IMM;
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264 |
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for (i = 0; i < 1000; i = i + 1)
|
265 |
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begin
|
266 |
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alu_a = i;
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267 |
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@(negedge clk_i);
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268 |
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alu_result_expected = i & alu_result_expected;
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269 |
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alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
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270 |
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alu_status_expected[N] = alu_result_expected[7];
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271 |
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//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
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272 |
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//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
273 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
274 |
|
|
check();
|
275 |
|
|
end
|
276 |
|
|
|
277 |
|
|
// ASL
|
278 |
|
|
alu_opcode = ASL_ACC;
|
279 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
280 |
|
|
begin
|
281 |
|
|
alu_a = i;
|
282 |
|
|
@(negedge clk_i);
|
283 |
|
|
alu_status_expected[C] = alu_result_expected[7];
|
284 |
|
|
alu_result_expected[7:0] = alu_result_expected << 1;
|
285 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
286 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
287 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
288 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
289 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
290 |
|
|
check();
|
291 |
|
|
end
|
292 |
|
|
|
293 |
|
|
// INC
|
294 |
|
|
alu_opcode = INC_ZPG;
|
295 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
296 |
|
|
begin
|
297 |
|
|
alu_a = i;
|
298 |
|
|
@(negedge clk_i);
|
299 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
300 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
301 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
302 |
|
|
alu_result_expected = alu_a + 1;
|
303 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
304 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
305 |
|
|
check();
|
306 |
|
|
end
|
307 |
|
|
|
308 |
|
|
// INX
|
309 |
|
|
alu_opcode = INX_IMP;
|
310 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
311 |
|
|
begin
|
312 |
|
|
alu_a = i;
|
313 |
|
|
@(negedge clk_i);
|
314 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
315 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
316 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
317 |
|
|
alu_x_expected = alu_x_expected + 1;
|
318 |
|
|
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
|
319 |
|
|
alu_status_expected[N] = alu_x_expected[7];
|
320 |
|
|
check();
|
321 |
|
|
end
|
322 |
|
|
|
323 |
|
|
// INY
|
324 |
|
|
alu_opcode = INY_IMP;
|
325 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
326 |
|
|
begin
|
327 |
|
|
alu_a = i;
|
328 |
|
|
@(negedge clk_i);
|
329 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
330 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
331 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
332 |
|
|
alu_y_expected = alu_y_expected + 1;
|
333 |
|
|
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
|
334 |
|
|
alu_status_expected[N] = alu_y_expected[7];
|
335 |
|
|
check();
|
336 |
|
|
end
|
337 |
|
|
|
338 |
|
|
// DEC
|
339 |
|
|
alu_opcode = DEC_ZPG;
|
340 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
341 |
|
|
begin
|
342 |
|
|
alu_a = i;
|
343 |
|
|
@(negedge clk_i);
|
344 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
345 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
346 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
347 |
|
|
alu_result_expected = alu_a - 1;
|
348 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
349 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
350 |
|
|
check();
|
351 |
|
|
end
|
352 |
|
|
|
353 |
|
|
// DEX
|
354 |
|
|
alu_opcode = DEX_IMP;
|
355 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
356 |
|
|
begin
|
357 |
|
|
alu_a = i;
|
358 |
|
|
@(negedge clk_i);
|
359 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
360 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
361 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
362 |
|
|
alu_x_expected = alu_x_expected - 1;
|
363 |
|
|
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
|
364 |
|
|
alu_status_expected[N] = alu_x_expected[7];
|
365 |
|
|
check();
|
366 |
|
|
end
|
367 |
|
|
|
368 |
|
|
// DEY
|
369 |
|
|
alu_opcode = DEY_IMP;
|
370 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
371 |
|
|
begin
|
372 |
|
|
alu_a = i;
|
373 |
|
|
@(negedge clk_i);
|
374 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
375 |
|
|
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
376 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
377 |
|
|
alu_y_expected = alu_y_expected - 1;
|
378 |
|
|
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
|
379 |
|
|
alu_status_expected[N] = alu_y_expected[7];
|
380 |
|
|
check();
|
381 |
|
|
end
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
// LDA
|
385 |
|
|
alu_a = 0;
|
386 |
|
|
alu_opcode = LDA_IMM;
|
387 |
|
|
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
388 |
|
|
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
389 |
|
|
@(negedge clk_i);
|
390 |
|
|
alu_result_expected = 8'h00;
|
391 |
|
|
// NV1BDIZC
|
392 |
|
|
alu_status_expected = 8'b00100010;
|
393 |
|
|
check();
|
394 |
|
|
|
395 |
|
|
// BIT
|
396 |
|
|
alu_opcode = BIT_ZPG;
|
397 |
|
|
for (i = 0; i < 1000; i = i + 1)
|
398 |
|
|
begin
|
399 |
|
|
alu_a = i;
|
400 |
|
|
@(negedge clk_i);
|
401 |
|
|
$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
|
402 |
|
|
$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
|
403 |
|
|
$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
|
404 |
|
|
alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
|
405 |
|
|
alu_status_expected[V] = alu_a[6];
|
406 |
|
|
alu_status_expected[N] = alu_a[7];
|
407 |
|
|
check();
|
408 |
|
|
end
|
409 |
|
|
|
410 |
|
|
// SEC
|
411 |
|
|
alu_opcode = SEC_IMP;
|
412 |
|
|
@(negedge clk_i);
|
413 |
|
|
alu_status_expected[C] = 1;
|
414 |
|
|
check();
|
415 |
|
|
|
416 |
|
|
// SED
|
417 |
|
|
alu_opcode = SED_IMP;
|
418 |
|
|
@(negedge clk_i);
|
419 |
|
|
alu_status_expected[D] = 1;
|
420 |
|
|
check();
|
421 |
|
|
|
422 |
|
|
// SEI
|
423 |
|
|
alu_opcode = SEI_IMP;
|
424 |
|
|
@(negedge clk_i);
|
425 |
|
|
alu_status_expected[I] = 1;
|
426 |
|
|
check();
|
427 |
|
|
|
428 |
|
|
// CLC
|
429 |
|
|
alu_opcode = CLC_IMP;
|
430 |
|
|
@(negedge clk_i);
|
431 |
|
|
alu_status_expected[C] = 0;
|
432 |
|
|
check();
|
433 |
|
|
|
434 |
|
|
// CLD
|
435 |
|
|
alu_opcode = CLD_IMP;
|
436 |
|
|
@(negedge clk_i);
|
437 |
|
|
alu_status_expected[D] = 0;
|
438 |
|
|
check();
|
439 |
|
|
|
440 |
|
|
// CLI
|
441 |
|
|
alu_opcode = CLI_IMP;
|
442 |
|
|
@(negedge clk_i);
|
443 |
|
|
alu_status_expected[I] = 0;
|
444 |
|
|
check();
|
445 |
|
|
|
446 |
|
|
// CLV
|
447 |
|
|
alu_opcode = CLV_IMP;
|
448 |
|
|
@(negedge clk_i);
|
449 |
|
|
alu_status_expected[V] = 0;
|
450 |
|
|
check();
|
451 |
|
|
|
452 |
|
|
// LDA
|
453 |
|
|
alu_opcode = LDA_IMM;
|
454 |
|
|
alu_a = 8'h76;
|
455 |
|
|
@(negedge clk_i);
|
456 |
|
|
alu_result_expected = alu_a;
|
457 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
458 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
459 |
|
|
check();
|
460 |
|
|
|
461 |
|
|
// TAX
|
462 |
|
|
alu_opcode = TAX_IMP;
|
463 |
|
|
@(negedge clk_i);
|
464 |
|
|
alu_x_expected = alu_result_expected;
|
465 |
|
|
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
|
466 |
|
|
alu_status_expected[N] = alu_x_expected[7];
|
467 |
|
|
check();
|
468 |
|
|
|
469 |
|
|
// TAY
|
470 |
|
|
alu_opcode = TAY_IMP;
|
471 |
|
|
@(negedge clk_i);
|
472 |
|
|
alu_y_expected = alu_result_expected;
|
473 |
|
|
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
|
474 |
|
|
alu_status_expected[N] = alu_y_expected[7];
|
475 |
|
|
check();
|
476 |
|
|
|
477 |
|
|
// TSX
|
478 |
|
|
alu_opcode = TSX_IMP;
|
479 |
|
|
@(negedge clk_i);
|
480 |
|
|
alu_x_expected = alu_a;
|
481 |
|
|
//alu_result_expected = alu_a;
|
482 |
|
|
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
|
483 |
|
|
alu_status_expected[N] = alu_x_expected[7];
|
484 |
|
|
check();
|
485 |
|
|
|
486 |
|
|
// TXA
|
487 |
|
|
alu_opcode = TXA_IMP;
|
488 |
|
|
@(negedge clk_i);
|
489 |
|
|
alu_result_expected = alu_x_expected;
|
490 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
491 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
492 |
|
|
check();
|
493 |
|
|
|
494 |
|
|
// TXS
|
495 |
|
|
alu_opcode = TXS_IMP;
|
496 |
|
|
@(negedge clk_i);
|
497 |
|
|
alu_result_expected = alu_x_expected;
|
498 |
|
|
check();
|
499 |
|
|
|
500 |
|
|
// TYA
|
501 |
|
|
alu_opcode = TYA_IMP;
|
502 |
|
|
@(negedge clk_i);
|
503 |
|
|
alu_result_expected = alu_y_expected;
|
504 |
|
|
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
|
505 |
|
|
alu_status_expected[N] = alu_result_expected[7];
|
506 |
|
|
check();
|
507 |
|
|
|
508 |
|
|
// Nothing should happen
|
509 |
|
|
// BCC
|
510 |
|
|
alu_opcode = BCC_REL;
|
511 |
|
|
@(negedge clk_i);
|
512 |
|
|
check();
|
513 |
|
|
|
514 |
|
|
// BCS
|
515 |
|
|
alu_opcode = BCS_REL;
|
516 |
|
|
@(negedge clk_i);
|
517 |
|
|
check();
|
518 |
|
|
|
519 |
|
|
// BEQ
|
520 |
|
|
alu_opcode = BEQ_REL;
|
521 |
|
|
@(negedge clk_i);
|
522 |
|
|
check();
|
523 |
|
|
|
524 |
|
|
// BMI
|
525 |
|
|
alu_opcode = BMI_REL;
|
526 |
|
|
@(negedge clk_i);
|
527 |
|
|
check();
|
528 |
|
|
|
529 |
|
|
// BNE
|
530 |
|
|
alu_opcode = BNE_REL;
|
531 |
|
|
@(negedge clk_i);
|
532 |
|
|
check();
|
533 |
|
|
|
534 |
|
|
// BPL
|
535 |
|
|
alu_opcode = BPL_REL;
|
536 |
|
|
@(negedge clk_i);
|
537 |
|
|
check();
|
538 |
|
|
|
539 |
|
|
// BVC
|
540 |
|
|
alu_opcode = BVC_REL;
|
541 |
|
|
@(negedge clk_i);
|
542 |
|
|
check();
|
543 |
|
|
|
544 |
|
|
// BVS
|
545 |
|
|
alu_opcode = BVS_REL;
|
546 |
|
|
@(negedge clk_i);
|
547 |
|
|
check();
|
548 |
|
|
|
549 |
|
|
// JMP
|
550 |
|
|
alu_opcode = JMP_ABS;
|
551 |
|
|
@(negedge clk_i);
|
552 |
|
|
check();
|
553 |
|
|
|
554 |
|
|
// JMP
|
555 |
|
|
alu_opcode = JMP_IND;
|
556 |
|
|
@(negedge clk_i);
|
557 |
|
|
check();
|
558 |
|
|
|
559 |
|
|
// JSR
|
560 |
|
|
alu_opcode = JSR_ABS;
|
561 |
|
|
@(negedge clk_i);
|
562 |
|
|
check();
|
563 |
|
|
|
564 |
|
|
// NOP
|
565 |
|
|
alu_opcode = NOP_IMP;
|
566 |
|
|
@(negedge clk_i);
|
567 |
|
|
check();
|
568 |
|
|
|
569 |
|
|
// RTS
|
570 |
|
|
alu_opcode = RTS_IMP;
|
571 |
|
|
@(negedge clk_i);
|
572 |
|
|
check();
|
573 |
|
|
|
574 |
|
|
$display("TEST PASSED");
|
575 |
|
|
$finish;
|
576 |
|
|
end
|
577 |
|
|
|
578 |
|
|
endmodule
|
579 |
|
|
|