URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Blame information for rev 255

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU Testbench                                                 ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module t6507lp_alu_tb;
 
`include  "t6507lp_package.v"
 
reg        clk;
reg        reset_n;
reg        alu_enable;
wire [7:0] alu_result;
wire [7:0] alu_status;
reg  [7:0] alu_opcode;
reg  [7:0] alu_a;
wire [7:0] alu_x;
wire [7:0] alu_y;
 
integer i, j;
integer ADC_RESULTS, SBC_RESULTS;
 
reg [7:0] alu_result_expected;
reg [7:0] alu_status_expected;
reg [7:0] alu_x_expected;
reg [7:0] alu_y_expected;
 
reg       C_in;
reg       C_temp;
reg       sign;
reg [7:0] temp1;
reg [7:0] temp2;
reg [3:0] AL;
reg [3:0] AH;
reg [3:0] BL;
reg [3:0] BH;
reg [7:0] alu_result_expected_temp;
 
t6507lp_alu DUT (
        .clk        (   clk    ),
        .reset_n    ( reset_n  ),
        .alu_enable (alu_enable),
        .alu_result (alu_result),
        .alu_status (alu_status),
        .alu_opcode (alu_opcode),
        .alu_a      (  alu_a   ),
        .alu_x      (  alu_x   ),
        .alu_y      (  alu_y   )
);
 
 
localparam period = 10;
 
task check;
        begin
                $display("               RESULTS       EXPECTED");
                $display("alu_result       %h             %h   ", alu_result, alu_result_expected);
                $display("alu_status    %b       %b   ", alu_status, alu_status_expected);
                $display("alu_x            %h             %h   ", alu_x,      alu_x_expected     );
                $display("alu_y            %h             %h   ", alu_y,      alu_y_expected     );
                if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y))
                begin
                        $display("Instruction %h... OK!", alu_opcode);
                end
                else
                begin
                        $display("ERROR at instruction %h",alu_opcode);
                        $finish;
                end
        end
endtask
 
 
always begin
        #(period/2) clk = ~clk;
end
 
initial
begin
        //ADC_RESULT = fopen("ADC_RESULTS.txt");
        //SBC_RESULT = fopen("SBC_RESULTS.txt");
 
        // Reset
        clk = 0;
        reset_n = 0;
        @(negedge clk);
        reset_n = 1;
        alu_enable = 1;
        alu_result_expected = 8'h00;
        alu_status_expected = 8'b00100010;
        alu_x_expected = 8'h00;
        alu_y_expected = 8'h00;
 
        // LDA
        alu_a = 0;
        alu_opcode = LDA_IMM;
        @(negedge clk);
        alu_result_expected = 8'h00;
                              // NV1BDIZC
        alu_status_expected = 8'b00100010;
        check;
 
        // ADC
        for (i = 0; i < 256; i = i + 1)
        begin
                alu_a = i;
                alu_opcode = LDA_IMM;
                @(negedge clk);
                alu_result_expected = i;
                alu_status_expected[Z] = (alu_a == 0) ? 1 : 0;
                alu_status_expected[N] = alu_a[7];
                check;
                for (j = 0; j < 256; j = j + 1)
                begin
                        alu_opcode = ADC_IMM;
                        alu_a = j;
                        @(negedge clk);
                        sign = alu_result_expected[7];
                        {alu_status_expected[C], alu_result_expected} = alu_result_expected + alu_a + alu_status_expected[C];
                        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                        alu_status_expected[N] = alu_result_expected[7];
                        alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                        check;
                end
        end
 
        // SBC
        for (i = 0; i < 256; i = i + 1)
        begin
                alu_a = i;
                alu_opcode = LDA_IMM;
                @(negedge clk);
                alu_result_expected = i;
                alu_status_expected[Z] = (alu_a == 0) ? 1 : 0;
                alu_status_expected[N] = alu_a[7];
                check;
                for (j = 0; j < 256; j = j + 1)
                begin
                        alu_opcode = SBC_IMM;
                        alu_a = j;
                        @(negedge clk);
                        sign = alu_result_expected[7];
                        alu_result_expected = alu_result_expected - alu_a - (1 - alu_status_expected[C]);
                        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                        alu_status_expected[N] = alu_result_expected[7];
                        alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] == alu_result_expected[7]));
                        alu_status_expected[C] = ~alu_result_expected[7];
                        check;
                end
        end
 
        // CLC
        alu_opcode = CLC_IMP;
        @(negedge clk);
        alu_status_expected[C] = 0;
        check;
 
/*
        // SED
        alu_opcode = SED_IMP;
        @(negedge clk);
        alu_status_expected[D] = 1;
        check;
 
        // ADC
        alu_opcode = ADC_IMM;
        alu_a = 8'h12;
        @(negedge clk);
        sign = alu_result_expected[7];
        AL = alu_a[3:0] + alu_result_expected[3:0] + alu_status_expected[C];
        $display("AL = %b", AL);
        AH = alu_a[7:4] + alu_result_expected[7:4] + AL[4];
        $display("AH = %b", AH);
        if (AL > 9) begin
          temp1 = AL - 6;
        end
        else begin
          temp1 = AL;
        end
        $display("temp1 = %b", temp1);
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
        if (AH > 9) begin
          temp2 = AH - 6;
        end
        else begin
          temp2 = AH;
        end
        $display("temp2 = %b", temp2);
        alu_status_expected[C] = (temp2 > 15) ? 1 : 0;
        alu_result_expected = {temp2[3:0],temp1[3:0]};
        $display("A = %b PS = %b", alu_result_expected, alu_status_expected);
        check;
 
        // CLD
        alu_opcode = CLD_IMP;
        @(negedge clk);
        alu_status_expected[D] = 0;
        check;
*/
/*
        // LDA
        alu_a = 0;
        alu_opcode = LDA_IMM;
        //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
        //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
        @(negedge clk);
        alu_result_expected = 8'h00;
        //                       NV1BDIZC
        alu_status_expected[N] = 0;
        alu_status_expected[Z] = 1;
        check;
 
        // SED
        alu_opcode = SED_IMP;
        //$display("A = %h B = %h X = %h Y = %h", alu_result, alu_a, alu_x, alu_y);
        @(negedge clk);
        alu_status_expected[D] = 1;
        check;
 
        // ADC
        alu_opcode = ADC_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = $random;
                //$display("A = %h B = %h C = %b X = %h Y = %h", alu_result, alu_a, alu_status_expected[C], alu_x, alu_y);
                @(negedge clk);
                AL = alu_result_expected[3:0] + alu_a[3:0] + alu_status_expected[C];
                AH = alu_result_expected[7:4] + alu_a[7:4] + AL[4];
                if (AL > 9) AL = AL + 6;
                if (AH > 9) AH = AH + 6;
                alu_status_expected[C] = AH[4];
                alu_result_expected = {AH[3:0],AL[3:0]};
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                check;
        end
        //$stop;
        // CLD
        alu_opcode = CLD_IMP;
        @(negedge clk);
        alu_status_expected[D] = 0;
        check;
*/
        // ASL
        alu_opcode = ASL_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                {alu_status_expected[C], alu_result_expected} = {alu_a,1'b0};
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // ROL
        alu_opcode = ROL_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                {alu_status_expected[C], alu_result_expected} = {alu_a,alu_status_expected[C]};
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // ROR
        alu_opcode = ROR_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                {alu_result_expected, alu_status_expected[C]} = {alu_status_expected[C],alu_a};
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // LDA
        alu_a = 137;
        alu_opcode = LDA_IMM;
        @(negedge clk);
        alu_result_expected = 8'd137;
        //                       NV1BDIZC
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        check;
 
        // EOR
        alu_opcode = EOR_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_result_expected = alu_a ^ alu_result_expected;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        /*
        // LDA
        alu_a = 0;
        alu_opcode = LDA_IMM;
    //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
        //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
        @(negedge clk);
        alu_result_expected = 8'h00;
        //                       NV1BDIZC
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        check;
 
        // SBC
        alu_opcode = SBC_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = 1;
                @(negedge clk);
                //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
                //$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
                //$display("op1 = %d op2 = %d  c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
                sign = alu_result_expected[7];
                alu_result_expected = alu_result_expected - alu_a - ( 1 - alu_status_expected[C]);
                alu_status_expected[C] = ~alu_result_expected[7];
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                //$display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]);
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                check;
        end
        */
 
        // LDA
        alu_opcode = LDA_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_result_expected = i;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // LDX
        alu_opcode = LDX_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_x_expected = alu_a;
                alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_x_expected[7];
                check;
        end
 
        // LDY
        alu_opcode = LDY_IMM;
        for (i = 0; i < 1001; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_y_expected = alu_a;
                alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_y_expected[7];
                check;
        end
 
        // STA
        alu_opcode = STA_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                check;
        end
 
        // STX
        alu_opcode = STX_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                check;
        end
 
        // STY
        alu_opcode = STY_ABS;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                check;
        end
 
        // CMP
        alu_opcode = CMP_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                temp1 = alu_result_expected - alu_a;
                alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;
                alu_status_expected[N] = temp1[7];
                alu_status_expected[C] = (alu_result_expected >= alu_a) ? 1 : 0;
                check;
        end
 
        // CPX
        alu_opcode = CPX_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                temp1 = alu_x_expected - alu_a;
                alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;
                alu_status_expected[N] = temp1[7];
                alu_status_expected[C] = (alu_x_expected >= alu_a) ? 1 : 0;
                check;
        end
 
        // CPY
        alu_opcode = CPY_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                temp1 = alu_y_expected - alu_a;
                alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;
                alu_status_expected[N] = temp1[7];
                alu_status_expected[C] = (alu_y_expected >= alu_a) ? 1 : 0;
                check;
        end
 
 
        // AND
        alu_opcode = AND_IMM;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_result_expected = alu_a & alu_result_expected;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // ASL
        alu_opcode = ASL_ACC;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_status_expected[C] = alu_result_expected[7];
                alu_result_expected[7:0] = alu_result_expected << 1;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // INC
        alu_opcode = INC_ZPG;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_result_expected = alu_a + 1;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // INX
        alu_opcode = INX_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_x_expected = alu_x_expected + 1;
                alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_x_expected[7];
                check;
        end
 
        // INY
        alu_opcode = INY_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_y_expected = alu_y_expected + 1;
                alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_y_expected[7];
                check;
        end
 
        // DEC
        alu_opcode = DEC_ZPG;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_result_expected = alu_a - 1;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                check;
        end
 
        // DEX
        alu_opcode = DEX_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_x_expected = alu_x_expected - 1;
                alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_x_expected[7];
                check;
        end
 
        // DEY
        alu_opcode = DEY_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_y_expected = alu_y_expected - 1;
                alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_y_expected[7];
                check;
        end
 
 
        // LDA
        alu_a = 0;
        alu_opcode = LDA_IMM;
        @(negedge clk);
        alu_result_expected = 8'h00;
        //                       NV1BDIZC
        alu_status_expected[Z] = 1;
        alu_status_expected[N] = 0;
        check;
 
        // BIT
        alu_opcode = BIT_ZPG;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
                alu_status_expected[V] = alu_a[6];
                alu_status_expected[N] = alu_a[7];
                check;
        end
 
        // RTI
        alu_opcode = RTI_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_status_expected[C] = alu_a[C];
                alu_status_expected[Z] = alu_a[Z];
                alu_status_expected[N] = alu_a[N];
                alu_status_expected[V] = alu_a[V];
                alu_status_expected[B] = alu_a[B];
                alu_status_expected[D] = alu_a[D];
                alu_status_expected[I] = alu_a[I];
                check;
        end
 
        // PLP
        alu_opcode = PLP_IMP;
        for (i = 0; i < 1000; i = i + 1)
        begin
                alu_a = i;
                @(negedge clk);
                alu_status_expected[C] = alu_a[C];
                alu_status_expected[Z] = alu_a[Z];
                alu_status_expected[N] = alu_a[N];
                alu_status_expected[V] = alu_a[V];
                alu_status_expected[B] = alu_a[B];
                alu_status_expected[D] = alu_a[D];
                alu_status_expected[I] = alu_a[I];
                check;
        end
 
        // PHA
        alu_opcode = PHA_IMP;
        @(negedge clk);
        check;
 
        // PHP
        alu_opcode = PHP_IMP;
        @(negedge clk);
        check;
 
        // BRK
        alu_opcode = BRK_IMP;
        @(negedge clk);
        alu_status_expected[B] = 1;
        check;
 
        // SEC
        alu_opcode = SEC_IMP;
        @(negedge clk);
        alu_status_expected[C] = 1;
        check;
 
        // SED
        alu_opcode = SED_IMP;
        @(negedge clk);
        alu_status_expected[D] = 1;
        check;
 
        // SEI
        alu_opcode = SEI_IMP;
        @(negedge clk);
        alu_status_expected[I] = 1;
        check;
 
        // CLC
        alu_opcode = CLC_IMP;
        @(negedge clk);
        alu_status_expected[C] = 0;
        check;
 
        // CLD
        alu_opcode = CLD_IMP;
        @(negedge clk);
        alu_status_expected[D] = 0;
        check;
 
        // CLI
        alu_opcode = CLI_IMP;
        @(negedge clk);
        alu_status_expected[I] = 0;
        check;
 
        // CLV
        alu_opcode = CLV_IMP;
        @(negedge clk);
        alu_status_expected[V] = 0;
        check;
 
        // LDA
        alu_opcode = LDA_IMM;
        alu_a = 8'h76;
        @(negedge clk);
        alu_result_expected = alu_a;
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        check;
 
        // TAX
        alu_opcode = TAX_IMP;
        @(negedge clk);
        alu_x_expected = alu_result_expected;
        alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_x_expected[7];
        check;
 
        // TAY
        alu_opcode = TAY_IMP;
        @(negedge clk);
        alu_y_expected = alu_result_expected;
        alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_y_expected[7];
        check;
 
        // TSX
        alu_opcode = TSX_IMP;
        @(negedge clk);
        alu_x_expected = alu_a;
        //alu_result_expected = alu_a;
        alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_x_expected[7];
        check;
 
        // TXA
        alu_opcode = TXA_IMP;
        @(negedge clk);
        alu_result_expected = alu_x_expected;
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        check;
 
        // TXS
        alu_opcode = TXS_IMP;
        @(negedge clk);
        alu_result_expected = alu_x_expected;
        check;
 
        // TYA
        alu_opcode = TYA_IMP;
        @(negedge clk);
        alu_result_expected = alu_y_expected;
        alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
        alu_status_expected[N] = alu_result_expected[7];
        check;
 
        // Nothing should happen
        // BCC
        alu_opcode = BCC_REL;
        @(negedge clk);
        check;
 
        // BCS
        alu_opcode = BCS_REL;
        @(negedge clk);
        check;
 
        // BEQ
        alu_opcode = BEQ_REL;
        @(negedge clk);
        check;
 
        // BMI
        alu_opcode = BMI_REL;
        @(negedge clk);
        check;
 
        // BNE
        alu_opcode = BNE_REL;
        @(negedge clk);
        check;
 
        // BPL
        alu_opcode = BPL_REL;
        @(negedge clk);
        check;
 
        // BVC
        alu_opcode = BVC_REL;
        @(negedge clk);
        check;
 
        // BVS
        alu_opcode = BVS_REL;
        @(negedge clk);
        check;
 
        // JMP
        alu_opcode = JMP_ABS;
        @(negedge clk);
        check;
 
        // JMP
        alu_opcode = JMP_IND;
        @(negedge clk);
        check;
 
        // JSR
        alu_opcode = JSR_ABS;
        @(negedge clk);
        check;
 
        // NOP
        alu_opcode = NOP_IMP;
        @(negedge clk);
        check;
 
        // RTS
        alu_opcode = RTS_IMP;
        @(negedge clk);
        check;
 
        $display("TEST PASSED");
        $finish;
end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	224	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU Testbench ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45	127	gabrielosh	`include "timescale.v"
46	224	creep
47	136	gabrielosh	`module t6507lp_alu_tb;`
48	127	gabrielosh
49	136	gabrielosh	`include "t6507lp_package.v"
50	127	gabrielosh
51	224	creep	`reg clk;`
52			`reg reset_n;`
53			`reg alu_enable;`
54			`wire [7:0] alu_result;`
55			`wire [7:0] alu_status;`
56			`reg [7:0] alu_opcode;`
57			`reg [7:0] alu_a;`
58			`wire [7:0] alu_x;`
59			`wire [7:0] alu_y;`
60	127	gabrielosh
61	224	creep	`integer i, j;`
62			`integer ADC_RESULTS, SBC_RESULTS;`
63
64	127	gabrielosh	`reg [7:0] alu_result_expected;`
65			`reg [7:0] alu_status_expected;`
66			`reg [7:0] alu_x_expected;`
67			`reg [7:0] alu_y_expected;`
68
69	224	creep	`reg C_in;`
70			`reg C_temp;`
71			`reg sign;`
72	181	gabrielosh	`reg [7:0] temp1;`
73			`reg [7:0] temp2;`
74	164	gabrielosh	`reg [3:0] AL;`
75			`reg [3:0] AH;`
76			`reg [3:0] BL;`
77			`reg [3:0] BH;`
78			`reg [7:0] alu_result_expected_temp;`
79	127	gabrielosh
80	136	gabrielosh	`t6507lp_alu DUT (`
81	224	creep	`.clk ( clk ),`
82			`.reset_n ( reset_n ),`
83			`.alu_enable (alu_enable),`
84			`.alu_result (alu_result),`
85			`.alu_status (alu_status),`
86			`.alu_opcode (alu_opcode),`
87			`.alu_a ( alu_a ),`
88			`.alu_x ( alu_x ),`
89			`.alu_y ( alu_y )`
90			`);`
91	127	gabrielosh
92
93			`localparam period = 10;`
94
95			`task check;`
96			`begin`
97			`$display(" RESULTS EXPECTED");`
98			`$display("alu_result %h %h ", alu_result, alu_result_expected);`
99			`$display("alu_status %b %b ", alu_status, alu_status_expected);`
100			`$display("alu_x %h %h ", alu_x, alu_x_expected );`
101			`$display("alu_y %h %h ", alu_y, alu_y_expected );`
102	150	gabrielosh	`if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y))`
103	127	gabrielosh	`begin`
104	150	gabrielosh	`$display("Instruction %h... OK!", alu_opcode);`
105	127	gabrielosh	`end`
106			`else`
107			`begin`
108	150	gabrielosh	`$display("ERROR at instruction %h",alu_opcode);`
109			`$finish;`
110	127	gabrielosh	`end`
111			`end`
112			`endtask`
113
114
115			`always begin`
116	136	gabrielosh	`#(period/2) clk = ~clk;`
117	127	gabrielosh	`end`
118
119			`initial`
120			`begin`
121	224	creep	`//ADC_RESULT = fopen("ADC_RESULTS.txt");`
122			`//SBC_RESULT = fopen("SBC_RESULTS.txt");`
123
124	127	gabrielosh	`// Reset`
125	136	gabrielosh	`clk = 0;`
126			`reset_n = 0;`
127	140	gabrielosh	`@(negedge clk);`
128	148	gabrielosh	`reset_n = 1;`
129	127	gabrielosh	`alu_enable = 1;`
130			`alu_result_expected = 8'h00;`
131			`alu_status_expected = 8'b00100010;`
132			`alu_x_expected = 8'h00;`
133			`alu_y_expected = 8'h00;`
134
135			`// LDA`
136			`alu_a = 0;`
137			`alu_opcode = LDA_IMM;`
138	140	gabrielosh	`@(negedge clk);`
139	127	gabrielosh	`alu_result_expected = 8'h00;`
140	224	creep	`// NV1BDIZC`
141			`alu_status_expected = 8'b00100010;`
142	173	gabrielosh	`check;`
143	127	gabrielosh
144			`// ADC`
145	224	creep	`for (i = 0; i < 256; i = i + 1)`
146	127	gabrielosh	`begin`
147	224	creep	`alu_a = i;`
148			`alu_opcode = LDA_IMM;`
149	140	gabrielosh	`@(negedge clk);`
150	224	creep	`alu_result_expected = i;`
151			`alu_status_expected[Z] = (alu_a == 0) ? 1 : 0;`
152			`alu_status_expected[N] = alu_a[7];`
153	173	gabrielosh	`check;`
154	224	creep	`for (j = 0; j < 256; j = j + 1)`
155			`begin`
156			`alu_opcode = ADC_IMM;`
157			`alu_a = j;`
158			`@(negedge clk);`
159			`sign = alu_result_expected[7];`
160			`{alu_status_expected[C], alu_result_expected} = alu_result_expected + alu_a + alu_status_expected[C];`
161			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
162			`alu_status_expected[N] = alu_result_expected[7];`
163			`alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));`
164			`check;`
165			`end`
166	127	gabrielosh	`end`
167	169	gabrielosh
168	224	creep	`// SBC`
169			`for (i = 0; i < 256; i = i + 1)`
170			`begin`
171			`alu_a = i;`
172			`alu_opcode = LDA_IMM;`
173			`@(negedge clk);`
174			`alu_result_expected = i;`
175			`alu_status_expected[Z] = (alu_a == 0) ? 1 : 0;`
176			`alu_status_expected[N] = alu_a[7];`
177			`check;`
178			`for (j = 0; j < 256; j = j + 1)`
179			`begin`
180			`alu_opcode = SBC_IMM;`
181			`alu_a = j;`
182			`@(negedge clk);`
183			`sign = alu_result_expected[7];`
184			`alu_result_expected = alu_result_expected - alu_a - (1 - alu_status_expected[C]);`
185			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
186			`alu_status_expected[N] = alu_result_expected[7];`
187			`alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] == alu_result_expected[7]));`
188			`alu_status_expected[C] = ~alu_result_expected[7];`
189			`check;`
190			`end`
191			`end`
192
193	186	gabrielosh	`// CLC`
194			`alu_opcode = CLC_IMP;`
195			`@(negedge clk);`
196			`alu_status_expected[C] = 0;`
197			`check;`
198
199	224	creep	`/*`
200	186	gabrielosh	`// SED`
201			`alu_opcode = SED_IMP;`
202			`@(negedge clk);`
203			`alu_status_expected[D] = 1;`
204			`check;`
205	224	creep
206	186	gabrielosh	`// ADC`
207			`alu_opcode = ADC_IMM;`
208			`alu_a = 8'h12;`
209			`@(negedge clk);`
210			`sign = alu_result_expected[7];`
211			`AL = alu_a[3:0] + alu_result_expected[3:0] + alu_status_expected[C];`
212			`$display("AL = %b", AL);`
213			`AH = alu_a[7:4] + alu_result_expected[7:4] + AL[4];`
214			`$display("AH = %b", AH);`
215			`if (AL > 9) begin`
216			`temp1 = AL - 6;`
217			`end`
218			`else begin`
219			`temp1 = AL;`
220			`end`
221			`$display("temp1 = %b", temp1);`
222			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
223			`alu_status_expected[N] = alu_result_expected[7];`
224			`alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));`
225			`if (AH > 9) begin`
226			`temp2 = AH - 6;`
227			`end`
228			`else begin`
229			`temp2 = AH;`
230			`end`
231			`$display("temp2 = %b", temp2);`
232			`alu_status_expected[C] = (temp2 > 15) ? 1 : 0;`
233			`alu_result_expected = {temp2[3:0],temp1[3:0]};`
234			`$display("A = %b PS = %b", alu_result_expected, alu_status_expected);`
235			`check;`
236
237			`// CLD`
238			`alu_opcode = CLD_IMP;`
239			`@(negedge clk);`
240			`alu_status_expected[D] = 0;`
241			`check;`
242	224	creep	`*/`
243			`/*`
244	161	gabrielosh	`// LDA`
245			`alu_a = 0;`
246			`alu_opcode = LDA_IMM;`
247			`//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);`
248			`//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);`
249			`@(negedge clk);`
250			`alu_result_expected = 8'h00;`
251			`// NV1BDIZC`
252	164	gabrielosh	`alu_status_expected[N] = 0;`
253			`alu_status_expected[Z] = 1;`
254	173	gabrielosh	`check;`
255	224	creep
256	164	gabrielosh	`// SED`
257			`alu_opcode = SED_IMP;`
258	181	gabrielosh	`//$display("A = %h B = %h X = %h Y = %h", alu_result, alu_a, alu_x, alu_y);`
259	164	gabrielosh	`@(negedge clk);`
260			`alu_status_expected[D] = 1;`
261	173	gabrielosh	`check;`
262	161	gabrielosh
263			`// ADC`
264			`alu_opcode = ADC_IMM;`
265			`for (i = 0; i < 1000; i = i + 1)`
266			`begin`
267			`alu_a = $random;`
268	181	gabrielosh	`//$display("A = %h B = %h C = %b X = %h Y = %h", alu_result, alu_a, alu_status_expected[C], alu_x, alu_y);`
269	161	gabrielosh	`@(negedge clk);`
270	186	gabrielosh	`AL = alu_result_expected[3:0] + alu_a[3:0] + alu_status_expected[C];`
271			`AH = alu_result_expected[7:4] + alu_a[7:4] + AL[4];`
272			`if (AL > 9) AL = AL + 6;`
273			`if (AH > 9) AH = AH + 6;`
274			`alu_status_expected[C] = AH[4];`
275			`alu_result_expected = {AH[3:0],AL[3:0]};`
276	161	gabrielosh	`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
277			`alu_status_expected[N] = alu_result_expected[7];`
278			`alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));`
279	173	gabrielosh	`check;`
280	179	gabrielosh	`end`
281	181	gabrielosh	`//$stop;`
282	179	gabrielosh	`// CLD`
283			`alu_opcode = CLD_IMP;`
284			`@(negedge clk);`
285			`alu_status_expected[D] = 0;`
286			`check;`
287	184	gabrielosh	`*/`
288	148	gabrielosh	`// ASL`
289	145	gabrielosh	`alu_opcode = ASL_ABS;`
290			`for (i = 0; i < 1000; i = i + 1)`
291			`begin`
292			`alu_a = i;`
293			`@(negedge clk);`
294			`{alu_status_expected[C], alu_result_expected} = {alu_a,1'b0};`
295			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
296			`alu_status_expected[N] = alu_result_expected[7];`
297	173	gabrielosh	`check;`
298	145	gabrielosh	`end`
299
300	186	gabrielosh	`// ROL`
301			`alu_opcode = ROL_ABS;`
302			`for (i = 0; i < 1000; i = i + 1)`
303			`begin`
304			`alu_a = i;`
305			`@(negedge clk);`
306			`{alu_status_expected[C], alu_result_expected} = {alu_a,alu_status_expected[C]};`
307			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
308			`alu_status_expected[N] = alu_result_expected[7];`
309			`check;`
310	224	creep	`end`
311	186	gabrielosh
312			`// ROR`
313			`alu_opcode = ROR_ABS;`
314			`for (i = 0; i < 1000; i = i + 1)`
315			`begin`
316			`alu_a = i;`
317			`@(negedge clk);`
318			`{alu_result_expected, alu_status_expected[C]} = {alu_status_expected[C],alu_a};`
319			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
320			`alu_status_expected[N] = alu_result_expected[7];`
321			`check;`
322	224	creep	`end`
323	186	gabrielosh
324	145	gabrielosh	`// LDA`
325	156	gabrielosh	`alu_a = 137;`
326			`alu_opcode = LDA_IMM;`
327			`@(negedge clk);`
328			`alu_result_expected = 8'd137;`
329			`// NV1BDIZC`
330			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
331			`alu_status_expected[N] = alu_result_expected[7];`
332	173	gabrielosh	`check;`
333	156	gabrielosh
334			`// EOR`
335			`alu_opcode = EOR_IMM;`
336			`for (i = 0; i < 1000; i = i + 1)`
337			`begin`
338			`alu_a = i;`
339			`@(negedge clk);`
340			`alu_result_expected = alu_a ^ alu_result_expected;`
341			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
342			`alu_status_expected[N] = alu_result_expected[7];`
343	173	gabrielosh	`check;`
344	156	gabrielosh	`end`
345
346	224	creep	`/*`
347	156	gabrielosh	`// LDA`
348	145	gabrielosh	`alu_a = 0;`
349			`alu_opcode = LDA_IMM;`
350			`//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);`
351			`//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);`
352			`@(negedge clk);`
353			`alu_result_expected = 8'h00;`
354			`// NV1BDIZC`
355			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
356			`alu_status_expected[N] = alu_result_expected[7];`
357	173	gabrielosh	`check;`
358	145	gabrielosh
359	127	gabrielosh	`// SBC`
360			`alu_opcode = SBC_IMM;`
361			`for (i = 0; i < 1000; i = i + 1)`
362			`begin`
363	145	gabrielosh	`alu_a = 1;`
364	140	gabrielosh	`@(negedge clk);`
365	174	gabrielosh	`//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);`
366			`//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);`
367			`//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);`
368	156	gabrielosh	`sign = alu_result_expected[7];`
369	174	gabrielosh	`alu_result_expected = alu_result_expected - alu_a - ( 1 - alu_status_expected[C]);`
370			`alu_status_expected[C] = ~alu_result_expected[7];`
371	127	gabrielosh	`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
372			`alu_status_expected[N] = alu_result_expected[7];`
373	174	gabrielosh	`//$display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]);`
374	156	gabrielosh	`alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));`
375	173	gabrielosh	`check;`
376	127	gabrielosh	`end`
377	224	creep	`*/`
378	127	gabrielosh
379			`// LDA`
380			`alu_opcode = LDA_IMM;`
381			`for (i = 0; i < 1000; i = i + 1)`
382			`begin`
383			`alu_a = i;`
384	140	gabrielosh	`@(negedge clk);`
385	127	gabrielosh	`alu_result_expected = i;`
386			`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
387			`alu_status_expected[N] = alu_result_expected[7];`
388	173	gabrielosh	`check;`
389	127	gabrielosh	`end`
390
391			`// LDX`
392			`alu_opcode = LDX_IMM;`
393			`for (i = 0; i < 1000; i = i + 1)`
394			`begin`
395			`alu_a = i;`
396	140	gabrielosh	`@(negedge clk);`
397	178	gabrielosh	`alu_x_expected = alu_a;`
398	127	gabrielosh	`alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;`
399			`alu_status_expected[N] = alu_x_expected[7];`
400	173	gabrielosh	`check;`
401	127	gabrielosh	`end`
402
403			`// LDY`
404			`alu_opcode = LDY_IMM;`
405			`for (i = 0; i < 1001; i = i + 1)`
406			`begin`
407			`alu_a = i;`
408	140	gabrielosh	`@(negedge clk);`
409	178	gabrielosh	`alu_y_expected = alu_a;`
410	127	gabrielosh	`alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;`
411			`alu_status_expected[N] = alu_y_expected[7];`
412	173	gabrielosh	`check;`
413	127	gabrielosh	`end`
414
415			`// STA`
416			`alu_opcode = STA_ABS;`
417			`for (i = 0; i < 1000; i = i + 1)`
418			`begin`
419			`alu_a = i;`
420	140	gabrielosh	`@(negedge clk);`
421	173	gabrielosh	`check;`
422	127	gabrielosh	`end`
423
424			`// STX`
425			`alu_opcode = STX_ABS;`
426			`for (i = 0; i < 1000; i = i + 1)`
427			`begin`
428			`alu_a = i;`
429	140	gabrielosh	`@(negedge clk);`
430	173	gabrielosh	`check;`
431	127	gabrielosh	`end`
432
433			`// STY`
434			`alu_opcode = STY_ABS;`
435			`for (i = 0; i < 1000; i = i + 1)`
436			`begin`
437			`alu_a = i;`
438	140	gabrielosh	`@(negedge clk);`
439	173	gabrielosh	`check;`
440	127	gabrielosh	`end`
441
442			`// CMP`
443			`alu_opcode = CMP_IMM;`
444			`for (i = 0; i < 1000; i = i + 1)`
445			`begin`
446			`alu_a = i;`
447	140	gabrielosh	`@(negedge clk);`
448	181	gabrielosh	`temp1 = alu_result_expected - alu_a;`
449			`alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;`
450			`alu_status_expected[N] = temp1[7];`
451	127	gabrielosh	`alu_status_expected[C] = (alu_result_expected >= alu_a) ? 1 : 0;`
452	173	gabrielosh	`check;`
453	127	gabrielosh	`end`
454
455			`// CPX`
456			`alu_opcode = CPX_IMM;`
457			`for (i = 0; i < 1000; i = i + 1)`
458			`begin`
459			`alu_a = i;`
460	140	gabrielosh	`@(negedge clk);`
461	181	gabrielosh	`temp1 = alu_x_expected - alu_a;`
462			`alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;`
463			`alu_status_expected[N] = temp1[7];`
464	127	gabrielosh	`alu_status_expected[C] = (alu_x_expected >= alu_a) ? 1 : 0;`
465	173	gabrielosh	`check;`
466	127	gabrielosh	`end`
467
468			`// CPY`
469			`alu_opcode = CPY_IMM;`
470			`for (i = 0; i < 1000; i = i + 1)`
471			`begin`
472			`alu_a = i;`
473	140	gabrielosh	`@(negedge clk);`
474	181	gabrielosh	`temp1 = alu_y_expected - alu_a;`
475			`alu_status_expected[Z] = (temp1 == 0) ? 1 : 0;`
476			`alu_status_expected[N] = temp1[7];`
477	127	gabrielosh	`alu_status_expected[C] = (alu_y_expected >= alu_a) ? 1 : 0;`
478	173	gabrielosh	`check;`
479	127	gabrielosh	`end`
480
481
482			`// AND`
483			`alu_opcode = AND_IMM;`
484			`for (i = 0; i < 1000; i = i + 1)`
485			`begin`
486			`alu_a = i;`
487	140	gabrielosh	`@(negedge clk);`
488	156	gabrielosh	`alu_result_expected = alu_a & alu_result_expected;`
489	127	gabrielosh	`alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;`
490			`alu_status_expected[N] = alu_result_expected[7];`
491	173	gabrielosh	`check;`
492	127	gabrielosh	`end`
493
494			`// ASL`
495			`alu_opcode = ASL_ACC;`
496			`for (i = 0; i < 1000; i = i + 1)`
497			`begin`
498			`alu_a = i;`
499	140	gabrielosh	`@(negedge clk);`
500	127	gabrielosh	`alu_status_expected[C] = alu_result_expected[7];`

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Blame information for rev 255