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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_wrapper.v] - Blame information for rev 206

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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// T6507LP IP Core                                                    ////
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////                                                                    ////
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//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
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////                                                                    ////
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//// Description                                                        ////
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//// 6507 ALU wrapper                                                   ////
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////                                                                    ////
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//// TODO:                                                              ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
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////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
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//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
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//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
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//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "t6507lp_alu.v"
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module t6507lp_alu_wrapper();
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        parameter [3:0] DATA_SIZE = 4'd8;
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        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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        // all inputs are regs
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        reg clk;
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        reg reset_n;
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        reg alu_enable;
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        reg [DATA_SIZE_:0] alu_opcode;
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        reg [DATA_SIZE_:0] alu_a;
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        // all outputs are wires
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        wire [DATA_SIZE_:0] alu_result;
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        wire [DATA_SIZE_:0] alu_status;
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        wire [DATA_SIZE_:0] alu_x;
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        wire [DATA_SIZE_:0] alu_y;
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        initial clk = 0;
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        always #10 clk <= ~clk;
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        always @(posedge clk) begin
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                //$display("reset is %b", reset_n);
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                //$display("alu_enable is %b", alu_enable);
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                //$display("alu_opcode is %h", alu_opcode);
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                //$display("alu_a is %d", alu_a);
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        end
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        t6507lp_alu t6507lp_alu (
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                .clk            (clk),
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                .reset_n        (reset_n),
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                .alu_enable     (alu_enable),
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                .alu_result     (alu_result),
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                .alu_status     (alu_status),
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                .alu_opcode     (alu_opcode),
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                .alu_a          (alu_a),
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                .alu_x          (alu_x),
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                .alu_y          (alu_y)
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        );
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endmodule

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