URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Blame information for rev 101

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix relative mode, bit 7 means negative                          ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
        parameter DATA_SIZE = 8;
        parameter ADDR_SIZE = 13;
 
        localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        input reset_n;
        input [DATA_SIZE_:0] alu_result;
        input [DATA_SIZE_:0] alu_status;
        input [DATA_SIZE_:0] data_in;
        output reg [ADDR_SIZE_:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;
        output reg [DATA_SIZE_:0] alu_opcode;
        output reg [DATA_SIZE_:0] alu_a;
        output reg alu_enable;
 
        input [DATA_SIZE_:0] alu_x;
        input [DATA_SIZE_:0] alu_y;
 
        // FSM states
        localparam FETCH_OP = 5'b00000;
        localparam FETCH_OP_CALC = 5'b00001;
        localparam FETCH_LOW = 5'b00010;
        localparam FETCH_HIGH = 5'b00011;
        localparam READ_MEM = 5'b00100;
        localparam DUMMY_WRT_CALC = 5'b00101;
        localparam WRITE_MEM = 5'b00110;
        localparam FETCH_OP_CALC_PARAM = 5'b00111;
        localparam READ_MEM_CALC_INDEX = 5'b01000;
        localparam FETCH_HIGH_CALC_INDEX = 5'b01001;
        localparam READ_MEM_FIX_ADDR = 5'b01010;
        localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
        localparam FETCH_OP_FIX_PC = 5'b01100;
        localparam READ_FROM_POINTER = 5'b01101;
        localparam READ_FROM_POINTER_X = 5'b01110;
        localparam READ_FROM_POINTER_X1 = 5'b01111;
 
        localparam RESET = 5'b11111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE_:0] pc;           // program counter
        reg [DATA_SIZE_:0] sp;           // stack pointer
        reg [DATA_SIZE_:0] ir;           // instruction register
        reg [ADDR_SIZE_:0] temp_addr;    // temporary address
        reg [DATA_SIZE_:0] temp_data;    // temporary data
 
        reg [4:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
        // wiring that simplifies the FSM logic
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirectx;
        reg indirecty;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
        reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
        reg jump_indirect;
 
        wire [ADDR_SIZE_:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
        reg page_crossed;                       // so the simple assign was changed into a combinational always block
 
        reg branch;
 
        always @(*) begin
                address_plus_index = 0;
                page_crossed = 0;
 
                if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
                        {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                        address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
                end
                else if (branch) begin
                        if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
                                {page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
                                address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
                        end                                                             // solution: add a temp reg i guess
                end
                else if (state == READ_FROM_POINTER) begin
                        if (indirectx) begin
                                {page_crossed, address_plus_index[7:0]} = temp_data + index;
                                address_plus_index[12:8] = 5'b00000;
                        end
                        else if (jump_indirect) begin
                                address_plus_index[7:0] = temp_addr + 8'h01;
                                address_plus_index[12:8] = 5'b00000;
                        end
                        else begin // indirecty falls here
                                address_plus_index[7:0] = temp_data + 8'h01;
                                address_plus_index[12:8] = 5'b00000;
                        end
                end
                else if (state == READ_FROM_POINTER_X) begin
                        {page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
                        address_plus_index[12:8] = 5'b00000;
                end
                else if (state == READ_FROM_POINTER_X1) begin
                        {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                        address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
                end
        end
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
                        ir <= 8'h00;
                        temp_addr <= 0;
                        temp_data <= 8'h00;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 0;
                        control <= MEM_READ;
                        data_out <= 8'h00;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin
                                        // The processor was reset
                                        $write("under reset");
                                end
                                FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
                                                // the last cycle was a memory write.
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                control <= MEM_READ;
                                        end
                                        else if (immediate || relative) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute || absolute_indexed || jump_indirect) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_addr <= {{5{1'b0}},data_in};
                                                temp_data <= 8'h00;
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        else if (zero_page_indexed) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}}, data_in};
                                                temp_addr <= {{5{1'b0}}, data_in};
                                                control <= MEM_READ;
                                        end
                                        else if (indirectx || indirecty) begin
                                                pc <= next_pc;
                                                address <= data_in;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                        end
                                end
                                FETCH_HIGH_CALC_INDEX: begin
                                        pc <= next_pc;
                                        temp_addr[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], address_plus_index[7:0]};
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                FETCH_OP_EVAL_BRANCH: begin
                                        if (branch) begin
                                                pc <= {{5{1'b0}}, address_plus_index[7:0]};
                                                address <= {{5{1'b0}}, address_plus_index[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                                ir <= data_in;
                                        end
                                end
                                FETCH_OP_FIX_PC: begin
                                        if (page_crossed) begin
                                                pc[12:8] <= address_plus_index[12:8];
                                                address[12:8] <= address_plus_index[12:8];
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                ir <= data_in;
                                        end
                                end
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        //else begin
                                        //      $write("FETCHHIGH PROBLEM"); 
                                        //      $finish(0); 
                                        //end
                                end
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                control <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                end
                                READ_MEM_CALC_INDEX: begin
                                                //pc <= next_pc; // pc was  already updated in the previous cycle
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
 
                                end
                                READ_MEM_FIX_ADDR: begin
                                        if (read) begin
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
 
                                                if (page_crossed) begin
                                                        address <= address_plus_index;
                                                        temp_addr <= address_plus_index;
                                                end
                                                else begin
                                                        address <= pc;
                                                        temp_data <= data_in;
                                                end
                                        end
                                        else if (write) begin
                                                control <= MEM_WRITE;
                                                data_out <= alu_result;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                        end
                                        else begin // read modify write
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
                                        end
                                end
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        control <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                READ_FROM_POINTER: begin
                                        if (jump_indirect) begin
                                                pc[7:0] <= data_in;
                                                control <= MEM_READ;
                                                address <= address_plus_index;
                                        end
                                        else begin
                                                pc <= pc;
                                                control <= MEM_READ;
 
                                                if (indirectx) begin
                                                        address <= address_plus_index;
                                                end
                                                else begin // indirecty falls here
                                                        address <= address_plus_index;
                                                        temp_addr <= {{5{1'b0}}, data_in};
                                                end
                                        end
                                end
                                READ_FROM_POINTER_X: begin
                                        pc <= pc;
                                        address <= address_plus_index;
                                        temp_addr[7:0] <= data_in;
                                        control <= MEM_READ;
                                end
                                READ_FROM_POINTER_X1: begin
                                        if (jump_indirect) begin
                                                pc[12:8] <= data_in[4:0];
                                                control <= MEM_READ;
                                                address <= {data_in[4:0], pc[7:0]};
                                        end
                                        else if (indirectx) begin
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                end
                                        end
                                        else begin // indirecty falls here
                                                address <= address_plus_index;
                                                temp_addr[12:8] <= data_in;
                                                control <= MEM_READ;
                                        end
                                end
                                default: begin
                                        $write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the output logic always block
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
 
                next_state = RESET; // this prevents the latch
 
                case (state)
                        RESET: begin
                                next_state = FETCH_OP;
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        //FETCH_OP_CALC: begin // so far no addressing mode required the use of this state
                        //      next_state = FETCH_LOW;
                        //      alu_opcode = ir;
                        //      alu_enable = 1'b1;
                        //end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                        else begin
                                                $write("unknown behavior");
                                                $finish(0);
                                        end
                                end
                                else if (zero_page_indexed) begin
                                        next_state = READ_MEM_CALC_INDEX;
                                end
                                else if (absolute || jump_indirect) begin // at least the absolute address mode falls here
                                        next_state = FETCH_HIGH;
                                        if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                end
                                else if (absolute_indexed) begin
                                        next_state = FETCH_HIGH_CALC_INDEX;
                                end
                                else if (relative) begin
                                        next_state = FETCH_OP_EVAL_BRANCH;
                                end
                                else if (indirectx || indirecty) begin
                                        next_state = READ_FROM_POINTER;
                                end
                        end
                        READ_FROM_POINTER: begin
                                if (indirectx) begin
                                        next_state = READ_FROM_POINTER_X;
                                end
                                else begin // indirecty and jump indirect falls here
                                        next_state = READ_FROM_POINTER_X1;
                                end
                        end
                        READ_FROM_POINTER_X: begin
                                next_state = READ_FROM_POINTER_X1;
                        end
                        READ_FROM_POINTER_X1: begin
                                if (jump_indirect) begin
                                        next_state = FETCH_OP;
                                end
                                else if (indirecty) begin
                                        next_state = READ_MEM_FIX_ADDR;
                                end
                                else begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                next_state = WRITE_MEM;
                                        end
                                end
                        end
                        FETCH_OP_EVAL_BRANCH: begin
                                if (branch) begin
                                        next_state = FETCH_OP_FIX_PC;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_OP_FIX_PC: begin
                                if (page_crossed) begin
                                        next_state = FETCH_OP;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_HIGH_CALC_INDEX: begin
                                next_state = READ_MEM_FIX_ADDR;
                        end
                        READ_MEM_FIX_ADDR: begin
                                if (read) begin
                                        if (page_crossed) begin
                                                next_state = READ_MEM;
                                        end
                                        else begin
                                                next_state = FETCH_OP_CALC_PARAM;
                                        end
                                end
                                else if (read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                        alu_enable = 1'b1;
                                        alu_opcode = ir;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        FETCH_HIGH: begin
                                if (jump_indirect) begin
                                        next_state = READ_FROM_POINTER;
                                end
                                else if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM_CALC_INDEX: begin
                                if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirectx = 1'b0;
                indirecty = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                index = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
                jump_indirect = 1'b0;
                branch = 1'b0;
 
                case (ir)
                        BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                        PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                                index = alu_x;
                        end
                        LDX_ZPY, STX_ZPY: begin
                                zero_page_indexed = 1'b1;
                                index = alu_y;
                        end
                        BCC_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BCS_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BEQ_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[Z]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BNE_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[Z] == 1'b0) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BPL_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BMI_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVC_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVS_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JSR_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX: begin
                                absolute_indexed = 1'b1;
                                index = alu_x;
                        end
                        ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                                index = alu_y;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX: begin
                                indirectx = 1'b1;
                                index = alu_x;
                        end
                        ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, ORA_IDY, SBC_IDY, STA_IDY: begin
                                indirecty = 1'b1;
                                index = alu_y;
                        end
                        JMP_ABS: begin
                                absolute = 1'b1;
                                jump = 1'b1;
                        end
                        JMP_IND: begin
                                jump_indirect = 1'b1;
                        end
                        default: begin
                                $write("state : %b", state);
                                if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
                                        $write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                        $finish();
                                end
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
        end
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12	96	creep	`//// - Fix relative mode, bit 7 means negative ////`
13	61	creep	`//// - Code the indirect indexed mode ////`
14			`//// - Code the absolute indirect mode ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
18			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
19			`//// ////`
20			`////////////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`////////////////////////////////////////////////////////////////////////////`
46
47			`timescale 1ns / 1ps
48
49	86	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`
50	87	creep	`parameter DATA_SIZE = 8;`
51			`parameter ADDR_SIZE = 13;`
52	68	creep
53	83	creep	`localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;`
54			`localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
55	82	creep
56	71	creep	`input clk;`
57			`input reset_n;`
58	82	creep	`input [DATA_SIZE_:0] alu_result;`
59			`input [DATA_SIZE_:0] alu_status;`
60			`input [DATA_SIZE_:0] data_in;`
61			`output reg [ADDR_SIZE_:0] address;`
62	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
63	82	creep	`output reg [DATA_SIZE_:0] data_out;`
64			`output reg [DATA_SIZE_:0] alu_opcode;`
65			`output reg [DATA_SIZE_:0] alu_a;`
66	68	creep	`output reg alu_enable;`
67	61	creep
68	86	creep	`input [DATA_SIZE_:0] alu_x;`
69			`input [DATA_SIZE_:0] alu_y;`
70	68	creep
71	61	creep	`// FSM states`
72	95	creep	`localparam FETCH_OP = 5'b00000;`
73			`localparam FETCH_OP_CALC = 5'b00001;`
74			`localparam FETCH_LOW = 5'b00010;`
75			`localparam FETCH_HIGH = 5'b00011;`
76			`localparam READ_MEM = 5'b00100;`
77			`localparam DUMMY_WRT_CALC = 5'b00101;`
78			`localparam WRITE_MEM = 5'b00110;`
79			`localparam FETCH_OP_CALC_PARAM = 5'b00111;`
80			`localparam READ_MEM_CALC_INDEX = 5'b01000;`
81			`localparam FETCH_HIGH_CALC_INDEX = 5'b01001;`
82			`localparam READ_MEM_FIX_ADDR = 5'b01010;`
83			`localparam FETCH_OP_EVAL_BRANCH = 5'b01011;`
84			`localparam FETCH_OP_FIX_PC = 5'b01100;`
85			`localparam READ_FROM_POINTER = 5'b01101;`
86			`localparam READ_FROM_POINTER_X = 5'b01110;`
87			`localparam READ_FROM_POINTER_X1 = 5'b01111;`
88	61	creep
89	95	creep	`localparam RESET = 5'b11111;`
90
91	61	creep	`// OPCODES TODO: verify how this get synthesised`
92			`include "../T6507LP_Package.v"
93
94			`// control signals`
95			`localparam MEM_READ = 1'b0;`
96			`localparam MEM_WRITE = 1'b1;`
97
98	82	creep	`reg [ADDR_SIZE_:0] pc; // program counter`
99			`reg [DATA_SIZE_:0] sp; // stack pointer`
100			`reg [DATA_SIZE_:0] ir; // instruction register`
101			`reg [ADDR_SIZE_:0] temp_addr; // temporary address`
102			`reg [DATA_SIZE_:0] temp_data; // temporary data`
103	61	creep
104	96	creep	`reg [4:0] state, next_state; // current and next state registers`
105	61	creep	`// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.`
106
107			`// wiring that simplifies the FSM logic`
108			`reg absolute;`
109			`reg absolute_indexed;`
110			`reg accumulator;`
111			`reg immediate;`
112			`reg implied;`
113	95	creep	`reg indirectx;`
114			`reg indirecty;`
115	61	creep	`reg relative;`
116			`reg zero_page;`
117			`reg zero_page_indexed;`
118	86	creep	`reg [DATA_SIZE_:0] index; // will be assigned with either X or Y`
119	61	creep
120			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
121			`reg read;`
122			`reg read_modify_write;`
123			`reg write;`
124			`reg jump;`
125	101	creep	`reg jump_indirect;`
126	61	creep
127	82	creep	`wire [ADDR_SIZE_:0] next_pc;`
128	63	creep	`assign next_pc = pc + 13'b0000000000001;`
129	61	creep
130	87	creep	`reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.`
131			`reg page_crossed; // so the simple assign was changed into a combinational always block`
132
133	94	creep	`reg branch;`
134
135	87	creep	`always @(*) begin`
136			`address_plus_index = 0;`
137			`page_crossed = 0;`
138	86	creep
139	88	creep	`if (state == READ_MEM_CALC_INDEX \|\| state == READ_MEM_FIX_ADDR \|\| state == FETCH_HIGH_CALC_INDEX) begin`
140			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
141			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
142	87	creep	`end`
143	94	creep	`else if (branch) begin`
144			`if (state == FETCH_OP_FIX_PC \|\| state == FETCH_OP_EVAL_BRANCH) begin`
145			`{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;`
146			`address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure`
147			`end // solution: add a temp reg i guess`
148			`end`
149	95	creep	`else if (state == READ_FROM_POINTER) begin`
150	96	creep	`if (indirectx) begin`
151			`{page_crossed, address_plus_index[7:0]} = temp_data + index;`
152			`address_plus_index[12:8] = 5'b00000;`
153			`end`
154	101	creep	`else if (jump_indirect) begin`
155			`address_plus_index[7:0] = temp_addr + 8'h01;`
156			`address_plus_index[12:8] = 5'b00000;`
157			`end`
158	96	creep	`else begin // indirecty falls here`
159			`address_plus_index[7:0] = temp_data + 8'h01;`
160			`address_plus_index[12:8] = 5'b00000;`
161			`end`
162	95	creep	`end`
163			`else if (state == READ_FROM_POINTER_X) begin`
164			`{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;`
165			`address_plus_index[12:8] = 5'b00000;`
166			`end`
167	96	creep	`else if (state == READ_FROM_POINTER_X1) begin`
168			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
169			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
170			`end`
171	87	creep	`end`
172
173	71	creep	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
174			`if (reset_n == 1'b0) begin`
175			`// all registers must assume default values`
176	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
177			`sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.`
178	82	creep	`ir <= 8'h00;`
179	71	creep	`temp_addr <= 0;`
180	82	creep	`temp_data <= 8'h00;`
181	68	creep	`state <= RESET;`
182	71	creep	`// registered outputs also receive default values`
183			`address <= 0;`
184	82	creep	`control <= MEM_READ;`
185			`data_out <= 8'h00;`
186	61	creep	`end`
187			`else begin`
188			`state <= next_state;`
189	83	creep
190	61	creep	`case (state)`
191	68	creep	`RESET: begin`
192	82	creep	`// The processor was reset`
193			`$write("under reset");`
194	68	creep	`end`
195	61	creep	`FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or`
196			`// the last cycle was a memory write.`
197			`pc <= next_pc;`
198	71	creep	`address <= next_pc;`
199	83	creep	`control <= MEM_READ;`
200	70	creep	`ir <= data_in;`
201	61	creep	`end`
202	71	creep	`FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
203	61	creep	`pc <= next_pc;`
204	71	creep	`address <= next_pc;`
205	83	creep	`control <= MEM_READ;`
206	70	creep	`ir <= data_in;`
207	61	creep	`end`
208	68	creep	`FETCH_LOW: begin // in this state the opcode is already known so truly execution begins`
209			`if (accumulator \|\| implied) begin`
210	70	creep	`pc <= pc; // is this better?`
211	71	creep	`address <= pc;`
212	83	creep	`control <= MEM_READ;`
213	61	creep	`end`
214	94	creep	`else if (immediate \|\| relative) begin`
215	68	creep	`pc <= next_pc;`
216	71	creep	`address <= next_pc;`
217	83	creep	`control <= MEM_READ;`
218	70	creep	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
219	61	creep	`end`
220	101	creep	`else if (absolute \|\| absolute_indexed \|\| jump_indirect) begin`
221	71	creep	`pc <= next_pc;`
222			`address <= next_pc;`
223	83	creep	`control <= MEM_READ;`
224	87	creep	`temp_addr <= {{5{1'b0}},data_in};`
225	101	creep	`temp_data <= 8'h00;`
226	71	creep	`end`
227	77	creep	`else if (zero_page) begin`
228			`pc <= next_pc;`
229			`address <= {{5{1'b0}},data_in};`
230	78	creep	`temp_addr <= {{5{1'b0}},data_in};`
231
232	77	creep	`if (write) begin`
233			`control <= MEM_WRITE;`
234	78	creep	`data_out <= alu_result;`
235	77	creep	`end`
236	83	creep	`else begin`
237			`control <= MEM_READ;`
238			`data_out <= 8'h00;`
239			`end`
240	77	creep	`end`
241	86	creep	`else if (zero_page_indexed) begin`
242			`pc <= next_pc;`
243	94	creep	`address <= {{5{1'b0}}, data_in};`
244			`temp_addr <= {{5{1'b0}}, data_in};`
245	86	creep	`control <= MEM_READ;`
246			`end`
247	96	creep	`else if (indirectx \|\| indirecty) begin`
248	95	creep	`pc <= next_pc;`
249			`address <= data_in;`
250			`temp_data <= data_in;`
251			`control <= MEM_READ;`
252			`end`
253	61	creep	`end`
254	87	creep	`FETCH_HIGH_CALC_INDEX: begin`
255			`pc <= next_pc;`
256			`temp_addr[12:8] <= data_in[4:0];`
257			`address <= {data_in[4:0], address_plus_index[7:0]};`
258			`control <= MEM_READ;`
259			`data_out <= 8'h00;`
260			`end`
261	94	creep	`FETCH_OP_EVAL_BRANCH: begin`
262			`if (branch) begin`
263			`pc <= {{5{1'b0}}, address_plus_index[7:0]};`
264			`address <= {{5{1'b0}}, address_plus_index[7:0]};`
265			`control <= MEM_READ;`
266			`data_out <= 8'h00;`
267			`end`
268			`else begin`
269			`pc <= next_pc;`
270			`address <= next_pc;`
271			`control <= MEM_READ;`
272			`data_out <= 8'h00;`
273	95	creep	`ir <= data_in;`
274	94	creep	`end`
275			`end`
276			`FETCH_OP_FIX_PC: begin`
277			`if (page_crossed) begin`
278			`pc[12:8] <= address_plus_index[12:8];`
279			`address[12:8] <= address_plus_index[12:8];`
280			`end`
281			`else begin`
282			`pc <= next_pc;`
283			`address <= next_pc;`
284			`control <= MEM_READ;`
285			`ir <= data_in;`
286			`end`
287			`end`
288	71	creep	`FETCH_HIGH: begin`
289			`if (jump) begin`
290	83	creep	`pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte`
291			`address <= {data_in[4:0], temp_addr[7:0]};`
292			`control <= MEM_READ;`
293			`data_out <= 8'h00;`
294	71	creep	`end`
295			`else begin`
296			`if (write) begin`
297			`pc <= next_pc;`
298			`temp_addr[12:8] <= data_in[4:0];`
299			`address <= {data_in[4:0],temp_addr[7:0]};`
300			`control <= MEM_WRITE;`
301	77	creep	`data_out <= alu_result;`
302	71	creep	`end`
303			`else begin // read_modify_write or just read`
304			`pc <= next_pc;`
305			`temp_addr[12:8] <= data_in[4:0];`
306			`address <= {data_in[4:0],temp_addr[7:0]};`
307	83	creep	`control <= MEM_READ;`
308			`data_out <= 8'h00;`
309	71	creep	`end`
310			`end`
311			`//else begin`
312			`// $write("FETCHHIGH PROBLEM");`
313			`// $finish(0);`
314			`//end`
315	61	creep	`end`
316	71	creep	`READ_MEM: begin`
317			`if (read_modify_write) begin`
318			`pc <= pc;`
319			`address <= temp_addr;`
320			`control <= MEM_WRITE;`
321			`temp_data <= data_in;`
322			`data_out <= data_in; // writeback the same value`
323			`end`
324			`else begin`
325			`pc <= pc;`
326			`address <= pc;`
327			`temp_data <= data_in;`
328	83	creep	`control <= MEM_READ;`
329			`data_out <= 8'h00;`
330	71	creep	`end`
331	70	creep	`end`
332	86	creep	`READ_MEM_CALC_INDEX: begin`
333			`//pc <= next_pc; // pc was already updated in the previous cycle`
334			`address <= address_plus_index;`
335			`temp_addr <= address_plus_index;`
336
337			`if (write) begin`
338			`control <= MEM_WRITE;`
339			`data_out <= alu_result;`
340			`end`
341			`else begin`
342			`control <= MEM_READ;`
343			`data_out <= 8'h00;`
344			`end`
345
346			`end`
347	87	creep	`READ_MEM_FIX_ADDR: begin`
348			`if (read) begin`
349			`control <= MEM_READ;`
350			`data_out <= 8'h00;`
351
352			`if (page_crossed) begin`
353			`address <= address_plus_index;`
354			`temp_addr <= address_plus_index;`
355			`end`
356			`else begin`
357			`address <= pc;`
358			`temp_data <= data_in;`
359			`end`
360			`end`
361			`else if (write) begin`
362			`control <= MEM_WRITE;`
363			`data_out <= alu_result;`
364			`address <= address_plus_index;`
365			`temp_addr <= address_plus_index;`
366
367			`end`
368			`else begin // read modify write`
369			`control <= MEM_READ;`
370			`data_out <= 8'h00;`
371			`address <= address_plus_index;`
372			`temp_addr <= address_plus_index;`
373			`end`
374			`end`
375	71	creep	`DUMMY_WRT_CALC: begin`
376			`pc <= pc;`
377			`address <= temp_addr;`
378			`control <= MEM_WRITE;`
379			`data_out <= alu_result;`
380	70	creep	`end`
381	71	creep	`WRITE_MEM: begin`
382			`pc <= pc;`
383			`address <= pc;`
384	83	creep	`control <= MEM_READ;`
385			`data_out <= 8'h00;`
386	70	creep	`end`
387	95	creep	`READ_FROM_POINTER: begin`
388	101	creep	`if (jump_indirect) begin`
389			`pc[7:0] <= data_in;`
390			`control <= MEM_READ;`
391	96	creep	`address <= address_plus_index;`
392			`end`
393	101	creep	`else begin`
394			`pc <= pc;`
395			`control <= MEM_READ;`
396
397			`if (indirectx) begin`
398			`address <= address_plus_index;`
399			`end`
400			`else begin // indirecty falls here`
401			`address <= address_plus_index;`
402			`temp_addr <= {{5{1'b0}}, data_in};`
403			`end`
404	96	creep	`end`
405	95	creep	`end`
406			`READ_FROM_POINTER_X: begin`
407			`pc <= pc;`
408			`address <= address_plus_index;`
409			`temp_addr[7:0] <= data_in;`
410			`control <= MEM_READ;`
411			`end`
412			`READ_FROM_POINTER_X1: begin`
413	101	creep	`if (jump_indirect) begin`
414			`pc[12:8] <= data_in[4:0];`
415			`control <= MEM_READ;`
416			`address <= {data_in[4:0], pc[7:0]};`
417			`end`
418			`else if (indirectx) begin`
419			`address <= {data_in[4:0], temp_addr[7:0]};`
420	96	creep	`if (write) begin`
421			`control <= MEM_WRITE;`
422			`data_out <= alu_result;`
423			`end`
424			`else begin`
425			`control <= MEM_READ;`
426			`end`
427	95	creep	`end`
428	96	creep	`else begin // indirecty falls here`
429			`address <= address_plus_index;`
430			`temp_addr[12:8] <= data_in;`
431	95	creep	`control <= MEM_READ;`
432			`end`
433			`end`
434	70	creep	`default: begin`
435	95	creep	$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
436	70	creep	`$finish(0);`
437			`end`
438
439			`endcase`
440			`end`
441			`end`
442
443	71	creep	`always @ (*) begin // this is the next_state logic and the output logic always block`
444			`alu_opcode = 8'h00;`
445			`alu_a = 8'h00;`
446			`alu_enable = 1'b0;`
447	70	creep
448	71	creep	`next_state = RESET; // this prevents the latch`
449	68	creep
450	71	creep	`case (state)`
451			`RESET: begin`
452			`next_state = FETCH_OP;`
453			`end`
454			`FETCH_OP: begin`
455			`next_state = FETCH_LOW;`
456			`end`
457	82	creep	`//FETCH_OP_CALC: begin // so far no addressing mode required the use of this state`
458			`// next_state = FETCH_LOW;`
459			`// alu_opcode = ir;`
460			`// alu_enable = 1'b1;`
461			`//end`
462	71	creep	`FETCH_OP_CALC_PARAM: begin`
463			`next_state = FETCH_LOW;`
464			`alu_opcode = ir;`
465			`alu_enable = 1'b1;`
466			`alu_a = temp_data;`
467			`end`
468			`FETCH_LOW: begin`
469			`if (accumulator \|\| implied) begin`
470			`alu_opcode = ir;`
471			`alu_enable = 1'b1;`
472			`next_state = FETCH_OP;`
473			`end`
474			`else if (immediate) begin`
475			`next_state = FETCH_OP_CALC_PARAM;`
476			`end`
477	77	creep	`else if (zero_page) begin`
478			`if (read \|\| read_modify_write) begin`
479			`next_state = READ_MEM;`
480			`end`
481			`else if (write) begin`
482			`next_state = WRITE_MEM;`
483	86	creep	`alu_opcode = ir;`
484			`alu_enable = 1'b1;`
485			`alu_a = 8'h00;`
486	77	creep	`end`
487			`else begin`
488			`$write("unknown behavior");`
489			`$finish(0);`
490			`end`
491			`end`
492	86	creep	`else if (zero_page_indexed) begin`
493			`next_state = READ_MEM_CALC_INDEX;`
494			`end`
495	101	creep	`else if (absolute \|\| jump_indirect) begin // at least the absolute address mode falls here`
496	71	creep	`next_state = FETCH_HIGH;`
497	87	creep	`if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly`
498	86	creep	`alu_opcode = ir;`
499			`alu_enable = 1'b1;`
500			`alu_a = 8'h00;`

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Blame information for rev 101