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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix relative mode, bit 7 means negative                          ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
        parameter DATA_SIZE = 8;
        parameter ADDR_SIZE = 13;
 
        localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        input reset_n;
        input [DATA_SIZE_:0] alu_result;
        input [DATA_SIZE_:0] alu_status;
        input [DATA_SIZE_:0] data_in;
        output reg [ADDR_SIZE_:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;
        output reg [DATA_SIZE_:0] alu_opcode;
        output reg [DATA_SIZE_:0] alu_a;
        output reg alu_enable;
 
        input [DATA_SIZE_:0] alu_x;
        input [DATA_SIZE_:0] alu_y;
 
        // FSM states
        localparam FETCH_OP = 5'b00000;
        localparam FETCH_OP_CALC = 5'b00001;
        localparam FETCH_LOW = 5'b00010;
        localparam FETCH_HIGH = 5'b00011;
        localparam READ_MEM = 5'b00100;
        localparam DUMMY_WRT_CALC = 5'b00101;
        localparam WRITE_MEM = 5'b00110;
        localparam FETCH_OP_CALC_PARAM = 5'b00111;
        localparam READ_MEM_CALC_INDEX = 5'b01000;
        localparam FETCH_HIGH_CALC_INDEX = 5'b01001;
        localparam READ_MEM_FIX_ADDR = 5'b01010;
        localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
        localparam FETCH_OP_FIX_PC = 5'b01100;
        localparam READ_FROM_POINTER = 5'b01101;
        localparam READ_FROM_POINTER_X = 5'b01110;
        localparam READ_FROM_POINTER_X1 = 5'b01111;
        localparam PUSH_PCH = 5'b10000;
        localparam PUSH_PCL = 5'b10001;
        localparam PUSH_STATUS = 5'b10010;
        localparam FETCH_PCL = 5'b10011;
        localparam FETCH_PCH = 5'b10100;
        localparam INCREMENT_SP = 5'b10101;
        localparam PULL_STATUS = 5'b10110;
        localparam PULL_PCL = 5'b10111;
        localparam PULL_PCH = 5'b11000;
        localparam INCREMENT_PC = 5'b11001;
 
        localparam RESET = 5'b11111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE_:0] pc;           // program counter
        reg [DATA_SIZE:0] sp;            // stack pointer. 9 bits wide.
        reg [DATA_SIZE_:0] ir;           // instruction register
        reg [ADDR_SIZE_:0] temp_addr;    // temporary address
        reg [DATA_SIZE_:0] temp_data;    // temporary data
 
        reg [4:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 5 bits wide. as of march 24th this was 5bit wide.
 
        // wiring that simplifies the FSM logic by simplifying the addressing modes
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirectx;
        reg indirecty;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
        reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
        reg jump_indirect;
 
        // regs for the special instructions
        reg break;
        reg rti;
        reg rts;
 
        wire [ADDR_SIZE_:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
        reg page_crossed;                       // so the simple assign was changed into a combinational always block
 
        reg branch;
 
        always @(*) begin
                address_plus_index = 0;
                page_crossed = 0;
 
                if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
                        {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                        address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
                end
                else if (branch) begin
                        if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
                                {page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
                                address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure
                        end                                                             // solution: add a temp reg i guess
                end
                else if (state == READ_FROM_POINTER) begin
                        if (indirectx) begin
                                {page_crossed, address_plus_index[7:0]} = temp_data + index;
                                address_plus_index[12:8] = 5'b00000;
                        end
                        else if (jump_indirect) begin
                                address_plus_index[7:0] = temp_addr + 8'h01;
                                address_plus_index[12:8] = 5'b00000;
                        end
                        else begin // indirecty falls here
                                address_plus_index[7:0] = temp_data + 8'h01;
                                address_plus_index[12:8] = 5'b00000;
                        end
                end
                else if (state == READ_FROM_POINTER_X) begin
                        {page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
                        address_plus_index[12:8] = 5'b00000;
                end
                else if (state == READ_FROM_POINTER_X1) begin
                        {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                        address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
                end
        end
 
        wire [8:0] sp_plus_one;
        assign sp_plus_one = sp + 9'b000000001;
 
        wire [8:0] sp_minus_one;
        assign sp_minus_one = sp - 9'b000000001;
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 9'b100000000; // the default is 'h100 
                        ir <= 8'h00;
                        temp_addr <= 13'h00;
                        temp_data <= 8'h00;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 0;
                        control <= MEM_READ;
                        data_out <= 8'h00;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin    // The processor was reset
                                        $write("under reset");
                                end
                                /*
                                FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
                                FETCH_OP_CALC: enables the alu and fetchs the next instruction opcode. (pipelining)
                                FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
                                */
                                FETCH_OP, FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                /*
                                in this state the opcode is already known so truly execution begins.
                                all instruction execute this cycle.
                                */
                                FETCH_LOW: begin
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                control <= MEM_READ;
                                        end
                                        else if (immediate || relative) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute || absolute_indexed || jump_indirect) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_addr <= {{5{1'b0}},data_in};
                                                temp_data <= 8'h00;
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        else if (zero_page_indexed) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}}, data_in};
                                                temp_addr <= {{5{1'b0}}, data_in};
                                                control <= MEM_READ;
                                        end
                                        else if (indirectx || indirecty) begin
                                                pc <= next_pc;
                                                address <= data_in;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                        end
                                        else begin // the special instructions will fall here: BRK, RTI, RTS...
                                                if (break) begin
                                                        pc <= next_pc;
                                                        address <= sp;
                                                        data_out <= {{3{1'b0}}, pc[12:8]};
                                                        control <= MEM_WRITE;
                                                        sp <= sp_minus_one;
                                                end
                                                else if (rti || rts) begin
                                                        address <= sp;
                                                        control <= MEM_READ;
                                                end
                                        end
                                end
                                FETCH_HIGH_CALC_INDEX: begin
                                        pc <= next_pc;
                                        temp_addr[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], address_plus_index[7:0]};
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                // this cycle fetchs the next operand while still evaluating if a branch occurred.
                                FETCH_OP_EVAL_BRANCH: begin
                                        if (branch) begin
                                                pc <= {{5{1'b0}}, address_plus_index[7:0]};
                                                address <= {{5{1'b0}}, address_plus_index[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                                ir <= data_in;
                                        end
                                end
                                // sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
                                FETCH_OP_FIX_PC: begin
                                        if (page_crossed) begin
                                                pc[12:8] <= address_plus_index[12:8];
                                                address[12:8] <= address_plus_index[12:8];
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                ir <= data_in;
                                        end
                                end
                                // several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        //else begin
                                        //      $write("FETCHHIGH PROBLEM"); 
                                        //      $finish(0); 
                                        //end
                                end
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                control <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                end
                                READ_MEM_CALC_INDEX: begin
                                                //pc <= next_pc; // pc was  already updated in the previous cycle
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
 
                                end
                                READ_MEM_FIX_ADDR: begin
                                        if (read) begin
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
 
                                                if (page_crossed) begin
                                                        address <= address_plus_index;
                                                        temp_addr <= address_plus_index;
                                                end
                                                else begin
                                                        address <= pc;
                                                        temp_data <= data_in;
                                                end
                                        end
                                        else if (write) begin
                                                control <= MEM_WRITE;
                                                data_out <= alu_result;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                        end
                                        else begin // read modify write
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
                                        end
                                end
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        control <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                READ_FROM_POINTER: begin
                                        if (jump_indirect) begin
                                                pc[7:0] <= data_in;
                                                control <= MEM_READ;
                                                address <= address_plus_index;
                                        end
                                        else begin
                                                pc <= pc;
                                                control <= MEM_READ;
 
                                                if (indirectx) begin
                                                        address <= address_plus_index;
                                                end
                                                else begin // indirecty falls here
                                                        address <= address_plus_index;
                                                        temp_addr <= {{5{1'b0}}, data_in};
                                                end
                                        end
                                end
                                READ_FROM_POINTER_X: begin
                                        pc <= pc;
                                        address <= address_plus_index;
                                        temp_addr[7:0] <= data_in;
                                        control <= MEM_READ;
                                end
                                READ_FROM_POINTER_X1: begin
                                        if (jump_indirect) begin
                                                pc[12:8] <= data_in[4:0];
                                                control <= MEM_READ;
                                                address <= {data_in[4:0], pc[7:0]};
                                        end
                                        else if (indirectx) begin
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                end
                                        end
                                        else begin // indirecty falls here
                                                address <= address_plus_index;
                                                temp_addr[12:8] <= data_in;
                                                control <= MEM_READ;
                                        end
                                end
                                PUSH_PCH: begin
                                        pc <= pc;
                                        address <= sp;
                                        data_out <= pc[7:0];
                                        control <= MEM_WRITE;
                                        sp <= sp_minus_one;
                                end
                                PUSH_PCL: begin
                                        pc <= pc;
                                        address <= sp;
                                        data_out <= alu_status;
                                        control <= MEM_WRITE;
                                        sp <= sp_minus_one;
                                end
                                PUSH_STATUS: begin
                                        address <= 13'hFFFE;
                                        control <= MEM_READ;
                                end
                                FETCH_PCL: begin
                                        pc[7:0] <= data_in;
                                        address <= 13'hFFFF;
                                        control <= MEM_READ;
                                end
                                FETCH_PCH: begin
                                        pc[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], pc[7:0]};
                                        control <= MEM_READ;
                                end
                                INCREMENT_SP: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                end
                                PULL_STATUS: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                        temp_data <= data_in;
                                end
                                PULL_PCL: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                        pc[7:0] <= data_in;
                                end
                                PULL_PCH: begin
                                        pc[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], pc[7:0]};
                                end
                                INCREMENT_PC: begin
                                        pc <= next_pc;
                                        address <= next_pc;
                                end
                                default: begin
                                        $write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the output logic always block
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
 
                next_state = RESET; // this prevents the latch
 
                case (state)
                        RESET: begin
                                next_state = FETCH_OP;
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        //FETCH_OP_CALC: begin // so far no addressing mode required the use of this state
                        //      next_state = FETCH_LOW;
                        //      alu_opcode = ir;
                        //      alu_enable = 1'b1;
                        //end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                        else begin
                                                $write("unknown behavior");
                                                $finish(0);
                                        end
                                end
                                else if (zero_page_indexed) begin
                                        next_state = READ_MEM_CALC_INDEX;
                                end
                                else if (absolute || jump_indirect) begin // at least the absolute address mode falls here
                                        next_state = FETCH_HIGH;
                                        if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                end
                                else if (absolute_indexed) begin
                                        next_state = FETCH_HIGH_CALC_INDEX;
                                end
                                else if (relative) begin
                                        next_state = FETCH_OP_EVAL_BRANCH;
                                end
                                else if (indirectx || indirecty) begin
                                        next_state = READ_FROM_POINTER;
                                end
                                else begin // all the special instructions will fall here
                                        if (break) begin
                                                next_state = PUSH_PCH;
                                        end
                                        else if (rti || rts) begin
                                                next_state = INCREMENT_SP;
                                        end
                                end
                        end
                        READ_FROM_POINTER: begin
                                if (indirectx) begin
                                        next_state = READ_FROM_POINTER_X;
                                end
                                else begin // indirecty and jump indirect falls here
                                        next_state = READ_FROM_POINTER_X1;
                                end
                        end
                        READ_FROM_POINTER_X: begin
                                next_state = READ_FROM_POINTER_X1;
                        end
                        READ_FROM_POINTER_X1: begin
                                if (jump_indirect) begin
                                        next_state = FETCH_OP;
                                end
                                else if (indirecty) begin
                                        next_state = READ_MEM_FIX_ADDR;
                                end
                                else begin
                                        if (read) begin // read_modify_write was showing up here for no reason. no instruction using pointers is from that type.
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                next_state = WRITE_MEM;
                                        end
                                end
                        end
                        FETCH_OP_EVAL_BRANCH: begin
                                if (branch) begin
                                        next_state = FETCH_OP_FIX_PC;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_OP_FIX_PC: begin
                                if (page_crossed) begin
                                        next_state = FETCH_OP;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_HIGH_CALC_INDEX: begin
                                next_state = READ_MEM_FIX_ADDR;
                        end
                        READ_MEM_FIX_ADDR: begin
                                if (read) begin
                                        if (page_crossed) begin
                                                next_state = READ_MEM;
                                        end
                                        else begin
                                                next_state = FETCH_OP_CALC_PARAM;
                                        end
                                end
                                else if (read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                        alu_enable = 1'b1;
                                        alu_opcode = ir;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        FETCH_HIGH: begin
                                if (jump_indirect) begin
                                        next_state = READ_FROM_POINTER;
                                end
                                else if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM_CALC_INDEX: begin
                                if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        PUSH_PCH: begin
                                next_state = PUSH_PCL;
                        end
                        PUSH_PCL: begin
                                next_state = PUSH_STATUS;
                        end
                        PUSH_STATUS: begin
                                next_state = FETCH_PCL;
                        end
                        FETCH_PCL: begin
                                next_state = FETCH_PCH;
                        end
                        FETCH_PCH: begin
                                next_state = FETCH_OP;
                        end
                        INCREMENT_SP: begin
                                if (rti) begin
                                        next_state = PULL_STATUS;
                                end
                                else begin // rts
                                        next_state = PULL_PCL;
                                end
                        end
                        PULL_STATUS: begin
                                next_state = PULL_PCL;
                        end
                        PULL_PCL: begin
                                next_state = PULL_PCH;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        PULL_PCH: begin
                                if (rti) begin
                                        next_state = FETCH_OP;
                                end
                                else begin // rts
                                        next_state = INCREMENT_PC;
                                end
                        end
                        INCREMENT_PC: begin
                                next_state = FETCH_OP;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirectx = 1'b0;
                indirecty = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                index = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
                jump_indirect = 1'b0;
                branch = 1'b0;
 
                break = 1'b0;
                rti = 1'b0;
                rts = 1'b0;
 
                case (ir)
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                        PLP_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                                index = alu_x;
                        end
                        LDX_ZPY, STX_ZPY: begin
                                zero_page_indexed = 1'b1;
                                index = alu_y;
                        end
                        BCC_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BCS_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BEQ_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[Z]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BNE_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[Z] == 1'b0) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BPL_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BMI_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVC_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (!alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVS_REL: begin
                                relative = 1'b1;
                                index = temp_data;
 
                                if (alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JSR_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX: begin
                                absolute_indexed = 1'b1;
                                index = alu_x;
                        end
                        ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                                index = alu_y;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX: begin
                                indirectx = 1'b1;
                                index = alu_x;
                        end
                        ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, ORA_IDY, SBC_IDY, STA_IDY: begin
                                indirecty = 1'b1;
                                index = alu_y;
                        end
                        JMP_ABS: begin
                                absolute = 1'b1;
                                jump = 1'b1;
                        end
                        JMP_IND: begin
                                jump_indirect = 1'b1;
                        end
                        BRK_IMP: begin
                                break = 1'b1;
                        end
                        RTI_IMP: begin
                                rti = 1'b1;
                        end
                        RTS_IMP: begin
                                rts = 1'b1;
                        end
                        default: begin
                                $write("state : %b", state);
                                if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
                                        $write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                        $finish();
                                end
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
        end
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12	96	creep	`//// - Fix relative mode, bit 7 means negative ////`
13	61	creep	`//// - Code the indirect indexed mode ////`
14			`//// - Code the absolute indirect mode ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
18			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
19			`//// ////`
20			`////////////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`////////////////////////////////////////////////////////////////////////////`
46
47			`timescale 1ns / 1ps
48
49	86	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`
50	87	creep	`parameter DATA_SIZE = 8;`
51			`parameter ADDR_SIZE = 13;`
52	68	creep
53	83	creep	`localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;`
54			`localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
55	82	creep
56	71	creep	`input clk;`
57			`input reset_n;`
58	82	creep	`input [DATA_SIZE_:0] alu_result;`
59			`input [DATA_SIZE_:0] alu_status;`
60			`input [DATA_SIZE_:0] data_in;`
61			`output reg [ADDR_SIZE_:0] address;`
62	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
63	82	creep	`output reg [DATA_SIZE_:0] data_out;`
64			`output reg [DATA_SIZE_:0] alu_opcode;`
65			`output reg [DATA_SIZE_:0] alu_a;`
66	68	creep	`output reg alu_enable;`
67	61	creep
68	86	creep	`input [DATA_SIZE_:0] alu_x;`
69			`input [DATA_SIZE_:0] alu_y;`
70	68	creep
71	61	creep	`// FSM states`
72	95	creep	`localparam FETCH_OP = 5'b00000;`
73			`localparam FETCH_OP_CALC = 5'b00001;`
74			`localparam FETCH_LOW = 5'b00010;`
75			`localparam FETCH_HIGH = 5'b00011;`
76			`localparam READ_MEM = 5'b00100;`
77			`localparam DUMMY_WRT_CALC = 5'b00101;`
78			`localparam WRITE_MEM = 5'b00110;`
79			`localparam FETCH_OP_CALC_PARAM = 5'b00111;`
80			`localparam READ_MEM_CALC_INDEX = 5'b01000;`
81			`localparam FETCH_HIGH_CALC_INDEX = 5'b01001;`
82			`localparam READ_MEM_FIX_ADDR = 5'b01010;`
83			`localparam FETCH_OP_EVAL_BRANCH = 5'b01011;`
84			`localparam FETCH_OP_FIX_PC = 5'b01100;`
85			`localparam READ_FROM_POINTER = 5'b01101;`
86			`localparam READ_FROM_POINTER_X = 5'b01110;`
87			`localparam READ_FROM_POINTER_X1 = 5'b01111;`
88	104	creep	`localparam PUSH_PCH = 5'b10000;`
89			`localparam PUSH_PCL = 5'b10001;`
90			`localparam PUSH_STATUS = 5'b10010;`
91			`localparam FETCH_PCL = 5'b10011;`
92			`localparam FETCH_PCH = 5'b10100;`
93	105	creep	`localparam INCREMENT_SP = 5'b10101;`
94			`localparam PULL_STATUS = 5'b10110;`
95			`localparam PULL_PCL = 5'b10111;`
96			`localparam PULL_PCH = 5'b11000;`
97	107	creep	`localparam INCREMENT_PC = 5'b11001;`
98	61	creep
99	95	creep	`localparam RESET = 5'b11111;`
100
101	61	creep	`// OPCODES TODO: verify how this get synthesised`
102			`include "../T6507LP_Package.v"
103
104			`// control signals`
105			`localparam MEM_READ = 1'b0;`
106			`localparam MEM_WRITE = 1'b1;`
107
108	82	creep	`reg [ADDR_SIZE_:0] pc; // program counter`
109	104	creep	`reg [DATA_SIZE:0] sp; // stack pointer. 9 bits wide.`
110	82	creep	`reg [DATA_SIZE_:0] ir; // instruction register`
111			`reg [ADDR_SIZE_:0] temp_addr; // temporary address`
112			`reg [DATA_SIZE_:0] temp_data; // temporary data`
113	61	creep
114	96	creep	`reg [4:0] state, next_state; // current and next state registers`
115	104	creep	`// TODO: not sure if this will be 5 bits wide. as of march 24th this was 5bit wide.`
116	61	creep
117	104	creep	`// wiring that simplifies the FSM logic by simplifying the addressing modes`
118	61	creep	`reg absolute;`
119			`reg absolute_indexed;`
120			`reg accumulator;`
121			`reg immediate;`
122			`reg implied;`
123	95	creep	`reg indirectx;`
124			`reg indirecty;`
125	61	creep	`reg relative;`
126			`reg zero_page;`
127			`reg zero_page_indexed;`
128	86	creep	`reg [DATA_SIZE_:0] index; // will be assigned with either X or Y`
129	61	creep
130			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
131			`reg read;`
132			`reg read_modify_write;`
133			`reg write;`
134			`reg jump;`
135	101	creep	`reg jump_indirect;`
136	61	creep
137	104	creep	`// regs for the special instructions`
138			`reg break;`
139	105	creep	`reg rti;`
140	107	creep	`reg rts;`
141	104	creep
142	82	creep	`wire [ADDR_SIZE_:0] next_pc;`
143	63	creep	`assign next_pc = pc + 13'b0000000000001;`
144	61	creep
145	87	creep	`reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.`
146			`reg page_crossed; // so the simple assign was changed into a combinational always block`
147
148	94	creep	`reg branch;`
149
150	87	creep	`always @(*) begin`
151			`address_plus_index = 0;`
152			`page_crossed = 0;`
153	86	creep
154	88	creep	`if (state == READ_MEM_CALC_INDEX \|\| state == READ_MEM_FIX_ADDR \|\| state == FETCH_HIGH_CALC_INDEX) begin`
155			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
156			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
157	87	creep	`end`
158	94	creep	`else if (branch) begin`
159			`if (state == FETCH_OP_FIX_PC \|\| state == FETCH_OP_EVAL_BRANCH) begin`
160			`{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;`
161			`address_plus_index[12:8] = pc[12:8] + page_crossed;// warning: pc might feed these lines twice and cause branch failure`
162			`end // solution: add a temp reg i guess`
163			`end`
164	95	creep	`else if (state == READ_FROM_POINTER) begin`
165	96	creep	`if (indirectx) begin`
166			`{page_crossed, address_plus_index[7:0]} = temp_data + index;`
167			`address_plus_index[12:8] = 5'b00000;`
168			`end`
169	101	creep	`else if (jump_indirect) begin`
170			`address_plus_index[7:0] = temp_addr + 8'h01;`
171			`address_plus_index[12:8] = 5'b00000;`
172			`end`
173	96	creep	`else begin // indirecty falls here`
174			`address_plus_index[7:0] = temp_data + 8'h01;`
175			`address_plus_index[12:8] = 5'b00000;`
176			`end`
177	95	creep	`end`
178			`else if (state == READ_FROM_POINTER_X) begin`
179			`{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;`
180			`address_plus_index[12:8] = 5'b00000;`
181			`end`
182	96	creep	`else if (state == READ_FROM_POINTER_X1) begin`
183			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
184			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
185			`end`
186	87	creep	`end`
187
188	103	creep	`wire [8:0] sp_plus_one;`
189			`assign sp_plus_one = sp + 9'b000000001;`
190
191			`wire [8:0] sp_minus_one;`
192			`assign sp_minus_one = sp - 9'b000000001;`
193
194	71	creep	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
195			`if (reset_n == 1'b0) begin`
196			`// all registers must assume default values`
197	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
198	103	creep	`sp <= 9'b100000000; // the default is 'h100`
199	82	creep	`ir <= 8'h00;`
200	102	creep	`temp_addr <= 13'h00;`
201	82	creep	`temp_data <= 8'h00;`
202	68	creep	`state <= RESET;`
203	71	creep	`// registered outputs also receive default values`
204			`address <= 0;`
205	82	creep	`control <= MEM_READ;`
206			`data_out <= 8'h00;`
207	61	creep	`end`
208			`else begin`
209			`state <= next_state;`
210	83	creep
211	61	creep	`case (state)`
212	104	creep	`RESET: begin // The processor was reset`
213	82	creep	`$write("under reset");`
214	68	creep	`end`
215	104	creep	`/*`
216			`FETCH_OP: executed when the processor was reset or the last instruction could not fetch.`
217			`FETCH_OP_CALC: enables the alu and fetchs the next instruction opcode. (pipelining)`
218			`FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)`
219			`*/`
220			`FETCH_OP, FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
221	61	creep	`pc <= next_pc;`
222	71	creep	`address <= next_pc;`
223	83	creep	`control <= MEM_READ;`
224	70	creep	`ir <= data_in;`
225	61	creep	`end`
226	104	creep	`/*`
227			`in this state the opcode is already known so truly execution begins.`
228			`all instruction execute this cycle.`
229			`*/`
230			`FETCH_LOW: begin`
231	68	creep	`if (accumulator \|\| implied) begin`
232	70	creep	`pc <= pc; // is this better?`
233	71	creep	`address <= pc;`
234	83	creep	`control <= MEM_READ;`
235	61	creep	`end`
236	94	creep	`else if (immediate \|\| relative) begin`
237	68	creep	`pc <= next_pc;`
238	71	creep	`address <= next_pc;`
239	83	creep	`control <= MEM_READ;`
240	70	creep	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
241	61	creep	`end`
242	101	creep	`else if (absolute \|\| absolute_indexed \|\| jump_indirect) begin`
243	71	creep	`pc <= next_pc;`
244			`address <= next_pc;`
245	83	creep	`control <= MEM_READ;`
246	87	creep	`temp_addr <= {{5{1'b0}},data_in};`
247	101	creep	`temp_data <= 8'h00;`
248	71	creep	`end`
249	77	creep	`else if (zero_page) begin`
250			`pc <= next_pc;`
251			`address <= {{5{1'b0}},data_in};`
252	78	creep	`temp_addr <= {{5{1'b0}},data_in};`
253
254	77	creep	`if (write) begin`
255			`control <= MEM_WRITE;`
256	78	creep	`data_out <= alu_result;`
257	77	creep	`end`
258	83	creep	`else begin`
259			`control <= MEM_READ;`
260			`data_out <= 8'h00;`
261			`end`
262	77	creep	`end`
263	86	creep	`else if (zero_page_indexed) begin`
264			`pc <= next_pc;`
265	94	creep	`address <= {{5{1'b0}}, data_in};`
266			`temp_addr <= {{5{1'b0}}, data_in};`
267	86	creep	`control <= MEM_READ;`
268			`end`
269	96	creep	`else if (indirectx \|\| indirecty) begin`
270	95	creep	`pc <= next_pc;`
271			`address <= data_in;`
272			`temp_data <= data_in;`
273			`control <= MEM_READ;`
274			`end`
275	102	creep	`else begin // the special instructions will fall here: BRK, RTI, RTS...`
276	104	creep	`if (break) begin`
277			`pc <= next_pc;`
278			`address <= sp;`
279			`data_out <= {{3{1'b0}}, pc[12:8]};`
280			`control <= MEM_WRITE;`
281			`sp <= sp_minus_one;`
282			`end`
283	107	creep	`else if (rti \|\| rts) begin`
284	105	creep	`address <= sp;`
285			`control <= MEM_READ;`
286			`end`
287	102	creep	`end`
288	61	creep	`end`
289	87	creep	`FETCH_HIGH_CALC_INDEX: begin`
290			`pc <= next_pc;`
291			`temp_addr[12:8] <= data_in[4:0];`
292			`address <= {data_in[4:0], address_plus_index[7:0]};`
293			`control <= MEM_READ;`
294			`data_out <= 8'h00;`
295			`end`
296	104	creep	`// this cycle fetchs the next operand while still evaluating if a branch occurred.`
297	94	creep	`FETCH_OP_EVAL_BRANCH: begin`
298			`if (branch) begin`
299			`pc <= {{5{1'b0}}, address_plus_index[7:0]};`
300			`address <= {{5{1'b0}}, address_plus_index[7:0]};`
301			`control <= MEM_READ;`
302			`data_out <= 8'h00;`
303			`end`
304			`else begin`
305			`pc <= next_pc;`
306			`address <= next_pc;`
307			`control <= MEM_READ;`
308			`data_out <= 8'h00;`
309	95	creep	`ir <= data_in;`
310	94	creep	`end`
311			`end`
312	104	creep	`// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100`
313	94	creep	`FETCH_OP_FIX_PC: begin`
314			`if (page_crossed) begin`
315			`pc[12:8] <= address_plus_index[12:8];`
316			`address[12:8] <= address_plus_index[12:8];`
317			`end`
318			`else begin`
319			`pc <= next_pc;`
320			`address <= next_pc;`
321			`control <= MEM_READ;`
322			`ir <= data_in;`
323			`end`
324			`end`
325	104	creep	`// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.`
326	71	creep	`FETCH_HIGH: begin`
327			`if (jump) begin`
328	83	creep	`pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte`
329			`address <= {data_in[4:0], temp_addr[7:0]};`
330			`control <= MEM_READ;`
331			`data_out <= 8'h00;`
332	71	creep	`end`
333			`else begin`
334			`if (write) begin`
335			`pc <= next_pc;`
336			`temp_addr[12:8] <= data_in[4:0];`
337			`address <= {data_in[4:0],temp_addr[7:0]};`
338			`control <= MEM_WRITE;`
339	77	creep	`data_out <= alu_result;`
340	71	creep	`end`
341			`else begin // read_modify_write or just read`
342			`pc <= next_pc;`
343			`temp_addr[12:8] <= data_in[4:0];`
344			`address <= {data_in[4:0],temp_addr[7:0]};`
345	83	creep	`control <= MEM_READ;`
346			`data_out <= 8'h00;`
347	71	creep	`end`
348			`end`
349			`//else begin`
350			`// $write("FETCHHIGH PROBLEM");`
351			`// $finish(0);`
352			`//end`
353	61	creep	`end`
354	71	creep	`READ_MEM: begin`
355			`if (read_modify_write) begin`
356			`pc <= pc;`
357			`address <= temp_addr;`
358			`control <= MEM_WRITE;`
359			`temp_data <= data_in;`
360			`data_out <= data_in; // writeback the same value`
361			`end`
362			`else begin`
363			`pc <= pc;`
364			`address <= pc;`
365			`temp_data <= data_in;`
366	83	creep	`control <= MEM_READ;`
367			`data_out <= 8'h00;`
368	71	creep	`end`
369	70	creep	`end`
370	86	creep	`READ_MEM_CALC_INDEX: begin`
371			`//pc <= next_pc; // pc was already updated in the previous cycle`
372			`address <= address_plus_index;`
373			`temp_addr <= address_plus_index;`
374
375			`if (write) begin`
376			`control <= MEM_WRITE;`
377			`data_out <= alu_result;`
378			`end`
379			`else begin`
380			`control <= MEM_READ;`
381			`data_out <= 8'h00;`
382			`end`
383
384			`end`
385	87	creep	`READ_MEM_FIX_ADDR: begin`
386			`if (read) begin`
387			`control <= MEM_READ;`
388			`data_out <= 8'h00;`
389
390			`if (page_crossed) begin`
391			`address <= address_plus_index;`
392			`temp_addr <= address_plus_index;`
393			`end`
394			`else begin`
395			`address <= pc;`
396			`temp_data <= data_in;`
397			`end`
398			`end`
399			`else if (write) begin`
400			`control <= MEM_WRITE;`
401			`data_out <= alu_result;`
402			`address <= address_plus_index;`
403			`temp_addr <= address_plus_index;`
404
405			`end`
406			`else begin // read modify write`
407			`control <= MEM_READ;`
408			`data_out <= 8'h00;`
409			`address <= address_plus_index;`
410			`temp_addr <= address_plus_index;`
411			`end`
412			`end`
413	71	creep	`DUMMY_WRT_CALC: begin`
414			`pc <= pc;`
415			`address <= temp_addr;`
416			`control <= MEM_WRITE;`
417			`data_out <= alu_result;`
418	70	creep	`end`
419	71	creep	`WRITE_MEM: begin`
420			`pc <= pc;`
421			`address <= pc;`
422	83	creep	`control <= MEM_READ;`
423			`data_out <= 8'h00;`
424	70	creep	`end`
425	95	creep	`READ_FROM_POINTER: begin`
426	101	creep	`if (jump_indirect) begin`
427			`pc[7:0] <= data_in;`
428			`control <= MEM_READ;`
429	96	creep	`address <= address_plus_index;`
430			`end`
431	101	creep	`else begin`
432			`pc <= pc;`
433			`control <= MEM_READ;`
434
435			`if (indirectx) begin`
436			`address <= address_plus_index;`
437			`end`
438			`else begin // indirecty falls here`
439			`address <= address_plus_index;`
440			`temp_addr <= {{5{1'b0}}, data_in};`
441			`end`
442	96	creep	`end`
443	95	creep	`end`
444			`READ_FROM_POINTER_X: begin`
445			`pc <= pc;`
446			`address <= address_plus_index;`
447			`temp_addr[7:0] <= data_in;`
448			`control <= MEM_READ;`
449			`end`
450			`READ_FROM_POINTER_X1: begin`
451	101	creep	`if (jump_indirect) begin`
452			`pc[12:8] <= data_in[4:0];`
453			`control <= MEM_READ;`
454			`address <= {data_in[4:0], pc[7:0]};`
455			`end`
456			`else if (indirectx) begin`
457			`address <= {data_in[4:0], temp_addr[7:0]};`
458	96	creep	`if (write) begin`
459			`control <= MEM_WRITE;`
460			`data_out <= alu_result;`
461			`end`
462			`else begin`
463			`control <= MEM_READ;`
464			`end`
465	95	creep	`end`
466	96	creep	`else begin // indirecty falls here`
467			`address <= address_plus_index;`
468			`temp_addr[12:8] <= data_in;`
469	95	creep	`control <= MEM_READ;`
470			`end`
471			`end`
472	104	creep	`PUSH_PCH: begin`
473			`pc <= pc;`
474			`address <= sp;`
475			`data_out <= pc[7:0];`
476			`control <= MEM_WRITE;`
477			`sp <= sp_minus_one;`
478			`end`
479			`PUSH_PCL: begin`
480			`pc <= pc;`
481			`address <= sp;`
482			`data_out <= alu_status;`
483			`control <= MEM_WRITE;`
484			`sp <= sp_minus_one;`
485			`end`
486			`PUSH_STATUS: begin`
487			`address <= 13'hFFFE;`
488			`control <= MEM_READ;`
489			`end`
490			`FETCH_PCL: begin`
491			`pc[7:0] <= data_in;`
492			`address <= 13'hFFFF;`
493			`control <= MEM_READ;`
494			`end`
495			`FETCH_PCH: begin`
496			`pc[12:8] <= data_in[4:0];`
497			`address <= {data_in[4:0], pc[7:0]};`
498			`control <= MEM_READ;`
499			`end`
500	105	creep	`INCREMENT_SP: begin`

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