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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix relative mode, bit 7 means negative                          ////
//// - Check reset behavior                                             ////
//// - Comment the code                                                 ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, alu_x, alu_y, address, rw_mem, data_out, alu_opcode, alu_a, alu_enable);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd13;
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;                              // master clock
        input reset_n;                          // active low reset
        input [DATA_SIZE_:0] alu_result; // result from alu operation
        input [DATA_SIZE_:0] alu_status; // alu status register
        input [DATA_SIZE_:0] data_in;            // data that comes from the bus controller
        input [DATA_SIZE_:0] alu_x;              // alu x index register
        input [DATA_SIZE_:0] alu_y;              // alu y index register
        output reg [ADDR_SIZE_:0] address;       // system bus address
        output reg rw_mem;                      // read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;      // data that will be written somewhere else
        output reg [DATA_SIZE_:0] alu_opcode;    // current opcode
        output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu
        output reg alu_enable;                  // a flag that when high tells the alu when to perform the operations
 
 
        // FSM states. If aiming for less power consumption try gray coding.
        //localparam FETCH_OP_CALC = 5'b00001; this was never used
        localparam FETCH_OP = 5'b00000;
        localparam FETCH_LOW = 5'b00010;
        localparam FETCH_HIGH = 5'b00011;
        localparam READ_MEM = 5'b00100;
        localparam DUMMY_WRT_CALC = 5'b00101;
        localparam WRITE_MEM = 5'b00110;
        localparam FETCH_OP_CALC_PARAM = 5'b00111;
        localparam READ_MEM_CALC_INDEX = 5'b01000;
        localparam FETCH_HIGH_CALC_INDEX = 5'b01001;
        localparam READ_MEM_FIX_ADDR = 5'b01010;
        localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
        localparam FETCH_OP_FIX_PC = 5'b01100;
        localparam READ_FROM_POINTER = 5'b01101;
        localparam READ_FROM_POINTER_X = 5'b01110;
        localparam READ_FROM_POINTER_X1 = 5'b01111;
        localparam PUSH_PCH = 5'b10000;
        localparam PUSH_PCL = 5'b10001;
        localparam PUSH_STATUS = 5'b10010;
        localparam FETCH_PCL = 5'b10011;
        localparam FETCH_PCH = 5'b10100;
        localparam INCREMENT_SP = 5'b10101;
        localparam PULL_STATUS = 5'b10110;
        localparam PULL_PCL = 5'b10111;
        localparam PULL_PCH = 5'b11000;
        localparam INCREMENT_PC = 5'b11001;
        localparam PUSH_REGISTER = 5'b11010;
        localparam PULL_REGISTER = 5'b11011;
        localparam DUMMY = 5'b11100;
        localparam RESET = 5'b11111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "t6507lp_package.v"
 
        // rw_mem signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE_:0] pc;           // program counter
        reg [DATA_SIZE:0] sp;            // stack pointer. 9 bits wide.
        reg [DATA_SIZE_:0] ir;           // instruction register
        reg [ADDR_SIZE_:0] temp_addr;    // temporary address
        reg [DATA_SIZE_:0] temp_data;    // temporary data
 
        reg [4:0] state, next_state; // current and next state registers
 
        // wiring that simplifies the FSM logic by simplifying the addressing modes
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirectx;
        reg indirecty;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
        reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
        reg jump_indirect;
        reg index_is_x;
        reg index_is_branch;
 
        // regs for the special instructions
        reg brk;
        reg rti;
        reg rts;
        reg pha;
        reg php;
        reg pla;
        reg plp;
        reg jsr;
        reg tsx;
        reg txs;
        reg nop;
 
        reg invalid;
 
        wire [ADDR_SIZE_:0] next_pc;      // a simple logic to add one to the PC
        assign next_pc = pc + 13'b0000000000001;
 
        wire [DATA_SIZE:0] sp_plus_one;          // simple adder and subtracter for the stack pointer
        assign sp_plus_one = {1'b1, sp[7:0] + 8'b000000001};
 
        wire [DATA_SIZE:0] sp_minus_one;
        assign sp_minus_one = {1'b1, sp[7:0] - 8'b000000001};
 
        reg [ADDR_SIZE_:0] address_plus_index;   // this two registers are used when the instruction uses indexing.
        reg page_crossed;                       // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.
 
        reg branch;     // a simple reg that is asserted everytime a branch will be executed.                   
 
        // this is the combinational logic related to indexed instructions
        always @(*) begin
                address_plus_index = 13'h000;
                page_crossed = 1'b0;
 
                case (state)
                        READ_MEM_FIX_ADDR, FETCH_HIGH_CALC_INDEX: begin
                                {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                                address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
                        end
                        READ_FROM_POINTER_X1: begin
                                {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                                address_plus_index[12:8] = data_in[4:0];
                        end
                        FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin
                                if (branch) begin
                                        {page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
                                        address_plus_index[12:8] = pc[12:8] + page_crossed;
                                        // warning: pc might feed these lines twice and cause branch failure
                                end     // solution: add a temp reg i guess
                        end
 
                        READ_FROM_POINTER: begin
                                if (indirectx) begin
                                        {page_crossed, address_plus_index[7:0]} = temp_data + index;
                                        //address_plus_index[12:8] = 5'b00000; // already assigned earlier at this block
                                end
                                else if (jump_indirect) begin
                                        address_plus_index[7:0] = temp_addr[7:0] + 8'h01;
                                        //address_plus_index[12:8] = 5'b00000;
                                end
                                else begin // indirecty falls here
                                        address_plus_index[7:0] = temp_data + 8'h01;
                                        //address_plus_index[12:8] = 5'b00000;
                                end
                        end
 
                        READ_FROM_POINTER_X: begin
                                {page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
                                //address_plus_index[12:8] = 5'b00000;
                        end
 
                        READ_MEM_CALC_INDEX: begin
                                {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                                //address_plus_index[12:8] = 5'b00000;
                        end
                endcase
        end
 
        reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 13'h0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 9'b111111111; // the default is 'h1FF 
                        ir <= 8'h00;
                        temp_addr <= 13'h0000;
                        temp_data <= 8'h00;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 13'h0000;
                        rw_mem <= MEM_READ;
                        data_out <= 8'h00;
                        rst_counter <= 3'h0;
                        index <= 8'h00;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin    // The processor was reset
                                        rst_counter <= rst_counter + 3'b001;
                                        //sp <= 9'b111111111; // this prevents flipflops with different drivers
                                        //$write("under reset"); 
                                end
                                /*
                                FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
                                FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
                                */
                                FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        rw_mem <= MEM_READ;
                                        ir <= data_in;
                                end
                                /*
                                in this state the opcode is already known so truly execution begins.
                                all instructions execute this cycle.
                                */
                                FETCH_LOW: begin
                                        //$display("index_is_x = %b",index_is_x);
                                        if (index_is_x == 1'b1) begin
                                                index <= alu_x;
                                                //$display("alu_x = %d",alu_x);
                                        end
                                        else begin
                                                index <= alu_y;
                                                //$display("alu_y = %d",alu_y);
                                        end
                                        if (index_is_branch) begin
                                                index <= temp_data;
                                        end
                                        if (accumulator || implied || txs || tsx) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                rw_mem <= MEM_READ;
 
                                                if (txs) begin
                                                        sp[7:0] <= alu_x;
                                                end
                                                //alu_a
                                        end
                                        else if (immediate || relative) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                rw_mem <= MEM_READ;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute || absolute_indexed || jump_indirect) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                rw_mem <= MEM_READ;
                                                temp_addr <= {{5{1'b0}},data_in};
                                                temp_data <= 8'h00;
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
 
                                                if (write) begin
                                                        rw_mem <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        rw_mem <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        else if (zero_page_indexed) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}}, data_in};
                                                temp_addr <= {{5{1'b0}}, data_in};
                                                rw_mem <= MEM_READ;
                                        end
                                        else if (indirectx || indirecty) begin
                                                pc <= next_pc;
                                                address <= data_in;
                                                temp_data <= data_in;
                                                rw_mem <= MEM_READ;
                                        end
                                        else begin // the special instructions will fall here: BRK, RTI, RTS...
                                                if (brk) begin
                                                        pc <= next_pc;
                                                        address <= sp;
                                                        data_out <= {{3{1'b0}}, pc[12:8]};
                                                        rw_mem <= MEM_WRITE;
                                                end
                                                else if (rti || rts) begin
                                                        address <= sp;
                                                        rw_mem <= MEM_READ;
                                                end
                                                else if (pha || php) begin
                                                        pc <= pc;
                                                        address <= sp;
                                                        data_out <= (pha) ? alu_result : alu_status;
                                                        rw_mem <= MEM_WRITE;
                                                end
                                                else if (pla || plp) begin
                                                        pc <= pc;
                                                        address <= sp;
                                                        rw_mem <= MEM_READ;
                                                end
                                                else if (invalid) begin
                                                        address <= pc;
                                                        rw_mem <= MEM_READ;
                                                end
                                                else begin // jsr
                                                        address <= sp;
                                                        rw_mem <= MEM_READ;
                                                        temp_addr <= {{5{1'b0}}, data_in};
                                                        pc <= next_pc;
                                                end
                                        end
                                end
                                FETCH_HIGH_CALC_INDEX: begin
                                        pc <= next_pc;
                                        temp_addr[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], address_plus_index[7:0]};
                                        rw_mem <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                // this cycle fetchs the next operand while still evaluating if a branch occurred.
                                FETCH_OP_EVAL_BRANCH: begin
                                        if (branch) begin
                                                pc <= {{5{1'b0}}, address_plus_index[7:0]};
                                                address <= {{5{1'b0}}, address_plus_index[7:0]};
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
                                                ir <= data_in;
                                        end
                                end
                                // sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
                                FETCH_OP_FIX_PC: begin
                                        if (page_crossed) begin
                                                pc[12:8] <= address_plus_index[12:8];
                                                address[12:8] <= address_plus_index[12:8];
                                        end
                                        else begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                rw_mem <= MEM_READ;
                                                ir <= data_in;
                                        end
                                end
                                // several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        rw_mem <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        rw_mem <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                end
                                // read memory at address
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                rw_mem <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                end
                                READ_MEM_CALC_INDEX: begin
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                                if (write) begin
                                                        rw_mem <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        rw_mem <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
 
                                end
                                READ_MEM_FIX_ADDR: begin
                                        if (read) begin
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
 
                                                if (page_crossed) begin // fix address 
                                                        address <= address_plus_index;
                                                        temp_addr <= address_plus_index;
                                                end
                                                else begin
                                                        address <= pc;
                                                        temp_data <= data_in;
                                                end
                                        end
                                        else if (write) begin
                                                rw_mem <= MEM_WRITE;
                                                data_out <= alu_result;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                        end
                                        else begin // read modify write
                                                rw_mem <= MEM_READ;
                                                data_out <= 8'h00;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
                                        end
                                end
                                // some instructions have a dummy write cycle. this is it.
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        rw_mem <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                        rw_mem <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                READ_FROM_POINTER: begin
                                        if (jump_indirect) begin
                                                pc[7:0] <= data_in;
                                                rw_mem <= MEM_READ;
                                                address <= address_plus_index;
                                        end
                                        else begin
                                                pc <= pc;
                                                rw_mem <= MEM_READ;
 
                                                if (indirectx) begin
                                                        address <= address_plus_index;
                                                end
                                                else begin // indirecty falls here
                                                        address <= address_plus_index;
                                                        temp_addr <= {{5{1'b0}}, data_in};
                                                end
                                        end
                                end
                                READ_FROM_POINTER_X: begin
                                        pc <= pc;
                                        address <= address_plus_index;
                                        temp_addr[7:0] <= data_in;
                                        rw_mem <= MEM_READ;
                                end
                                READ_FROM_POINTER_X1: begin
                                        if (jump_indirect) begin
                                                pc[12:8] <= data_in[4:0];
                                                rw_mem <= MEM_READ;
                                                address <= {data_in[4:0], pc[7:0]};
                                        end
                                        else if (indirectx) begin
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                if (write) begin
                                                        rw_mem <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        rw_mem <= MEM_READ;
                                                end
                                        end
                                        else begin // indirecty falls here
                                                address <= address_plus_index;
                                                temp_addr[12:8] <= data_in;
                                                rw_mem <= MEM_READ;
                                        end
                                end
                                PUSH_PCH: begin // this is probably wrong
                                        pc <= pc;
                                        address <= sp_minus_one;
                                        data_out <= pc[7:0];
                                        rw_mem <= MEM_WRITE;
                                        sp <= sp_minus_one;
                                end
                                PUSH_PCL: begin
                                        if (jsr) begin
                                                pc <= pc;
                                                address <= pc;
                                                rw_mem <= MEM_READ;
                                                sp <= sp_minus_one;
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= sp_minus_one;
                                                data_out <= alu_status;
                                                rw_mem <= MEM_WRITE;
                                                sp <= sp_minus_one;
                                        end
                                end
                                PUSH_STATUS: begin
                                        address <= 13'h1FFE;
                                        rw_mem <= MEM_READ;
                                        sp <= sp_minus_one;
                                end
                                FETCH_PCL: begin
                                        pc[7:0] <= data_in;
                                        address <= 13'h1FFF;
                                        rw_mem <= MEM_READ;
                                end
                                FETCH_PCH: begin
                                        pc[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], pc[7:0]};
                                        rw_mem <= MEM_READ;
                                end
                                INCREMENT_SP: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                end
                                PULL_STATUS: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                        temp_data <= data_in;
                                end
                                PULL_PCL: begin
                                        sp <= sp_plus_one;
                                        address <= sp_plus_one;
                                        pc[7:0] <= data_in;
                                end
                                PULL_PCH: begin
                                        pc[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], pc[7:0]};
                                end
                                INCREMENT_PC: begin
                                        pc <= next_pc;
                                        address <= next_pc;
                                end
                                PUSH_REGISTER: begin
                                        pc <= pc;
                                        address <= pc;
                                        sp <= sp_minus_one;
                                        rw_mem <= MEM_READ;
                                        temp_data <= data_in;
                                end
                                PULL_REGISTER: begin
                                        pc <= pc;
                                        address <= pc;
                                        temp_data <= data_in;
                                end
                                DUMMY: begin
                                        address <= sp;
                                        rw_mem <= MEM_WRITE;
                                end
                                default: begin
                                        //$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        //$finish(0); 
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the combinational output logic always block
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
                next_state = RESET; // these lines prevents latches
 
                if (invalid == 1'b1) begin
                        next_state = FETCH_OP;
                end
                else case (state)
                        RESET: begin
                                if (rst_counter == 3'd6) begin
                                        next_state = FETCH_OP;
                                end
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied || txs) begin
                                        if (!nop) begin
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                        end
                                        next_state = FETCH_OP;
                                end
                                else if (tsx) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                        alu_a = sp[7:0];
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                        else begin
                                                //$write("unknown behavior"); 
                                                //$finish(0);
                                        end
                                end
                                else if (zero_page_indexed) begin
                                        next_state = READ_MEM_CALC_INDEX;
                                end
                                else if (absolute || jump_indirect) begin
                                        next_state = FETCH_HIGH;
                                        if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                end
                                else if (absolute_indexed) begin
                                        next_state = FETCH_HIGH_CALC_INDEX;
                                end
                                else if (relative) begin
                                        next_state = FETCH_OP_EVAL_BRANCH;
                                end
                                else if (indirectx || indirecty) begin
                                        next_state = READ_FROM_POINTER;
                                end
                                else begin // all the special instructions will fall here
                                        if (brk) begin
                                                next_state = PUSH_PCH;
                                        end
                                        else if (rti || rts) begin
                                                next_state = INCREMENT_SP;
                                        end
                                        else if (pha) begin
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                //alu_a = 8'h00;
                                                next_state = PUSH_REGISTER;
                                        end
                                        else if (php) begin
                                                next_state = PUSH_REGISTER;
                                        end
                                        else if (pla || plp) begin
                                                next_state = INCREMENT_SP;
                                        end
                                        else begin // jsr
                                                next_state = DUMMY;
                                        end
                                end
                        end
                        READ_FROM_POINTER: begin
                                if (indirectx) begin
                                        next_state = READ_FROM_POINTER_X;
                                end
                                else begin // indirecty and jump indirect falls here
                                        next_state = READ_FROM_POINTER_X1;
                                end
                        end
                        READ_FROM_POINTER_X: begin
                                next_state = READ_FROM_POINTER_X1;
                        end
                        READ_FROM_POINTER_X1: begin
                                if (jump_indirect) begin
                                        next_state = FETCH_OP;
                                end
                                else if (indirecty) begin
                                        next_state = READ_MEM_FIX_ADDR;
                                end
                                else begin
                                        if (read) begin // no instruction using pointers is from type read_modify_write
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                next_state = WRITE_MEM;
                                        end
                                end
                        end
                        FETCH_OP_EVAL_BRANCH: begin
                                if (branch) begin
                                        next_state = FETCH_OP_FIX_PC;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_OP_FIX_PC: begin
                                if (page_crossed) begin
                                        next_state = FETCH_OP;
                                end
                                else begin
                                        next_state = FETCH_LOW;
                                end
                        end
                        FETCH_HIGH_CALC_INDEX: begin
                                next_state = READ_MEM_FIX_ADDR;
                        end
                        READ_MEM_FIX_ADDR: begin
                                if (read) begin
                                        if (page_crossed) begin
                                                next_state = READ_MEM;
                                        end
                                        else begin
                                                next_state = FETCH_OP_CALC_PARAM;
                                        end
                                end
                                else if (read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                        alu_enable = 1'b1;
                                        alu_opcode = ir;
                                end
                                else begin
                                        //$write("unknown behavior"); 
                                        //$finish(0);
                                end
                        end
                        FETCH_HIGH: begin
                                if (jump_indirect) begin
                                        next_state = READ_FROM_POINTER;
                                end
                                else if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        //$write("unknown behavior"); 
                                        //$finish(0);
                                end
                        end
                        READ_MEM_CALC_INDEX: begin
                                if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        //$write("unknown behavior"); 
                                        //$finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        PUSH_PCH: begin
                                next_state = PUSH_PCL;
                        end
                        PUSH_PCL: begin
                                if (jsr) begin
                                        next_state = FETCH_HIGH;
                                end
                                else begin
                                        next_state = PUSH_STATUS;
                                end
                        end
                        PUSH_STATUS: begin
                                next_state = FETCH_PCL;
                        end
                        FETCH_PCL: begin
                                next_state = FETCH_PCH;
                        end
                        FETCH_PCH: begin
                                next_state = FETCH_OP;
                        end
                        INCREMENT_SP: begin
                                if (rti) begin
                                        next_state = PULL_STATUS;
                                end
                                else if (pla || plp) begin
                                        next_state = PULL_REGISTER;
                                end
                                else begin // rts
                                        next_state = PULL_PCL;
                                end
                        end
                        PULL_STATUS: begin
                                next_state = PULL_PCL;
                        end
                        PULL_PCL: begin
                                next_state = PULL_PCH;
 
                                if (rti) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        alu_a = temp_data;
                                end
                        end
                        PULL_PCH: begin
                                if (rti) begin
                                        next_state = FETCH_OP;
                                end
                                else begin // rts
                                        next_state = INCREMENT_PC;
                                end
                        end
                        INCREMENT_PC: begin
                                next_state = FETCH_OP;
                        end
                        PUSH_REGISTER: begin
                                next_state = FETCH_OP;
                        end
                        PULL_REGISTER: begin
                                next_state = FETCH_OP_CALC_PARAM;
                        end
                        DUMMY: begin
                                next_state = PUSH_PCH;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirectx = 1'b0;
                indirecty = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
                //index_is_x = 1'b1;
                index_is_branch = 1'b0;
 
                //index = 8'h00;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
                jump_indirect = 1'b0;
                branch = 1'b0;
 
                brk = 1'b0;
                rti = 1'b0;
                rts = 1'b0;
                pha = 1'b0;
                php = 1'b0;
                pla = 1'b0;
                plp = 1'b0;
                jsr = 1'b0;
                tsx = 1'b0;
                txs = 1'b0;
                nop = 1'b0;
 
                invalid = 1'b0;
 
                case (ir)
                        CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP,
                        TAY_IMP, TXA_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        NOP_IMP: begin
                                implied = 1'b1;
                                nop = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                                index_is_x = 1'b1;
                                //index = alu_x;
                        end
                        LDX_ZPY, STX_ZPY: begin
                                zero_page_indexed = 1'b1;
                                index_is_x = 1'b0;
                                //index = alu_y;
                        end
                        BCC_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (!alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BCS_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (alu_status[C]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BEQ_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (alu_status[Z]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BNE_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (alu_status[Z] == 1'b0) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BPL_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (!alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BMI_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (alu_status[N]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVC_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (!alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        BVS_REL: begin
                                relative = 1'b1;
                                index_is_branch = 1'b1;
                                //index = temp_data;
 
                                if (alu_status[V]) begin
                                        branch = 1'b1;
                                end
                                else begin
                                        branch = 1'b0;
                                end
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX: begin
                                absolute_indexed = 1'b1;
                                index_is_x = 1'b1;
                                //index = alu_x;
                        end
                        ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                                index_is_x = 1'b0;
                                //index = alu_y;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX: begin
                                indirectx = 1'b1;
                                index_is_x = 1'b1;
                                //index = alu_x;
                        end
                        ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, ORA_IDY, SBC_IDY, STA_IDY: begin
                                indirecty = 1'b1;
                                index_is_x = 1'b0;
                                //index = alu_y;        
                        end
                        JMP_ABS: begin
                                absolute = 1'b1;
                                jump = 1'b1;
                        end
                        JMP_IND: begin
                                jump_indirect = 1'b1;
                        end
                        BRK_IMP: begin
                                brk = 1'b1;
                        end
                        RTI_IMP: begin
                                rti = 1'b1;
                        end
                        RTS_IMP: begin
                                rts = 1'b1;
                        end
                        PHA_IMP: begin
                                pha = 1'b1;
                        end
                        PHP_IMP: begin
                                php = 1'b1;
                        end
                        PLA_IMP: begin
                                pla = 1'b1;
                        end
                        PLP_IMP: begin
                                plp = 1'b1;
                        end
                        JSR_ABS: begin
                                jsr = 1'b1;
                                jump = 1'b1;
                        end
                        TSX_IMP: begin
                                tsx = 1'b1;
                        end
                        TXS_IMP: begin
                                txs = 1'b1;
                        end
                        default: begin
                                index_is_x = 1'b1;
                                //$write("state : %b", state);
                                if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
                                        invalid = 1'b1;
                                        //$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                        //$finish();
                                end
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
        end
endmodule
 
 
 

Line No.	Rev	Author	Line
1	128	gabrielosh	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Fix relative mode, bit 7 means negative ////`
13			`//// - Check reset behavior ////`
14			`//// - Comment the code ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
18			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
19			`//// ////`
20			`////////////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`////////////////////////////////////////////////////////////////////////////`
46
47			`include "timescale.v"
48
49	253	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, alu_x, alu_y, address, rw_mem, data_out, alu_opcode, alu_a, alu_enable);`
50	128	gabrielosh	`parameter [3:0] DATA_SIZE = 4'd8;`
51			`parameter [3:0] ADDR_SIZE = 4'd13;`
52
53			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;`
54			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
55
56			`input clk; // master clock`
57			`input reset_n; // active low reset`
58			`input [DATA_SIZE_:0] alu_result; // result from alu operation`
59			`input [DATA_SIZE_:0] alu_status; // alu status register`
60			`input [DATA_SIZE_:0] data_in; // data that comes from the bus controller`
61			`input [DATA_SIZE_:0] alu_x; // alu x index register`
62			`input [DATA_SIZE_:0] alu_y; // alu y index register`
63			`output reg [ADDR_SIZE_:0] address; // system bus address`
64	253	creep	`output reg rw_mem; // read = 0, write = 1`
65	128	gabrielosh	`output reg [DATA_SIZE_:0] data_out; // data that will be written somewhere else`
66			`output reg [DATA_SIZE_:0] alu_opcode; // current opcode`
67			`output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu`
68			`output reg alu_enable; // a flag that when high tells the alu when to perform the operations`
69
70
71			`// FSM states. If aiming for less power consumption try gray coding.`
72			`//localparam FETCH_OP_CALC = 5'b00001; this was never used`
73			`localparam FETCH_OP = 5'b00000;`
74			`localparam FETCH_LOW = 5'b00010;`
75			`localparam FETCH_HIGH = 5'b00011;`
76			`localparam READ_MEM = 5'b00100;`
77			`localparam DUMMY_WRT_CALC = 5'b00101;`
78			`localparam WRITE_MEM = 5'b00110;`
79			`localparam FETCH_OP_CALC_PARAM = 5'b00111;`
80			`localparam READ_MEM_CALC_INDEX = 5'b01000;`
81			`localparam FETCH_HIGH_CALC_INDEX = 5'b01001;`
82			`localparam READ_MEM_FIX_ADDR = 5'b01010;`
83			`localparam FETCH_OP_EVAL_BRANCH = 5'b01011;`
84			`localparam FETCH_OP_FIX_PC = 5'b01100;`
85			`localparam READ_FROM_POINTER = 5'b01101;`
86			`localparam READ_FROM_POINTER_X = 5'b01110;`
87			`localparam READ_FROM_POINTER_X1 = 5'b01111;`
88			`localparam PUSH_PCH = 5'b10000;`
89			`localparam PUSH_PCL = 5'b10001;`
90			`localparam PUSH_STATUS = 5'b10010;`
91			`localparam FETCH_PCL = 5'b10011;`
92			`localparam FETCH_PCH = 5'b10100;`
93			`localparam INCREMENT_SP = 5'b10101;`
94			`localparam PULL_STATUS = 5'b10110;`
95			`localparam PULL_PCL = 5'b10111;`
96			`localparam PULL_PCH = 5'b11000;`
97			`localparam INCREMENT_PC = 5'b11001;`
98			`localparam PUSH_REGISTER = 5'b11010;`
99			`localparam PULL_REGISTER = 5'b11011;`
100			`localparam DUMMY = 5'b11100;`
101			`localparam RESET = 5'b11111;`
102
103			`// OPCODES TODO: verify how this get synthesised`
104	146	creep	`include "t6507lp_package.v"
105	128	gabrielosh
106	253	creep	`// rw_mem signals`
107	128	gabrielosh	`localparam MEM_READ = 1'b0;`
108			`localparam MEM_WRITE = 1'b1;`
109
110			`reg [ADDR_SIZE_:0] pc; // program counter`
111			`reg [DATA_SIZE:0] sp; // stack pointer. 9 bits wide.`
112			`reg [DATA_SIZE_:0] ir; // instruction register`
113			`reg [ADDR_SIZE_:0] temp_addr; // temporary address`
114			`reg [DATA_SIZE_:0] temp_data; // temporary data`
115
116			`reg [4:0] state, next_state; // current and next state registers`
117
118			`// wiring that simplifies the FSM logic by simplifying the addressing modes`
119			`reg absolute;`
120			`reg absolute_indexed;`
121			`reg accumulator;`
122			`reg immediate;`
123			`reg implied;`
124			`reg indirectx;`
125			`reg indirecty;`
126			`reg relative;`
127			`reg zero_page;`
128			`reg zero_page_indexed;`
129			`reg [DATA_SIZE_:0] index; // will be assigned with either X or Y`
130
131			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
132			`reg read;`
133			`reg read_modify_write;`
134			`reg write;`
135			`reg jump;`
136			`reg jump_indirect;`
137	212	creep	`reg index_is_x;`
138			`reg index_is_branch;`
139	128	gabrielosh
140			`// regs for the special instructions`
141			`reg brk;`
142			`reg rti;`
143			`reg rts;`
144			`reg pha;`
145			`reg php;`
146	212	creep	`reg pla;`
147	128	gabrielosh	`reg plp;`
148	194	creep	`reg jsr;`
149			`reg tsx;`
150	205	creep	`reg txs;`
151	212	creep	`reg nop;`
152	128	gabrielosh
153	246	creep	`reg invalid;`
154
155	128	gabrielosh	`wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC`
156			`assign next_pc = pc + 13'b0000000000001;`
157
158	200	creep	`wire [DATA_SIZE:0] sp_plus_one; // simple adder and subtracter for the stack pointer`
159			`assign sp_plus_one = {1'b1, sp[7:0] + 8'b000000001};`
160	128	gabrielosh
161	200	creep	`wire [DATA_SIZE:0] sp_minus_one;`
162			`assign sp_minus_one = {1'b1, sp[7:0] - 8'b000000001};`
163	128	gabrielosh
164			`reg [ADDR_SIZE_:0] address_plus_index; // this two registers are used when the instruction uses indexing.`
165			`reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.`
166
167			`reg branch; // a simple reg that is asserted everytime a branch will be executed.`
168
169			`// this is the combinational logic related to indexed instructions`
170			`always @(*) begin`
171	200	creep	`address_plus_index = 13'h000;`
172	128	gabrielosh	`page_crossed = 1'b0;`
173
174	212	creep	`case (state)`
175	242	creep	`READ_MEM_FIX_ADDR, FETCH_HIGH_CALC_INDEX: begin`
176	212	creep	`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
177			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
178	128	gabrielosh	`end`
179	242	creep	`READ_FROM_POINTER_X1: begin`
180			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
181	243	creep	`address_plus_index[12:8] = data_in[4:0];`
182	242	creep	`end`
183	212	creep	`FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin`
184			`if (branch) begin`
185			`{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;`
186			`address_plus_index[12:8] = pc[12:8] + page_crossed;`
187			`// warning: pc might feed these lines twice and cause branch failure`
188			`end // solution: add a temp reg i guess`
189	128	gabrielosh	`end`
190	212	creep
191			`READ_FROM_POINTER: begin`
192			`if (indirectx) begin`
193			`{page_crossed, address_plus_index[7:0]} = temp_data + index;`
194			`//address_plus_index[12:8] = 5'b00000; // already assigned earlier at this block`
195			`end`
196			`else if (jump_indirect) begin`
197			`address_plus_index[7:0] = temp_addr[7:0] + 8'h01;`
198			`//address_plus_index[12:8] = 5'b00000;`
199			`end`
200			`else begin // indirecty falls here`
201			`address_plus_index[7:0] = temp_data + 8'h01;`
202			`//address_plus_index[12:8] = 5'b00000;`
203			`end`
204	128	gabrielosh	`end`
205	212	creep
206			`READ_FROM_POINTER_X: begin`
207			`{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;`
208			`//address_plus_index[12:8] = 5'b00000;`
209			`end`
210
211			`READ_MEM_CALC_INDEX: begin`
212			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
213			`//address_plus_index[12:8] = 5'b00000;`
214			`end`
215			`endcase`
216	128	gabrielosh	`end`
217
218	146	creep	`reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles`
219
220	128	gabrielosh	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
221			`if (reset_n == 1'b0) begin`
222			`// all registers must assume default values`
223	200	creep	`pc <= 13'h0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
224	194	creep	`sp <= 9'b111111111; // the default is 'h1FF`
225	128	gabrielosh	`ir <= 8'h00;`
226			`temp_addr <= 13'h0000;`
227			`temp_data <= 8'h00;`
228			`state <= RESET;`
229			`// registered outputs also receive default values`
230			`address <= 13'h0000;`
231	253	creep	`rw_mem <= MEM_READ;`
232	128	gabrielosh	`data_out <= 8'h00;`
233	200	creep	`rst_counter <= 3'h0;`
234	212	creep	`index <= 8'h00;`
235	128	gabrielosh	`end`
236			`else begin`
237			`state <= next_state;`
238	146	creep
239	128	gabrielosh	`case (state)`
240			`RESET: begin // The processor was reset`
241	200	creep	`rst_counter <= rst_counter + 3'b001;`
242	194	creep	`//sp <= 9'b111111111; // this prevents flipflops with different drivers`
243	128	gabrielosh	`//$write("under reset");`
244			`end`
245			`/*`
246			`FETCH_OP: executed when the processor was reset or the last instruction could not fetch.`
247			`FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)`
248			`*/`
249			`FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
250			`pc <= next_pc;`
251			`address <= next_pc;`
252	253	creep	`rw_mem <= MEM_READ;`
253	128	gabrielosh	`ir <= data_in;`
254			`end`
255			`/*`
256			`in this state the opcode is already known so truly execution begins.`
257			`all instructions execute this cycle.`
258			`*/`
259	196	creep	`FETCH_LOW: begin`
260	212	creep	`//$display("index_is_x = %b",index_is_x);`
261			`if (index_is_x == 1'b1) begin`
262			`index <= alu_x;`
263			`//$display("alu_x = %d",alu_x);`
264			`end`
265			`else begin`
266			`index <= alu_y;`
267			`//$display("alu_y = %d",alu_y);`
268			`end`
269			`if (index_is_branch) begin`
270			`index <= temp_data;`
271			`end`
272	195	creep	`if (accumulator \|\| implied \|\| txs \|\| tsx) begin`
273	128	gabrielosh	`pc <= pc; // is this better?`
274			`address <= pc;`
275	253	creep	`rw_mem <= MEM_READ;`
276	194	creep
277			`if (txs) begin`
278	196	creep	`sp[7:0] <= alu_x;`
279	194	creep	`end`
280			`//alu_a`
281	128	gabrielosh	`end`
282			`else if (immediate \|\| relative) begin`
283			`pc <= next_pc;`
284			`address <= next_pc;`
285	253	creep	`rw_mem <= MEM_READ;`
286	128	gabrielosh	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
287			`end`
288			`else if (absolute \|\| absolute_indexed \|\| jump_indirect) begin`
289			`pc <= next_pc;`
290	196	creep	`address <= next_pc;`
291	253	creep	`rw_mem <= MEM_READ;`
292	128	gabrielosh	`temp_addr <= {{5{1'b0}},data_in};`
293			`temp_data <= 8'h00;`
294			`end`
295			`else if (zero_page) begin`
296			`pc <= next_pc;`
297			`address <= {{5{1'b0}},data_in};`
298			`temp_addr <= {{5{1'b0}},data_in};`
299
300			`if (write) begin`
301	253	creep	`rw_mem <= MEM_WRITE;`
302	128	gabrielosh	`data_out <= alu_result;`
303			`end`
304			`else begin`
305	253	creep	`rw_mem <= MEM_READ;`
306	128	gabrielosh	`data_out <= 8'h00;`
307			`end`
308			`end`
309			`else if (zero_page_indexed) begin`
310			`pc <= next_pc;`
311			`address <= {{5{1'b0}}, data_in};`
312			`temp_addr <= {{5{1'b0}}, data_in};`
313	253	creep	`rw_mem <= MEM_READ;`
314	128	gabrielosh	`end`
315			`else if (indirectx \|\| indirecty) begin`
316			`pc <= next_pc;`
317			`address <= data_in;`
318			`temp_data <= data_in;`
319	253	creep	`rw_mem <= MEM_READ;`
320	128	gabrielosh	`end`
321			`else begin // the special instructions will fall here: BRK, RTI, RTS...`
322			`if (brk) begin`
323			`pc <= next_pc;`
324			`address <= sp;`
325			`data_out <= {{3{1'b0}}, pc[12:8]};`
326	253	creep	`rw_mem <= MEM_WRITE;`
327	128	gabrielosh	`end`
328			`else if (rti \|\| rts) begin`
329			`address <= sp;`
330	253	creep	`rw_mem <= MEM_READ;`
331	128	gabrielosh	`end`
332			`else if (pha \|\| php) begin`
333			`pc <= pc;`
334			`address <= sp;`
335			`data_out <= (pha) ? alu_result : alu_status;`
336	253	creep	`rw_mem <= MEM_WRITE;`
337	128	gabrielosh	`end`
338			`else if (pla \|\| plp) begin`
339			`pc <= pc;`
340			`address <= sp;`
341	253	creep	`rw_mem <= MEM_READ;`
342	128	gabrielosh	`end`
343	246	creep	`else if (invalid) begin`
344			`address <= pc;`
345	253	creep	`rw_mem <= MEM_READ;`
346	246	creep	`end`
347	128	gabrielosh	`else begin // jsr`
348			`address <= sp;`
349	253	creep	`rw_mem <= MEM_READ;`
350	128	gabrielosh	`temp_addr <= {{5{1'b0}}, data_in};`
351			`pc <= next_pc;`
352			`end`
353			`end`
354			`end`
355			`FETCH_HIGH_CALC_INDEX: begin`
356			`pc <= next_pc;`
357			`temp_addr[12:8] <= data_in[4:0];`
358			`address <= {data_in[4:0], address_plus_index[7:0]};`
359	253	creep	`rw_mem <= MEM_READ;`
360	128	gabrielosh	`data_out <= 8'h00;`
361			`end`
362			`// this cycle fetchs the next operand while still evaluating if a branch occurred.`
363			`FETCH_OP_EVAL_BRANCH: begin`
364			`if (branch) begin`
365			`pc <= {{5{1'b0}}, address_plus_index[7:0]};`
366			`address <= {{5{1'b0}}, address_plus_index[7:0]};`
367	253	creep	`rw_mem <= MEM_READ;`
368	128	gabrielosh	`data_out <= 8'h00;`
369			`end`
370			`else begin`
371			`pc <= next_pc;`
372			`address <= next_pc;`
373	253	creep	`rw_mem <= MEM_READ;`
374	128	gabrielosh	`data_out <= 8'h00;`
375			`ir <= data_in;`
376			`end`
377			`end`
378			`// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100`
379			`FETCH_OP_FIX_PC: begin`
380			`if (page_crossed) begin`
381			`pc[12:8] <= address_plus_index[12:8];`
382			`address[12:8] <= address_plus_index[12:8];`
383			`end`
384			`else begin`
385			`pc <= next_pc;`
386			`address <= next_pc;`
387	253	creep	`rw_mem <= MEM_READ;`
388	128	gabrielosh	`ir <= data_in;`
389			`end`
390			`end`
391			`// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.`
392			`FETCH_HIGH: begin`
393			`if (jump) begin`
394			`pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte`
395			`address <= {data_in[4:0], temp_addr[7:0]};`
396	253	creep	`rw_mem <= MEM_READ;`
397	128	gabrielosh	`data_out <= 8'h00;`
398			`end`
399			`else begin`
400			`if (write) begin`
401			`pc <= next_pc;`
402			`temp_addr[12:8] <= data_in[4:0];`
403			`address <= {data_in[4:0],temp_addr[7:0]};`
404	253	creep	`rw_mem <= MEM_WRITE;`
405	128	gabrielosh	`data_out <= alu_result;`
406			`end`
407			`else begin // read_modify_write or just read`
408			`pc <= next_pc;`
409			`temp_addr[12:8] <= data_in[4:0];`
410			`address <= {data_in[4:0],temp_addr[7:0]};`
411	253	creep	`rw_mem <= MEM_READ;`
412	128	gabrielosh	`data_out <= 8'h00;`
413			`end`
414			`end`
415			`end`
416			`// read memory at address`
417			`READ_MEM: begin`
418			`if (read_modify_write) begin`
419			`pc <= pc;`
420			`address <= temp_addr;`
421	253	creep	`rw_mem <= MEM_WRITE;`
422	128	gabrielosh	`temp_data <= data_in;`
423			`data_out <= data_in; // writeback the same value`
424			`end`
425			`else begin`
426			`pc <= pc;`
427			`address <= pc;`
428			`temp_data <= data_in;`
429	253	creep	`rw_mem <= MEM_READ;`
430	128	gabrielosh	`data_out <= 8'h00;`
431			`end`
432			`end`
433			`READ_MEM_CALC_INDEX: begin`
434			`address <= address_plus_index;`
435			`temp_addr <= address_plus_index;`
436
437			`if (write) begin`
438	253	creep	`rw_mem <= MEM_WRITE;`
439	128	gabrielosh	`data_out <= alu_result;`
440			`end`
441			`else begin`
442	253	creep	`rw_mem <= MEM_READ;`
443	128	gabrielosh	`data_out <= 8'h00;`
444			`end`
445
446			`end`
447			`READ_MEM_FIX_ADDR: begin`
448			`if (read) begin`
449	253	creep	`rw_mem <= MEM_READ;`
450	128	gabrielosh	`data_out <= 8'h00;`
451
452			`if (page_crossed) begin // fix address`
453			`address <= address_plus_index;`
454			`temp_addr <= address_plus_index;`
455			`end`
456			`else begin`
457			`address <= pc;`
458			`temp_data <= data_in;`
459			`end`
460			`end`
461			`else if (write) begin`
462	253	creep	`rw_mem <= MEM_WRITE;`
463	128	gabrielosh	`data_out <= alu_result;`
464			`address <= address_plus_index;`
465			`temp_addr <= address_plus_index;`
466
467			`end`
468			`else begin // read modify write`
469	253	creep	`rw_mem <= MEM_READ;`
470	128	gabrielosh	`data_out <= 8'h00;`
471			`address <= address_plus_index;`
472			`temp_addr <= address_plus_index;`
473			`end`
474			`end`
475			`// some instructions have a dummy write cycle. this is it.`
476			`DUMMY_WRT_CALC: begin`
477			`pc <= pc;`
478			`address <= temp_addr;`
479	253	creep	`rw_mem <= MEM_WRITE;`
480	128	gabrielosh	`data_out <= alu_result;`
481			`end`
482			`WRITE_MEM: begin`
483			`pc <= pc;`
484			`address <= pc;`
485	253	creep	`rw_mem <= MEM_READ;`
486	128	gabrielosh	`data_out <= 8'h00;`
487			`end`
488			`READ_FROM_POINTER: begin`
489			`if (jump_indirect) begin`
490			`pc[7:0] <= data_in;`
491	253	creep	`rw_mem <= MEM_READ;`
492	128	gabrielosh	`address <= address_plus_index;`
493			`end`
494			`else begin`
495			`pc <= pc;`
496	253	creep	`rw_mem <= MEM_READ;`
497	128	gabrielosh
498			`if (indirectx) begin`
499			`address <= address_plus_index;`
500			`end`

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