URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Blame information for rev 68

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix absolute indexed mode                                        ////
//// - Code the relative mode                                           ////
//// - Code the indexed indirect mode                                   ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
 
        parameter DATA_SIZE = 4'd8;
        parameter ADDR_SIZE = 4'd13;
 
        input clk_in;
        input rst_in_n;
        input [DATA_SIZE-1:0] alu_result;
        input [DATA_SIZE-1:0] alu_status;
        input [DATA_SIZE-1:0] data_in;
        output reg [ADDR_SIZE-1:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE-1:0] data_out;
        output reg [DATA_SIZE-1:0] alu_opcode;
        output reg [DATA_SIZE-1:0] alu_a;
        output reg alu_enable;
 
 
        // FSM states
        localparam RESET = 4'b1111;
        localparam FETCH_OP = 4'b0000;
        localparam FETCH_OP_CALC = 4'b0001;
        localparam FETCH_LOW = 4'b0010;
        localparam FETCH_HIGH = 4'b0011;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE-1:0] pc;          // program counter
        reg [DATA_SIZE-1:0] sp;          // stack pointer
        reg [DATA_SIZE-1:0] ir;          // instruction register
        reg [ADDR_SIZE:0] temp_add;      // temporary address
        reg [DATA_SIZE-1:0] temp_data;   // temporary data
 
        reg [3:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
        // wiring that simplifies the FSM logic
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirect;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
 
        wire [ADDR_SIZE-1:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        always @ (posedge clk_in or negedge rst_in_n) begin
                if (rst_in_n == 1'b0) begin
                        // TODO: all internal flip-flops must assume default values
 
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
                        ir <= 0;
                        temp_add <= 0;
                        temp_data <= 0;
                        state <= RESET;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin
                                        // The processor was reset 
                                end
                                FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
                                                // the last cycle was a memory write.
                                        pc <= next_pc;
                                end
                                FETCH_OP_CALC: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                end
                                FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this necessary?
                                        end
                                        else begin
                                                pc <= next_pc;
                                                ir <= data_in; // opcode must be saved in the instruction register
                                        end
                                end
                                default: begin
                                        $write("unknown state");        // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and output logic always block
                address = pc;
                control = MEM_READ;
                data_out = 8'h00;
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
 
                next_state = RESET; // this prevents the latch 
 
                begin
                        case (state)
                                RESET: begin
                                        next_state = FETCH_OP;
                                end
                                FETCH_OP: begin
                                        next_state = FETCH_LOW;
                                end
                                FETCH_OP_CALC: begin
                                        next_state = FETCH_LOW;
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                end
                                FETCH_LOW: begin
                                        if (accumulator  || implied) begin
                                                alu_opcode = data_in;
                                                alu_enable = 1'b1;
                                                next_state = FETCH_OP;
                                        end
                                        else if (immediate) begin
                                                next_state = FETCH_OP_CALC;
                                        end
                                        else begin // at least the immediate address mode falls here
                                                next_state = FETCH_HIGH;
                                        end
                                end
                                default: begin
                                        next_state = RESET;
                                end
                        endcase
                end
        end
 
        // this always block is responsible for updating the address mode
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirect = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
 
                if (state == FETCH_LOW) begin
                        case (data_in)
                                BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                                PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                        implied = 1'b1;
                                end
                                ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                        accumulator = 1'b1;
                                end
                                ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                        immediate = 1'b1;
                                end
                                ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                                LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                        zero_page = 1'b1;
                                end
                                ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                                SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
                                        zero_page_indexed = 1'b1;
                                end
                                BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
                                        relative = 1'b1;
                                end
                                ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
                                LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                        absolute = 1'b1;
                                end
                                ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                                SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                        absolute_indexed = 1'b1;
                                end
                                ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
                                ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
                                        indirect = 1'b1;
                                end
                        endcase
 
                        if (data_in == JMP_ABS || data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
                                jump = 1'b1;
                        end
 
                //      if (data_in == )
 
/*LDA_IMM = 8'hA9,
LDA_ZPG = 8'hA5,
LDA_ZPX = 8'hB5,
LDA_ABS = 8'hAD,
LDA_ABX = 8'hBD,
LDA_ABY = 8'hB9,
LDA_IDX = 8'hA1,
LDA_IDY = 8'hB1;
LDX_IMM = 8'hA2,
LDX_ZPG = 8'hA6,
LDX_ZPY = 8'hB6,
LDX_ABS = 8'hAE,
LDX_ABY = 8'hBE;
LDY_IMM = 8'hA0,
LDY_ZPG = 8'hA4,
LDY_ZPX = 8'hB4,
LDY_ABS = 8'hAC,
LDY_ABX = 8'hBC;
*/
 
 
                end
        end // no way
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Fix absolute indexed mode ////`
13			`//// - Code the relative mode ////`
14			`//// - Code the indexed indirect mode ////`
15			`//// - Code the indirect indexed mode ////`
16			`//// - Code the absolute indirect mode ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
20			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
21			`//// ////`
22			`////////////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////////`
48
49			`timescale 1ns / 1ps
50
51	68	creep	`module t6507lp_fsm(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);`
52
53			`parameter DATA_SIZE = 4'd8;`
54			`parameter ADDR_SIZE = 4'd13;`
55
56	61	creep	`input clk_in;`
57	68	creep	`input rst_in_n;`
58			`input [DATA_SIZE-1:0] alu_result;`
59			`input [DATA_SIZE-1:0] alu_status;`
60			`input [DATA_SIZE-1:0] data_in;`
61			`output reg [ADDR_SIZE-1:0] address;`
62	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
63	68	creep	`output reg [DATA_SIZE-1:0] data_out;`
64			`output reg [DATA_SIZE-1:0] alu_opcode;`
65			`output reg [DATA_SIZE-1:0] alu_a;`
66			`output reg alu_enable;`
67	61	creep
68	68	creep
69	61	creep	`// FSM states`
70	68	creep	`localparam RESET = 4'b1111;`
71	63	creep	`localparam FETCH_OP = 4'b0000;`
72	68	creep	`localparam FETCH_OP_CALC = 4'b0001;`
73			`localparam FETCH_LOW = 4'b0010;`
74			`localparam FETCH_HIGH = 4'b0011;`
75	61	creep
76			`// OPCODES TODO: verify how this get synthesised`
77			`include "../T6507LP_Package.v"
78
79			`// control signals`
80			`localparam MEM_READ = 1'b0;`
81			`localparam MEM_WRITE = 1'b1;`
82
83	68	creep	`reg [ADDR_SIZE-1:0] pc; // program counter`
84			`reg [DATA_SIZE-1:0] sp; // stack pointer`
85			`reg [DATA_SIZE-1:0] ir; // instruction register`
86			`reg [ADDR_SIZE:0] temp_add; // temporary address`
87			`reg [DATA_SIZE-1:0] temp_data; // temporary data`
88	61	creep
89			`reg [3:0] state, next_state; // current and next state registers`
90			`// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.`
91
92			`// wiring that simplifies the FSM logic`
93			`reg absolute;`
94			`reg absolute_indexed;`
95			`reg accumulator;`
96			`reg immediate;`
97			`reg implied;`
98			`reg indirect;`
99			`reg relative;`
100			`reg zero_page;`
101			`reg zero_page_indexed;`
102
103			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
104			`reg read;`
105			`reg read_modify_write;`
106			`reg write;`
107			`reg jump;`
108
109	68	creep	`wire [ADDR_SIZE-1:0] next_pc;`
110	63	creep	`assign next_pc = pc + 13'b0000000000001;`
111	61	creep
112	68	creep	`always @ (posedge clk_in or negedge rst_in_n) begin`
113			`if (rst_in_n == 1'b0) begin`
114			`// TODO: all internal flip-flops must assume default values`
115	61	creep
116	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
117			`sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.`
118			`ir <= 0;`
119			`temp_add <= 0;`
120			`temp_data <= 0;`
121			`state <= RESET;`
122	61	creep	`end`
123			`else begin`
124			`state <= next_state;`
125
126			`case (state)`
127	68	creep	`RESET: begin`
128			`// The processor was reset`
129			`end`
130	61	creep	`FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or`
131			`// the last cycle was a memory write.`
132			`pc <= next_pc;`
133			`end`
134	68	creep	`FETCH_OP_CALC: begin // this is the pipeline happening!`
135	61	creep	`pc <= next_pc;`
136			`end`
137	68	creep	`FETCH_LOW: begin // in this state the opcode is already known so truly execution begins`
138			`if (accumulator \|\| implied) begin`
139			`pc <= pc; // is this necessary?`
140	61	creep	`end`
141			`else begin`
142	68	creep	`pc <= next_pc;`
143			`ir <= data_in; // opcode must be saved in the instruction register`
144	61	creep	`end`
145			`end`
146			`default: begin`
147	68	creep	$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
148			`$finish(0);`
149	61	creep	`end`
150
151			`endcase`
152			`end`
153			`end`
154
155	68	creep	`always @ (*) begin // this is the next_state logic and output logic always block`
156			`address = pc;`
157			`control = MEM_READ;`
158			`data_out = 8'h00;`
159			`alu_opcode = 8'h00;`
160			`alu_a = 8'h00;`
161			`alu_enable = 1'b0;`
162	61	creep
163	68	creep	`next_state = RESET; // this prevents the latch`
164
165			`begin`
166			`case (state)`
167			`RESET: begin`
168			`next_state = FETCH_OP;`
169	61	creep	`end`
170			`FETCH_OP: begin`
171			`next_state = FETCH_LOW;`
172			`end`
173	68	creep	`FETCH_OP_CALC: begin`
174			`next_state = FETCH_LOW;`
175			`alu_opcode = ir;`
176			`alu_enable = 1'b1;`
177			`end`
178	61	creep	`FETCH_LOW: begin`
179			`if (accumulator \|\| implied) begin`
180	68	creep	`alu_opcode = data_in;`
181			`alu_enable = 1'b1;`
182			`next_state = FETCH_OP;`
183	61	creep	`end`
184	68	creep	`else if (immediate) begin`
185			`next_state = FETCH_OP_CALC;`
186	61	creep	`end`
187	68	creep	`else begin // at least the immediate address mode falls here`
188	61	creep	`next_state = FETCH_HIGH;`
189			`end`
190			`end`
191	68	creep	`default: begin`
192			`next_state = RESET;`
193	61	creep	`end`
194			`endcase`
195			`end`
196			`end`
197
198			`// this always block is responsible for updating the address mode`
199	68	creep	`always @ (*) begin //`
200	61	creep	`absolute = 1'b0;`
201			`absolute_indexed = 1'b0;`
202			`accumulator = 1'b0;`
203			`immediate = 1'b0;`
204			`implied = 1'b0;`
205			`indirect = 1'b0;`
206			`relative = 1'b0;`
207			`zero_page = 1'b0;`
208			`zero_page_indexed = 1'b0;`
209
210			`read = 1'b0;`
211			`read_modify_write = 1'b0;`
212			`write = 1'b0;`
213			`jump = 1'b0;`
214
215	68	creep	`if (state == FETCH_LOW) begin`
216	61	creep	`case (data_in)`
217			`BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,`
218			`PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin`
219			`implied = 1'b1;`
220			`end`
221			`ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin`
222			`accumulator = 1'b1;`
223			`end`
224			`ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin`
225			`immediate = 1'b1;`
226			`end`
227			`ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,`
228			`LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin`
229			`zero_page = 1'b1;`
230			`end`
231			`ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,`
232			`SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin`
233			`zero_page_indexed = 1'b1;`
234			`end`
235			`BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin`
236			`relative = 1'b1;`
237			`end`
238			`ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,`
239			`LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin`
240			`absolute = 1'b1;`
241			`end`
242			`ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,`
243			`SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin`
244			`absolute_indexed = 1'b1;`
245			`end`
246			`ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,`
247			`ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this`
248			`indirect = 1'b1;`
249			`end`
250			`endcase`
251
252			`if (data_in == JMP_ABS \|\| data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C`
253			`jump = 1'b1;`
254			`end`
255
256			`// if (data_in == )`
257
258			`/*LDA_IMM = 8'hA9,`
259			`LDA_ZPG = 8'hA5,`
260			`LDA_ZPX = 8'hB5,`
261			`LDA_ABS = 8'hAD,`
262			`LDA_ABX = 8'hBD,`
263			`LDA_ABY = 8'hB9,`
264			`LDA_IDX = 8'hA1,`
265			`LDA_IDY = 8'hB1;`
266			`LDX_IMM = 8'hA2,`
267			`LDX_ZPG = 8'hA6,`
268			`LDX_ZPY = 8'hB6,`
269			`LDX_ABS = 8'hAE,`
270			`LDX_ABY = 8'hBE;`
271			`LDY_IMM = 8'hA0,`
272			`LDY_ZPG = 8'hA4,`
273			`LDY_ZPX = 8'hB4,`
274			`LDY_ABS = 8'hAC,`
275			`LDY_ABX = 8'hBC;`
276			`*/`
277
278
279			`end`
280	63	creep	`end // no way`
281	61	creep	`endmodule`
282
283
284

Browse

Tools

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Blame information for rev 68