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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix absolute indexed mode                                        ////
//// - Code the relative mode                                           ////
//// - Code the indexed indirect mode                                   ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
        parameter DATA_SIZE = 4'd8;
        parameter ADDR_SIZE = 4'd13;
 
        input clk;
        input reset_n;
        input [DATA_SIZE-1:0] alu_result;
        input [DATA_SIZE-1:0] alu_status;
        input [DATA_SIZE-1:0] data_in;
        output reg [ADDR_SIZE-1:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE-1:0] data_out;
        output reg [DATA_SIZE-1:0] alu_opcode;
        output reg [DATA_SIZE-1:0] alu_a;
        output reg alu_enable;
 
 
        // FSM states
        localparam RESET = 4'b1111;
        localparam FETCH_OP = 4'b0000;
        localparam FETCH_OP_CALC = 4'b0001;
        localparam FETCH_LOW = 4'b0010;
        localparam FETCH_HIGH = 4'b0011;
        localparam READ_MEM = 4'b0100;
        localparam DUMMY_WRT_CALC = 4'b0101;
        localparam WRITE_MEM = 4'b0110;
        localparam FETCH_OP_CALC_PARAM = 4'b0111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE-1:0] pc;          // program counter
        reg [DATA_SIZE-1:0] sp;          // stack pointer
        reg [DATA_SIZE-1:0] ir;          // instruction register
        reg [ADDR_SIZE:0] temp_addr;     // temporary address
        reg [DATA_SIZE-1:0] temp_data;   // temporary data
 
        reg [3:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
        // wiring that simplifies the FSM logic
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirect;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
 
        wire [ADDR_SIZE-1:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
                        ir <= 0;
                        temp_addr <= 0;
                        temp_data <= 0;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 0;
                        control <= 0; // check if these 2 shouldnt be on the other always block along with the address
                        data_out <= 0;
                end
                else begin
                        state <= next_state;
                        control <= MEM_READ;
                        data_out = 8'hZ;
                        case (state)
                                RESET: begin
                                        // The processor was reset 
                                end
                                FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
                                                // the last cycle was a memory write.
                                        pc <= next_pc;
                                        address <= next_pc;
                                        ir <= data_in;
                                end
                                FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        ir <= data_in;
                                end
                                FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                        end
                                        else if (immediate) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                temp_addr[7:0] <= data_in;
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                end
                                        end
                                end
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr};
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                end
                                        end
                                        //else begin
                                        //      $write("FETCHHIGH PROBLEM"); 
                                        //      $finish(0); 
                                        //end
                                end
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                control <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                        end
                                end
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        control <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                end
                                default: begin
                                        $write("unknown state");        // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the output logic always block
                //control = MEM_READ; 
                //data_out = 8'h00;
 
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
                //address = pc;
 
                next_state = RESET; // this prevents the latch
 
                case (state)
                        RESET: begin
                                next_state = FETCH_OP;
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        FETCH_OP_CALC: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
 
                        end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                        end
                                        else begin
                                                $write("unknown behavior");
                                                $finish(0);
                                        end
                                end
                                else begin // at least the absolute address mode falls here
                                        next_state = FETCH_HIGH;
                                end
                        end
                        FETCH_HIGH: begin
                                if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirect = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
 
                case (ir)
                        BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                        PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                        end
                        BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
                                relative = 1'b1;
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
                        ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
                                indirect = 1'b1;
                        end
                        default: begin
                                $write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                $finish();
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
 
                if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
                        jump = 1'b1;
                end
        end // no way
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Fix absolute indexed mode ////`
13			`//// - Code the relative mode ////`
14			`//// - Code the indexed indirect mode ////`
15			`//// - Code the indirect indexed mode ////`
16			`//// - Code the absolute indirect mode ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
20			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
21			`//// ////`
22			`////////////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////////`
48
49			`timescale 1ns / 1ps
50
51	71	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);`
52	68	creep	`parameter DATA_SIZE = 4'd8;`
53			`parameter ADDR_SIZE = 4'd13;`
54
55	71	creep	`input clk;`
56			`input reset_n;`
57	68	creep	`input [DATA_SIZE-1:0] alu_result;`
58			`input [DATA_SIZE-1:0] alu_status;`
59			`input [DATA_SIZE-1:0] data_in;`
60			`output reg [ADDR_SIZE-1:0] address;`
61	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
62	68	creep	`output reg [DATA_SIZE-1:0] data_out;`
63			`output reg [DATA_SIZE-1:0] alu_opcode;`
64			`output reg [DATA_SIZE-1:0] alu_a;`
65			`output reg alu_enable;`
66	61	creep
67	68	creep
68	61	creep	`// FSM states`
69	68	creep	`localparam RESET = 4'b1111;`
70	63	creep	`localparam FETCH_OP = 4'b0000;`
71	68	creep	`localparam FETCH_OP_CALC = 4'b0001;`
72			`localparam FETCH_LOW = 4'b0010;`
73			`localparam FETCH_HIGH = 4'b0011;`
74	71	creep	`localparam READ_MEM = 4'b0100;`
75			`localparam DUMMY_WRT_CALC = 4'b0101;`
76			`localparam WRITE_MEM = 4'b0110;`
77			`localparam FETCH_OP_CALC_PARAM = 4'b0111;`
78	61	creep
79			`// OPCODES TODO: verify how this get synthesised`
80			`include "../T6507LP_Package.v"
81
82			`// control signals`
83			`localparam MEM_READ = 1'b0;`
84			`localparam MEM_WRITE = 1'b1;`
85
86	68	creep	`reg [ADDR_SIZE-1:0] pc; // program counter`
87			`reg [DATA_SIZE-1:0] sp; // stack pointer`
88			`reg [DATA_SIZE-1:0] ir; // instruction register`
89	71	creep	`reg [ADDR_SIZE:0] temp_addr; // temporary address`
90	68	creep	`reg [DATA_SIZE-1:0] temp_data; // temporary data`
91	61	creep
92			`reg [3:0] state, next_state; // current and next state registers`
93			`// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.`
94
95			`// wiring that simplifies the FSM logic`
96			`reg absolute;`
97			`reg absolute_indexed;`
98			`reg accumulator;`
99			`reg immediate;`
100			`reg implied;`
101			`reg indirect;`
102			`reg relative;`
103			`reg zero_page;`
104			`reg zero_page_indexed;`
105
106			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
107			`reg read;`
108			`reg read_modify_write;`
109			`reg write;`
110			`reg jump;`
111
112	68	creep	`wire [ADDR_SIZE-1:0] next_pc;`
113	63	creep	`assign next_pc = pc + 13'b0000000000001;`
114	61	creep
115	71	creep	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
116			`if (reset_n == 1'b0) begin`
117			`// all registers must assume default values`
118	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
119			`sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.`
120			`ir <= 0;`
121	71	creep	`temp_addr <= 0;`
122	68	creep	`temp_data <= 0;`
123			`state <= RESET;`
124	71	creep	`// registered outputs also receive default values`
125			`address <= 0;`
126			`control <= 0; // check if these 2 shouldnt be on the other always block along with the address`
127			`data_out <= 0;`
128	61	creep	`end`
129			`else begin`
130			`state <= next_state;`
131	71	creep	`control <= MEM_READ;`
132	77	creep	`data_out = 8'hZ;`
133	61	creep	`case (state)`
134	68	creep	`RESET: begin`
135			`// The processor was reset`
136			`end`
137	61	creep	`FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or`
138			`// the last cycle was a memory write.`
139			`pc <= next_pc;`
140	71	creep	`address <= next_pc;`
141	70	creep	`ir <= data_in;`
142	61	creep	`end`
143	71	creep	`FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
144	61	creep	`pc <= next_pc;`
145	71	creep	`address <= next_pc;`
146	70	creep	`ir <= data_in;`
147	61	creep	`end`
148	68	creep	`FETCH_LOW: begin // in this state the opcode is already known so truly execution begins`
149			`if (accumulator \|\| implied) begin`
150	70	creep	`pc <= pc; // is this better?`
151	71	creep	`address <= pc;`
152	61	creep	`end`
153	70	creep	`else if (immediate) begin`
154	68	creep	`pc <= next_pc;`
155	71	creep	`address <= next_pc;`
156	70	creep	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
157	61	creep	`end`
158	71	creep	`else if (absolute) begin`
159			`pc <= next_pc;`
160			`address <= next_pc;`
161			`temp_addr[7:0] <= data_in;`
162			`end`
163	77	creep	`else if (zero_page) begin`
164			`pc <= next_pc;`
165			`address <= {{5{1'b0}},data_in};`
166			`if (write) begin`
167			`control <= MEM_WRITE;`
168			`end`
169			`end`
170	61	creep	`end`
171	71	creep	`FETCH_HIGH: begin`
172			`if (jump) begin`
173			`pc <= {data_in[4:0], temp_addr}; // PCL <= first byte, PCH <= second byte`
174			`address <= {data_in[4:0], temp_addr};`
175			`end`
176			`else begin`
177			`if (write) begin`
178			`pc <= next_pc;`
179			`temp_addr[12:8] <= data_in[4:0];`
180			`address <= {data_in[4:0],temp_addr[7:0]};`
181			`control <= MEM_WRITE;`
182	77	creep	`data_out <= alu_result;`
183	71	creep	`end`
184			`else begin // read_modify_write or just read`
185			`pc <= next_pc;`
186			`temp_addr[12:8] <= data_in[4:0];`
187			`address <= {data_in[4:0],temp_addr[7:0]};`
188			`end`
189			`end`
190			`//else begin`
191			`// $write("FETCHHIGH PROBLEM");`
192			`// $finish(0);`
193			`//end`
194	61	creep	`end`
195	71	creep	`READ_MEM: begin`
196			`if (read_modify_write) begin`
197			`pc <= pc;`
198			`address <= temp_addr;`
199			`control <= MEM_WRITE;`
200			`temp_data <= data_in;`
201			`data_out <= data_in; // writeback the same value`
202			`end`
203			`else begin`
204			`pc <= pc;`
205			`address <= pc;`
206			`temp_data <= data_in;`
207			`end`
208	70	creep	`end`
209	71	creep	`DUMMY_WRT_CALC: begin`
210			`pc <= pc;`
211			`address <= temp_addr;`
212			`control <= MEM_WRITE;`
213			`data_out <= alu_result;`
214	70	creep	`end`
215	71	creep	`WRITE_MEM: begin`
216			`pc <= pc;`
217			`address <= pc;`
218	70	creep	`end`
219			`default: begin`
220			$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
221			`$finish(0);`
222			`end`
223
224			`endcase`
225			`end`
226			`end`
227
228	71	creep	`always @ (*) begin // this is the next_state logic and the output logic always block`
229	70	creep	`//control = MEM_READ;`
230			`//data_out = 8'h00;`
231	71	creep
232			`alu_opcode = 8'h00;`
233			`alu_a = 8'h00;`
234			`alu_enable = 1'b0;`
235			`//address = pc;`
236	70	creep
237	71	creep	`next_state = RESET; // this prevents the latch`
238	68	creep
239	71	creep	`case (state)`
240			`RESET: begin`
241			`next_state = FETCH_OP;`
242			`end`
243			`FETCH_OP: begin`
244			`next_state = FETCH_LOW;`
245			`end`
246			`FETCH_OP_CALC: begin`
247			`next_state = FETCH_LOW;`
248			`alu_opcode = ir;`
249			`alu_enable = 1'b1;`
250
251			`end`
252			`FETCH_OP_CALC_PARAM: begin`
253			`next_state = FETCH_LOW;`
254			`alu_opcode = ir;`
255			`alu_enable = 1'b1;`
256			`alu_a = temp_data;`
257			`end`
258			`FETCH_LOW: begin`
259			`if (accumulator \|\| implied) begin`
260			`alu_opcode = ir;`
261			`alu_enable = 1'b1;`
262			`next_state = FETCH_OP;`
263			`end`
264			`else if (immediate) begin`
265			`next_state = FETCH_OP_CALC_PARAM;`
266			`end`
267	77	creep	`else if (zero_page) begin`
268			`if (read \|\| read_modify_write) begin`
269			`next_state = READ_MEM;`
270			`end`
271			`else if (write) begin`
272			`next_state = WRITE_MEM;`
273			`end`
274			`else begin`
275			`$write("unknown behavior");`
276			`$finish(0);`
277			`end`
278			`end`
279	71	creep	`else begin // at least the absolute address mode falls here`
280			`next_state = FETCH_HIGH;`
281			`end`
282			`end`
283			`FETCH_HIGH: begin`
284			`if (jump) begin`
285	68	creep	`next_state = FETCH_OP;`
286	61	creep	`end`
287	71	creep	`else if (read \|\| read_modify_write) begin`
288			`next_state = READ_MEM;`
289	61	creep	`end`
290	71	creep	`else if (write) begin`
291			`next_state = WRITE_MEM;`
292	68	creep	`end`
293	71	creep	`else begin`
294			`$write("unknown behavior");`
295			`$finish(0);`
296	61	creep	`end`
297	71	creep	`end`
298			`READ_MEM: begin`
299			`if (read) begin`
300			`next_state = FETCH_OP_CALC_PARAM;`
301	61	creep	`end`
302	71	creep	`else if (read_modify_write) begin`
303			`next_state = DUMMY_WRT_CALC;`
304			`end`
305			`end`
306			`DUMMY_WRT_CALC: begin`
307			`alu_opcode = ir;`
308			`alu_enable = 1'b1;`
309			`alu_a = data_in;`
310			`next_state = WRITE_MEM;`
311			`end`
312			`WRITE_MEM: begin`
313			`next_state = FETCH_OP;`
314			`end`
315			`default: begin`
316			`next_state = RESET;`
317			`end`
318			`endcase`
319	61	creep	`end`
320
321	77	creep	`// this always block is responsible for updating the address mode and the type of operation being done`
322	68	creep	`always @ (*) begin //`
323	61	creep	`absolute = 1'b0;`
324			`absolute_indexed = 1'b0;`
325			`accumulator = 1'b0;`
326			`immediate = 1'b0;`
327			`implied = 1'b0;`
328			`indirect = 1'b0;`
329			`relative = 1'b0;`
330			`zero_page = 1'b0;`
331			`zero_page_indexed = 1'b0;`
332
333			`read = 1'b0;`
334			`read_modify_write = 1'b0;`
335			`write = 1'b0;`
336			`jump = 1'b0;`
337
338	70	creep	`case (ir)`
339			`BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,`
340			`PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin`
341			`implied = 1'b1;`
342			`end`
343			`ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin`
344			`accumulator = 1'b1;`
345			`end`
346			`ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin`
347			`immediate = 1'b1;`
348			`end`
349			`ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,`
350			`LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin`
351			`zero_page = 1'b1;`
352			`end`
353			`ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,`
354			`SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin`
355			`zero_page_indexed = 1'b1;`
356			`end`
357			`BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin`
358			`relative = 1'b1;`
359			`end`
360			`ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,`
361			`LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin`
362			`absolute = 1'b1;`
363			`end`
364			`ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,`
365			`SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin`
366			`absolute_indexed = 1'b1;`
367			`end`
368			`ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,`
369			`ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this`
370			`indirect = 1'b1;`
371			`end`
372	71	creep	`default: begin`
373	77	creep	`$write("\nunknown OPCODE!!!!! 0x%h\n", ir);`
374	71	creep	`$finish();`
375			`end`
376	70	creep	`endcase`
377	71	creep
378			`case (ir)`
379			`ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,`
380			`ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,`
381			`DEC_ABX: begin`
382			`read_modify_write = 1'b1;`
383			`end`
384			`STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin`
385			`write = 1'b1;`
386			`end`
387			`default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes`
388			`read = 1'b1;`
389			`end`
390			`endcase`
391	61	creep
392	71	creep	`if (ir == JMP_ABS \|\| ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C`
393	70	creep	`jump = 1'b1;`
394			`end`
395	63	creep	`end // no way`
396	61	creep	`endmodule`
397
398
399

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