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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix absolute indexed mode                                        ////
//// - Code the relative mode                                           ////
//// - Code the indexed indirect mode                                   ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
        parameter DATA_SIZE = 4'h8;
        parameter ADDR_SIZE = 4'hd;
 
        localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        input reset_n;
        input [DATA_SIZE_:0] alu_result;
        input [DATA_SIZE_:0] alu_status;
        input [DATA_SIZE_:0] data_in;
        output reg [ADDR_SIZE_:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;
        output reg [DATA_SIZE_:0] alu_opcode;
        output reg [DATA_SIZE_:0] alu_a;
        output reg alu_enable;
 
 
        // FSM states
        localparam RESET = 4'b1111;
        localparam FETCH_OP = 4'b0000;
        localparam FETCH_OP_CALC = 4'b0001;
        localparam FETCH_LOW = 4'b0010;
        localparam FETCH_HIGH = 4'b0011;
        localparam READ_MEM = 4'b0100;
        localparam DUMMY_WRT_CALC = 4'b0101;
        localparam WRITE_MEM = 4'b0110;
        localparam FETCH_OP_CALC_PARAM = 4'b0111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE_:0] pc;           // program counter
        reg [DATA_SIZE_:0] sp;           // stack pointer
        reg [DATA_SIZE_:0] ir;           // instruction register
        reg [ADDR_SIZE_:0] temp_addr;    // temporary address
        reg [DATA_SIZE_:0] temp_data;    // temporary data
 
        reg [3:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
        // wiring that simplifies the FSM logic
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirect;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
 
        wire [ADDR_SIZE_:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
                        ir <= 8'h00;
                        temp_addr <= 0;
                        temp_data <= 8'h00;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 0;
                        control <= MEM_READ;
                        data_out <= 8'h00;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin
                                        // The processor was reset
                                        $write("under reset");
                                end
                                FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
                                                // the last cycle was a memory write.
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                control <= MEM_READ;
                                        end
                                        else if (immediate) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_addr[7:0] <= data_in;
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                end
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        //else begin
                                        //      $write("FETCHHIGH PROBLEM"); 
                                        //      $finish(0); 
                                        //end
                                end
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                control <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                end
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        control <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                default: begin
                                        $write("unknown state");        // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the output logic always block
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
 
                next_state = RESET; // this prevents the latch
 
                case (state)
                        RESET: begin
                                next_state = FETCH_OP;
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        //FETCH_OP_CALC: begin // so far no addressing mode required the use of this state
                        //      next_state = FETCH_LOW;
                        //      alu_opcode = ir;
                        //      alu_enable = 1'b1;
                        //end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                        end
                                        else begin
                                                $write("unknown behavior");
                                                $finish(0);
                                        end
                                end
                                else begin // at least the absolute address mode falls here
                                        next_state = FETCH_HIGH;
                                end
 
                                if (write) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        alu_a = 8'h00;
                                end
 
 
                        end
                        FETCH_HIGH: begin
                                if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirect = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
 
                case (ir)
                        BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                        PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                        end
                        BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
                                relative = 1'b1;
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
                        ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
                                indirect = 1'b1;
                        end
                        default: begin
                                $write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                $finish();
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
 
                if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
                        jump = 1'b1;
                end
        end // no way
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Fix absolute indexed mode ////`
13			`//// - Code the relative mode ////`
14			`//// - Code the indexed indirect mode ////`
15			`//// - Code the indirect indexed mode ////`
16			`//// - Code the absolute indirect mode ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
20			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
21			`//// ////`
22			`////////////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////////`
48
49			`timescale 1ns / 1ps
50
51	71	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);`
52	82	creep	`parameter DATA_SIZE = 4'h8;`
53			`parameter ADDR_SIZE = 4'hd;`
54	68	creep
55	83	creep	`localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;`
56			`localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
57	82	creep
58	71	creep	`input clk;`
59			`input reset_n;`
60	82	creep	`input [DATA_SIZE_:0] alu_result;`
61			`input [DATA_SIZE_:0] alu_status;`
62			`input [DATA_SIZE_:0] data_in;`
63			`output reg [ADDR_SIZE_:0] address;`
64	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
65	82	creep	`output reg [DATA_SIZE_:0] data_out;`
66			`output reg [DATA_SIZE_:0] alu_opcode;`
67			`output reg [DATA_SIZE_:0] alu_a;`
68	68	creep	`output reg alu_enable;`
69	61	creep
70	68	creep
71	61	creep	`// FSM states`
72	68	creep	`localparam RESET = 4'b1111;`
73	63	creep	`localparam FETCH_OP = 4'b0000;`
74	68	creep	`localparam FETCH_OP_CALC = 4'b0001;`
75			`localparam FETCH_LOW = 4'b0010;`
76			`localparam FETCH_HIGH = 4'b0011;`
77	71	creep	`localparam READ_MEM = 4'b0100;`
78			`localparam DUMMY_WRT_CALC = 4'b0101;`
79			`localparam WRITE_MEM = 4'b0110;`
80			`localparam FETCH_OP_CALC_PARAM = 4'b0111;`
81	61	creep
82			`// OPCODES TODO: verify how this get synthesised`
83			`include "../T6507LP_Package.v"
84
85			`// control signals`
86			`localparam MEM_READ = 1'b0;`
87			`localparam MEM_WRITE = 1'b1;`
88
89	82	creep	`reg [ADDR_SIZE_:0] pc; // program counter`
90			`reg [DATA_SIZE_:0] sp; // stack pointer`
91			`reg [DATA_SIZE_:0] ir; // instruction register`
92			`reg [ADDR_SIZE_:0] temp_addr; // temporary address`
93			`reg [DATA_SIZE_:0] temp_data; // temporary data`
94	61	creep
95			`reg [3:0] state, next_state; // current and next state registers`
96			`// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.`
97
98			`// wiring that simplifies the FSM logic`
99			`reg absolute;`
100			`reg absolute_indexed;`
101			`reg accumulator;`
102			`reg immediate;`
103			`reg implied;`
104			`reg indirect;`
105			`reg relative;`
106			`reg zero_page;`
107			`reg zero_page_indexed;`
108
109			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
110			`reg read;`
111			`reg read_modify_write;`
112			`reg write;`
113			`reg jump;`
114
115	82	creep	`wire [ADDR_SIZE_:0] next_pc;`
116	63	creep	`assign next_pc = pc + 13'b0000000000001;`
117	61	creep
118	71	creep	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
119			`if (reset_n == 1'b0) begin`
120			`// all registers must assume default values`
121	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
122			`sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.`
123	82	creep	`ir <= 8'h00;`
124	71	creep	`temp_addr <= 0;`
125	82	creep	`temp_data <= 8'h00;`
126	68	creep	`state <= RESET;`
127	71	creep	`// registered outputs also receive default values`
128			`address <= 0;`
129	82	creep	`control <= MEM_READ;`
130			`data_out <= 8'h00;`
131	61	creep	`end`
132			`else begin`
133			`state <= next_state;`
134	83	creep
135	61	creep	`case (state)`
136	68	creep	`RESET: begin`
137	82	creep	`// The processor was reset`
138			`$write("under reset");`
139	68	creep	`end`
140	61	creep	`FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or`
141			`// the last cycle was a memory write.`
142			`pc <= next_pc;`
143	71	creep	`address <= next_pc;`
144	83	creep	`control <= MEM_READ;`
145	70	creep	`ir <= data_in;`
146	61	creep	`end`
147	71	creep	`FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
148	61	creep	`pc <= next_pc;`
149	71	creep	`address <= next_pc;`
150	83	creep	`control <= MEM_READ;`
151	70	creep	`ir <= data_in;`
152	61	creep	`end`
153	68	creep	`FETCH_LOW: begin // in this state the opcode is already known so truly execution begins`
154			`if (accumulator \|\| implied) begin`
155	70	creep	`pc <= pc; // is this better?`
156	71	creep	`address <= pc;`
157	83	creep	`control <= MEM_READ;`
158	61	creep	`end`
159	70	creep	`else if (immediate) begin`
160	68	creep	`pc <= next_pc;`
161	71	creep	`address <= next_pc;`
162	83	creep	`control <= MEM_READ;`
163	70	creep	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
164	61	creep	`end`
165	71	creep	`else if (absolute) begin`
166			`pc <= next_pc;`
167			`address <= next_pc;`
168	83	creep	`control <= MEM_READ;`
169	71	creep	`temp_addr[7:0] <= data_in;`
170			`end`
171	77	creep	`else if (zero_page) begin`
172			`pc <= next_pc;`
173			`address <= {{5{1'b0}},data_in};`
174	78	creep	`temp_addr <= {{5{1'b0}},data_in};`
175
176	77	creep	`if (write) begin`
177			`control <= MEM_WRITE;`
178	78	creep	`data_out <= alu_result;`
179	77	creep	`end`
180	83	creep	`else begin`
181			`control <= MEM_READ;`
182			`data_out <= 8'h00;`
183			`end`
184	77	creep	`end`
185	61	creep	`end`
186	71	creep	`FETCH_HIGH: begin`
187			`if (jump) begin`
188	83	creep	`pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte`
189			`address <= {data_in[4:0], temp_addr[7:0]};`
190			`control <= MEM_READ;`
191			`data_out <= 8'h00;`
192	71	creep	`end`
193			`else begin`
194			`if (write) begin`
195			`pc <= next_pc;`
196			`temp_addr[12:8] <= data_in[4:0];`
197			`address <= {data_in[4:0],temp_addr[7:0]};`
198			`control <= MEM_WRITE;`
199	77	creep	`data_out <= alu_result;`
200	71	creep	`end`
201			`else begin // read_modify_write or just read`
202			`pc <= next_pc;`
203			`temp_addr[12:8] <= data_in[4:0];`
204			`address <= {data_in[4:0],temp_addr[7:0]};`
205	83	creep	`control <= MEM_READ;`
206			`data_out <= 8'h00;`
207	71	creep	`end`
208			`end`
209			`//else begin`
210			`// $write("FETCHHIGH PROBLEM");`
211			`// $finish(0);`
212			`//end`
213	61	creep	`end`
214	71	creep	`READ_MEM: begin`
215			`if (read_modify_write) begin`
216			`pc <= pc;`
217			`address <= temp_addr;`
218			`control <= MEM_WRITE;`
219			`temp_data <= data_in;`
220			`data_out <= data_in; // writeback the same value`
221			`end`
222			`else begin`
223			`pc <= pc;`
224			`address <= pc;`
225			`temp_data <= data_in;`
226	83	creep	`control <= MEM_READ;`
227			`data_out <= 8'h00;`
228	71	creep	`end`
229	70	creep	`end`
230	71	creep	`DUMMY_WRT_CALC: begin`
231			`pc <= pc;`
232			`address <= temp_addr;`
233			`control <= MEM_WRITE;`
234			`data_out <= alu_result;`
235	70	creep	`end`
236	71	creep	`WRITE_MEM: begin`
237			`pc <= pc;`
238			`address <= pc;`
239	83	creep	`control <= MEM_READ;`
240			`data_out <= 8'h00;`
241	70	creep	`end`
242			`default: begin`
243			$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
244			`$finish(0);`
245			`end`
246
247			`endcase`
248			`end`
249			`end`
250
251	71	creep	`always @ (*) begin // this is the next_state logic and the output logic always block`
252			`alu_opcode = 8'h00;`
253			`alu_a = 8'h00;`
254			`alu_enable = 1'b0;`
255	70	creep
256	71	creep	`next_state = RESET; // this prevents the latch`
257	68	creep
258	71	creep	`case (state)`
259			`RESET: begin`
260			`next_state = FETCH_OP;`
261			`end`
262			`FETCH_OP: begin`
263			`next_state = FETCH_LOW;`
264			`end`
265	82	creep	`//FETCH_OP_CALC: begin // so far no addressing mode required the use of this state`
266			`// next_state = FETCH_LOW;`
267			`// alu_opcode = ir;`
268			`// alu_enable = 1'b1;`
269			`//end`
270	71	creep	`FETCH_OP_CALC_PARAM: begin`
271			`next_state = FETCH_LOW;`
272			`alu_opcode = ir;`
273			`alu_enable = 1'b1;`
274			`alu_a = temp_data;`
275			`end`
276			`FETCH_LOW: begin`
277			`if (accumulator \|\| implied) begin`
278			`alu_opcode = ir;`
279			`alu_enable = 1'b1;`
280			`next_state = FETCH_OP;`
281			`end`
282			`else if (immediate) begin`
283			`next_state = FETCH_OP_CALC_PARAM;`
284			`end`
285	77	creep	`else if (zero_page) begin`
286			`if (read \|\| read_modify_write) begin`
287			`next_state = READ_MEM;`
288			`end`
289			`else if (write) begin`
290			`next_state = WRITE_MEM;`
291			`end`
292			`else begin`
293			`$write("unknown behavior");`
294			`$finish(0);`
295			`end`
296			`end`
297	71	creep	`else begin // at least the absolute address mode falls here`
298			`next_state = FETCH_HIGH;`
299			`end`
300	78	creep
301			`if (write) begin`
302			`alu_opcode = ir;`
303			`alu_enable = 1'b1;`
304	82	creep	`alu_a = 8'h00;`
305	78	creep	`end`
306
307
308	71	creep	`end`
309			`FETCH_HIGH: begin`
310			`if (jump) begin`
311	68	creep	`next_state = FETCH_OP;`
312	61	creep	`end`
313	71	creep	`else if (read \|\| read_modify_write) begin`
314			`next_state = READ_MEM;`
315	61	creep	`end`
316	71	creep	`else if (write) begin`
317			`next_state = WRITE_MEM;`
318	68	creep	`end`
319	71	creep	`else begin`
320			`$write("unknown behavior");`
321			`$finish(0);`
322	61	creep	`end`
323	71	creep	`end`
324			`READ_MEM: begin`
325			`if (read) begin`
326			`next_state = FETCH_OP_CALC_PARAM;`
327	61	creep	`end`
328	71	creep	`else if (read_modify_write) begin`
329			`next_state = DUMMY_WRT_CALC;`
330			`end`
331			`end`
332			`DUMMY_WRT_CALC: begin`
333			`alu_opcode = ir;`
334			`alu_enable = 1'b1;`
335			`alu_a = data_in;`
336			`next_state = WRITE_MEM;`
337			`end`
338			`WRITE_MEM: begin`
339			`next_state = FETCH_OP;`
340			`end`
341			`default: begin`
342			`next_state = RESET;`
343			`end`
344			`endcase`
345	61	creep	`end`
346
347	77	creep	`// this always block is responsible for updating the address mode and the type of operation being done`
348	68	creep	`always @ (*) begin //`
349	61	creep	`absolute = 1'b0;`
350			`absolute_indexed = 1'b0;`
351			`accumulator = 1'b0;`
352			`immediate = 1'b0;`
353			`implied = 1'b0;`
354			`indirect = 1'b0;`
355			`relative = 1'b0;`
356			`zero_page = 1'b0;`
357			`zero_page_indexed = 1'b0;`
358
359			`read = 1'b0;`
360			`read_modify_write = 1'b0;`
361			`write = 1'b0;`
362			`jump = 1'b0;`
363
364	70	creep	`case (ir)`
365			`BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,`
366			`PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin`
367			`implied = 1'b1;`
368			`end`
369			`ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin`
370			`accumulator = 1'b1;`
371			`end`
372			`ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin`
373			`immediate = 1'b1;`
374			`end`
375			`ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,`
376			`LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin`
377			`zero_page = 1'b1;`
378			`end`
379			`ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,`
380			`SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin`
381			`zero_page_indexed = 1'b1;`
382			`end`
383			`BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin`
384			`relative = 1'b1;`
385			`end`
386			`ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,`
387			`LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin`
388			`absolute = 1'b1;`
389			`end`
390			`ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,`
391			`SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin`
392			`absolute_indexed = 1'b1;`
393			`end`
394			`ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,`
395			`ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this`
396			`indirect = 1'b1;`
397			`end`
398	71	creep	`default: begin`
399	77	creep	`$write("\nunknown OPCODE!!!!! 0x%h\n", ir);`
400	71	creep	`$finish();`
401			`end`
402	70	creep	`endcase`
403	71	creep
404			`case (ir)`
405			`ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,`
406			`ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,`
407			`DEC_ABX: begin`
408			`read_modify_write = 1'b1;`
409			`end`
410			`STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin`
411			`write = 1'b1;`
412			`end`
413			`default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes`
414			`read = 1'b1;`
415			`end`
416			`endcase`
417	61	creep
418	71	creep	`if (ir == JMP_ABS \|\| ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C`
419	70	creep	`jump = 1'b1;`
420			`end`
421	63	creep	`end // no way`
422	61	creep	`endmodule`
423
424
425

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