OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_io.v] - Blame information for rev 251

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 251 creep
////////////////////////////////////////////////////////////////////////////
2
////                                                                    ////
3
//// T6507LP IP Core                                                    ////
4
////                                                                    ////
5
//// This file is part of the T6507LP project                           ////
6
//// http://www.opencores.org/cores/t6507lp/                            ////
7
////                                                                    ////
8
//// Description                                                        ////
9
//// 6507 io wrapper                                                    ////
10
////                                                                    ////
11
//// TODO:                                                              ////
12
//// - Nothing                                                          ////
13
////                                                                    ////
14
//// Author(s):                                                         ////
15
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
16
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
17
////                                                                    ////
18
////////////////////////////////////////////////////////////////////////////
19
////                                                                    ////
20
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
21
////                                                                    ////
22
//// This source file may be used and distributed without               ////
23
//// restriction provided that this copyright statement is not          ////
24
//// removed from the file and that any derivative work contains        ////
25
//// the original copyright notice and the associated disclaimer.       ////
26
////                                                                    ////
27
//// This source file is free software; you can redistribute it         ////
28
//// and/or modify it under the terms of the GNU Lesser General         ////
29
//// Public License as published by the Free Software Foundation;       ////
30
//// either version 2.1 of the License, or (at your option) any         ////
31
//// later version.                                                     ////
32
////                                                                    ////
33
//// This source is distributed in the hope that it will be             ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
36
//// PURPOSE. See the GNU Lesser General Public License for more        ////
37
//// details.                                                           ////
38
////                                                                    ////
39
//// You should have received a copy of the GNU Lesser General          ////
40
//// Public License along with this source; if not, download it         ////
41
//// from http://www.opencores.org/lgpl.shtml                           ////
42
////                                                                    ////
43
////////////////////////////////////////////////////////////////////////////
44
 
45
`include "timescale.v"
46
 
47
module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);
48
        parameter [3:0] DATA_SIZE = 4'd8;
49
        parameter [3:0] ADDR_SIZE = 4'd13;
50
 
51
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
52
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
53
 
54
        input                 clk;
55
        input                 reset_n;
56
        input  [DATA_SIZE_:0] data_in;
57
        output                rw_mem;
58
        output [DATA_SIZE_:0] data_out;
59
        output [ADDR_SIZE_:0] address;
60
 
61
        t6507lp #(DATA_SIZE, ADDR_SIZE) t6507lp(
62
                .clk            (clk),
63
                .reset_n        (reset_n),
64
                .data_in        (data_in),
65
                .address        (address),
66
                .rw_mem         (rw_mem),
67
                .data_out       (data_out)
68
        );
69
 
70
endmodule
71
 
72
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.