Subversion Repositories t6507lp

////////////////////////////////////////////////////////////////////////////

////                                                                    ////

//// T6507LP IP Core                                                    ////

////                                                                    ////

//// This file is part of the T6507LP project                           ////

//// http://www.opencores.org/cores/t6507lp/                            ////

////                                                                    ////

//// Description                                                        ////

//// 6507 io wrapper                                                    ////

////                                                                    ////

//// TODO:                                                              ////

//// - Nothing                                                          ////

////                                                                    ////

//// Author(s):                                                         ////

//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////

//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////

////                                                                    ////

////////////////////////////////////////////////////////////////////////////

////                                                                    ////

//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////

////                                                                    ////

//// This source file may be used and distributed without               ////

//// restriction provided that this copyright statement is not          ////

//// removed from the file and that any derivative work contains        ////

//// the original copyright notice and the associated disclaimer.       ////

////                                                                    ////

//// This source file is free software; you can redistribute it         ////

//// and/or modify it under the terms of the GNU Lesser General         ////

//// Public License as published by the Free Software Foundation;       ////

//// either version 2.1 of the License, or (at your option) any         ////

//// later version.                                                     ////

////                                                                    ////

//// This source is distributed in the hope that it will be             ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////

//// PURPOSE. See the GNU Lesser General Public License for more        ////

//// details.                                                           ////

////                                                                    ////

//// You should have received a copy of the GNU Lesser General          ////

//// Public License along with this source; if not, download it         ////

//// from http://www.opencores.org/lgpl.shtml                           ////

////                                                                    ////

////////////////////////////////////////////////////////////////////////////

`include "timescale.v"

module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);

        parameter [3:0] DATA_SIZE = 4'd8;

        parameter [3:0] ADDR_SIZE = 4'd13;

        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;

        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;

        input                 clk;

        input                 reset_n;

        input  [DATA_SIZE_:0] data_in;

        output                rw_mem;

        output [DATA_SIZE_:0] data_out;

        output [ADDR_SIZE_:0] address;

        t6507lp #(DATA_SIZE, ADDR_SIZE) t6507lp(

                .clk            (clk),

                .reset_n        (reset_n),

                .data_in        (data_in),

                .address        (address),

                .rw_mem         (rw_mem),

                .data_out       (data_out)

        );

endmodule