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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t6507 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t6507 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// I/O wrapper for the 6507 processor                                 ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "stubs.v"
module t6507lp_io(clk, reset_n, scan_enable, data_in, rw_mem, data_out, address);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd13;
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        wire clkIO;
 
        input reset_n;
        wire reset_nIO;
 
        input scan_enable;
        wire scan_enableIO;
 
        input [DATA_SIZE_:0] data_in;
        reg [DATA_SIZE_:0] data_inIO;
 
        output rw_mem;
        wire rw_memIO;
 
        output [DATA_SIZE_:0] data_out;
        reg [DATA_SIZE_:0] data_outIO;
 
        output [ADDR_SIZE_:0] address;
        reg [ADDR_SIZE_:0] addressIO;
 
        wire pipo0, pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, pipo10, chainfinal;
 
        wire muxed;
 
        t6507lp t6507lp(  //core
                .clk            (clkIO),
                .reset_n        (reset_nIO),
                .data_in        (data_inIO),
                .rw_mem         (rw_memIO),
                .data_out       (data_outIO),
                .address        (addressIO)
        );
 
        wire vdd, gnd, dummy_clampc;
 
        ICP scan_pad(
                .PAD    (scan_enable),
                .PI     (pipo10),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (chain_final),
                .Y      (scan_enableIO)
        );
 
/*      ICP test_pad(
                .PAD    (pintest),
                .PI     (1'b1),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo0),
                .Y      (pintestIO)
        );
*/
        ICP clk_pad(
                .PAD    (clk),
                .PI     (pipo9),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo10),
                .Y      (clkIO)
        );
 
        ICP reset_n_pad(
                .PAD    (reset_n),
                .PI     (pipo8),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo9),
                .Y      (reset_nIO)
        );
 
        ICP data_in_pad0(
                .PAD    (data_in[0]),
                .PI     (pipo7),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo8),
                .Y      (data_inIO[0])
        );
 
        ICP data_in_pad1(
                .PAD    (data_in[1]),
                .PI     (pipo6),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo7),
                .Y      (data_inIO[1])
        );
 
        ICP data_in_pad2(
                .PAD    (data_in[2]),
                .PI     (pipo5),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo6),
                .Y      (data_inIO[2])
        );
 
        ICP data_in_pad3(
                .PAD    (data_in[3]),
                .PI     (pipo4),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo5),
                .Y      (data_inIO[3])
        );
 
        ICP data_in_pad4(
                .PAD    (data_in[4]),
                .PI     (pipo3),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo4),
                .Y      (data_inIO[4])
        );
 
        ICP data_in_pad5(
                .PAD    (data_in[5]),
                .PI     (pipo2),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo3),
                .Y      (data_inIO[5])
        );
 
        ICP data_in_pad6(
                .PAD    (data_in[6]),
                .PI     (pipo1),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo2),
                .Y      (data_inIO[6])
        );
 
        ICP data_in_pad7(
                .PAD    (data_in[7]),
                .PI     (pipo0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo1),
                .Y      (data_inIO[7])
        );
 
        BT4P rw_mem_pad(
                .A      (muxed),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (rw_mem)
        );
 
        BT4P data_out_pad0(
                .A      (data_outIO[0]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[0])
        );
 
        BT4P data_out_pad1(
                .A      (data_outIO[1]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[1])
        );
 
        BT4P data_out_pad2(
                .A      (data_outIO[2]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[2])
        );
 
        BT4P data_out_pad3(
                .A      (data_outIO[3]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[3])
        );
 
        BT4P data_out_pad4(
                .A      (data_outIO[4]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[4])
        );
 
        BT4P data_out_pad5(
                .A      (data_outIO[5]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[5])
        );
 
        BT4P data_out_pad6(
                .A      (data_outIO[6]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[6])
        );
 
        BT4P data_out_pad7(
                .A      (data_outIO[7]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[7])
        );
 
        BT4P address_pad0(
                .A      (addressIO[0]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[0])
        );
 
        BT4P address_pad1(
                .A      (addressIO[1]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[1])
        );
        BT4P address_pad2(
                .A      (addressIO[2]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[2])
        );
        BT4P address_pad3(
                .A      (addressIO[3]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[3])
        );
        BT4P address_pad4(
                .A      (addressIO[4]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[4])
        );
        BT4P address_pad5(
                .A      (addressIO[5]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[5])
        );
        BT4P address_pad6(
                .A      (addressIO[6]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[6])
        );
        BT4P address_pad7(
                .A      (addressIO[7]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[7])
        );
        BT4P address_pad8(
                .A      (addressIO[8]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[8])
        );
        BT4P address_pad9(
                .A      (addressIO[9]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[9])
        );
        BT4P address_pad10(
                .A      (addressIO[10]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[10])
        );
        BT4P address_pad11(
                .A      (addressIO[11]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[11])
        );
 
        BT4P address_pad12(
                .A      (addressIO[12]),
                .EN     (1'b0),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[12])
        );
 
        CORNERCLMP left_up_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
 
        CORNERCLMP left_down_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
 
        CORNERCLMP right_up_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
 
        CORNERCLMP right_down_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
 
        GND5ALLPADP gnd_pad_left (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND    (gnd)
        );
 
        GND5ALLPADP gnd_pad_right (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND    (gnd)
        );
 
        GND5ALLPADP gnd_pad_up (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND    (gnd)
        );
 
        GND5ALLPADP gnd_pad_down (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND    (gnd)
        );
 
        VDD5ALLPADP vdd_pad_left (
                .CLAMPC (dummy_clampc),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD    (vdd)
        );
 
        VDD5ALLPADP vdd_pad_right (
                .CLAMPC (dummy_clampc),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD    (vdd)
        );
 
        VDD5ALLPADP vdd_pad_up (
                .CLAMPC (dummy_clampc),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD    (vdd)
        );
 
        VDD5ALLPADP vdd_pad_down (
                .CLAMPC (dummy_clampc),
                .GND5O  (gnd),
                .GND5R  (gnd),
                .VDD    (vdd)
        );
 
        assign muxed = (reset_nIO == 1'b1) ? chainfinal : rw_memIO;
 
 
/*      FILLERP_110 filler0 (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
 
        FILLERP_110 filler1 (
                .CLAMPC (dummy_clampc),
                .VDD5O  (vdd),
                .VDD5R  (vdd),
                .GND5O  (gnd),
                .GND5R  (gnd)
        );
*/
endmodule

Line No.	Rev	Author	Line
1	251	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	255	creep	`//// t6507 IP Core ////`
4	251	creep	`//// ////`
5	255	creep	`//// This file is part of the t6507 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7	251	creep	`//// ////`
8			`//// Description ////`
9	255	creep	`//// I/O wrapper for the 6507 processor ////`
10	251	creep	`//// ////`
11			`//// Author(s): ////`
12			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
13			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
14			`//// ////`
15			`////////////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`////////////////////////////////////////////////////////////////////////////`
41
42			`include "timescale.v"
43	252	creep	`include "stubs.v"
44	258	creep	`module t6507lp_io(clk, reset_n, scan_enable, data_in, rw_mem, data_out, address);`
45	251	creep	`parameter [3:0] DATA_SIZE = 4'd8;`
46			`parameter [3:0] ADDR_SIZE = 4'd13;`
47
48			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;`
49			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
50
51	252	creep	`input clk;`
52	255	creep	`wire clkIO;`
53	252	creep
54			`input reset_n;`
55	255	creep	`wire reset_nIO;`
56	252	creep
57	258	creep	`input scan_enable;`
58			`wire scan_enableIO;`
59
60	252	creep	`input [DATA_SIZE_:0] data_in;`
61	255	creep	`reg [DATA_SIZE_:0] data_inIO;`
62	252	creep
63	255	creep	`output rw_mem;`
64			`wire rw_memIO;`
65	252	creep
66	255	creep	`output [DATA_SIZE_:0] data_out;`
67			`reg [DATA_SIZE_:0] data_outIO;`
68	252	creep
69	255	creep	`output [ADDR_SIZE_:0] address;`
70			`reg [ADDR_SIZE_:0] addressIO;`
71	252	creep
72	258	creep	`wire pipo0, pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, pipo10, chainfinal;`
73	255	creep
74			`wire muxed;`
75
76			`t6507lp t6507lp( //core`
77			`.clk (clkIO),`
78			`.reset_n (reset_nIO),`
79			`.data_in (data_inIO),`
80			`.rw_mem (rw_memIO),`
81			`.data_out (data_outIO),`
82			`.address (addressIO)`
83			`);`
84
85	258	creep	`wire vdd, gnd, dummy_clampc;`
86	255	creep
87	258	creep	`ICP scan_pad(`
88			`.PAD (scan_enable),`
89			`.PI (pipo10),`
90			`.GND5O (gnd),`
91			`.GND5R (gnd),`
92			`.VDD5O (vdd),`
93			`.VDD5R (vdd),`
94			`.CLAMPC (dummy_clampc),`
95			`.PO (chain_final),`
96			`.Y (scan_enableIO)`
97			`);`
98	255	creep
99	258	creep	`/* ICP test_pad(`
100			`.PAD (pintest),`
101			`.PI (1'b1),`
102			`.GND5O (gnd),`
103			`.GND5R (gnd),`
104			`.VDD5O (vdd),`
105			`.VDD5R (vdd),`
106			`.CLAMPC (dummy_clampc),`
107			`.PO (pipo0),`
108			`.Y (pintestIO)`
109			`);`
110			`*/`
111	252	creep	`ICP clk_pad(`
112	255	creep	`.PAD (clk),`
113			`.PI (pipo9),`
114	258	creep	`.GND5O (gnd),`
115			`.GND5R (gnd),`
116			`.VDD5O (vdd),`
117			`.VDD5R (vdd),`
118	255	creep	`.CLAMPC (dummy_clampc),`
119	258	creep	`.PO (pipo10),`
120	252	creep	`.Y (clkIO)`
121	251	creep	`);`
122
123	252	creep	`ICP reset_n_pad(`
124	255	creep	`.PAD (reset_n),`
125			`.PI (pipo8),`
126	258	creep	`.GND5O (gnd),`
127			`.GND5R (gnd),`
128			`.VDD5O (vdd),`
129			`.VDD5R (vdd),`
130	255	creep	`.CLAMPC (dummy_clampc),`
131			`.PO (pipo9),`
132	252	creep	`.Y (reset_nIO)`
133			`);`
134
135			`ICP data_in_pad0(`
136	255	creep	`.PAD (data_in[0]),`
137			`.PI (pipo7),`
138	258	creep	`.GND5O (gnd),`
139			`.GND5R (gnd),`
140			`.VDD5O (vdd),`
141			`.VDD5R (vdd),`
142	255	creep	`.CLAMPC (dummy_clampc),`
143			`.PO (pipo8),`
144	252	creep	`.Y (data_inIO[0])`
145			`);`
146
147			`ICP data_in_pad1(`
148	255	creep	`.PAD (data_in[1]),`
149			`.PI (pipo6),`
150	258	creep	`.GND5O (gnd),`
151			`.GND5R (gnd),`
152			`.VDD5O (vdd),`
153			`.VDD5R (vdd),`
154	255	creep	`.CLAMPC (dummy_clampc),`
155			`.PO (pipo7),`
156	252	creep	`.Y (data_inIO[1])`
157			`);`
158
159			`ICP data_in_pad2(`
160	255	creep	`.PAD (data_in[2]),`
161			`.PI (pipo5),`
162	258	creep	`.GND5O (gnd),`
163			`.GND5R (gnd),`
164			`.VDD5O (vdd),`
165			`.VDD5R (vdd),`
166	255	creep	`.CLAMPC (dummy_clampc),`
167			`.PO (pipo6),`
168	252	creep	`.Y (data_inIO[2])`
169			`);`
170
171			`ICP data_in_pad3(`
172	255	creep	`.PAD (data_in[3]),`
173			`.PI (pipo4),`
174	258	creep	`.GND5O (gnd),`
175			`.GND5R (gnd),`
176			`.VDD5O (vdd),`
177			`.VDD5R (vdd),`
178	255	creep	`.CLAMPC (dummy_clampc),`
179			`.PO (pipo5),`
180	252	creep	`.Y (data_inIO[3])`
181			`);`
182
183			`ICP data_in_pad4(`
184	255	creep	`.PAD (data_in[4]),`
185			`.PI (pipo3),`
186	258	creep	`.GND5O (gnd),`
187			`.GND5R (gnd),`
188			`.VDD5O (vdd),`
189			`.VDD5R (vdd),`
190	255	creep	`.CLAMPC (dummy_clampc),`
191			`.PO (pipo4),`
192	252	creep	`.Y (data_inIO[4])`
193			`);`
194
195			`ICP data_in_pad5(`
196	255	creep	`.PAD (data_in[5]),`
197			`.PI (pipo2),`
198	258	creep	`.GND5O (gnd),`
199			`.GND5R (gnd),`
200			`.VDD5O (vdd),`
201			`.VDD5R (vdd),`
202	255	creep	`.CLAMPC (dummy_clampc),`
203			`.PO (pipo3),`
204	252	creep	`.Y (data_inIO[5])`
205			`);`
206
207			`ICP data_in_pad6(`
208	255	creep	`.PAD (data_in[6]),`
209			`.PI (pipo1),`
210	258	creep	`.GND5O (gnd),`
211			`.GND5R (gnd),`
212			`.VDD5O (vdd),`
213			`.VDD5R (vdd),`
214	255	creep	`.CLAMPC (dummy_clampc),`
215			`.PO (pipo2),`
216	252	creep	`.Y (data_inIO[6])`
217			`);`
218
219			`ICP data_in_pad7(`
220	255	creep	`.PAD (data_in[7]),`
221	258	creep	`.PI (pipo0),`
222			`.GND5O (gnd),`
223			`.GND5R (gnd),`
224			`.VDD5O (vdd),`
225			`.VDD5R (vdd),`
226	255	creep	`.CLAMPC (dummy_clampc),`
227			`.PO (pipo1),`
228	252	creep	`.Y (data_inIO[7])`
229			`);`
230
231	255	creep	`BT4P rw_mem_pad(`
232			`.A (muxed),`
233	258	creep	`.EN (1'b0),`
234			`.GND5O (gnd),`
235			`.GND5R (gnd),`
236			`.VDD5O (vdd),`
237			`.VDD5R (vdd),`
238	255	creep	`.CLAMPC (dummy_clampc),`
239			`.PAD (rw_mem)`
240	252	creep	`);`
241
242	255	creep	`BT4P data_out_pad0(`
243			`.A (data_outIO[0]),`
244	258	creep	`.EN (1'b0),`
245			`.GND5O (gnd),`
246			`.GND5R (gnd),`
247			`.VDD5O (vdd),`
248			`.VDD5R (vdd),`
249	255	creep	`.CLAMPC (dummy_clampc),`
250			`.PAD (data_out[0])`
251	252	creep	`);`
252
253	255	creep	`BT4P data_out_pad1(`
254			`.A (data_outIO[1]),`
255	258	creep	`.EN (1'b0),`
256			`.GND5O (gnd),`
257			`.GND5R (gnd),`
258			`.VDD5O (vdd),`
259			`.VDD5R (vdd),`
260	255	creep	`.CLAMPC (dummy_clampc),`
261			`.PAD (data_out[1])`
262	252	creep	`);`
263
264	255	creep	`BT4P data_out_pad2(`
265			`.A (data_outIO[2]),`
266	258	creep	`.EN (1'b0),`
267			`.GND5O (gnd),`
268			`.GND5R (gnd),`
269			`.VDD5O (vdd),`
270			`.VDD5R (vdd),`
271	255	creep	`.CLAMPC (dummy_clampc),`
272			`.PAD (data_out[2])`
273	252	creep	`);`
274
275	255	creep	`BT4P data_out_pad3(`
276			`.A (data_outIO[3]),`
277	258	creep	`.EN (1'b0),`
278			`.GND5O (gnd),`
279			`.GND5R (gnd),`
280			`.VDD5O (vdd),`
281			`.VDD5R (vdd),`
282	255	creep	`.CLAMPC (dummy_clampc),`
283			`.PAD (data_out[3])`
284	252	creep	`);`
285
286	255	creep	`BT4P data_out_pad4(`
287			`.A (data_outIO[4]),`
288	258	creep	`.EN (1'b0),`
289			`.GND5O (gnd),`
290			`.GND5R (gnd),`
291			`.VDD5O (vdd),`
292			`.VDD5R (vdd),`
293	255	creep	`.CLAMPC (dummy_clampc),`
294			`.PAD (data_out[4])`
295	252	creep	`);`
296
297	255	creep	`BT4P data_out_pad5(`
298			`.A (data_outIO[5]),`
299	258	creep	`.EN (1'b0),`
300			`.GND5O (gnd),`
301			`.GND5R (gnd),`
302			`.VDD5O (vdd),`
303			`.VDD5R (vdd),`
304	255	creep	`.CLAMPC (dummy_clampc),`
305			`.PAD (data_out[5])`
306	252	creep	`);`
307
308	255	creep	`BT4P data_out_pad6(`
309			`.A (data_outIO[6]),`
310	258	creep	`.EN (1'b0),`
311			`.GND5O (gnd),`
312			`.GND5R (gnd),`
313			`.VDD5O (vdd),`
314			`.VDD5R (vdd),`
315	255	creep	`.CLAMPC (dummy_clampc),`
316			`.PAD (data_out[6])`
317	252	creep	`);`
318
319	255	creep	`BT4P data_out_pad7(`
320			`.A (data_outIO[7]),`
321	258	creep	`.EN (1'b0),`
322			`.GND5O (gnd),`
323			`.GND5R (gnd),`
324			`.VDD5O (vdd),`
325			`.VDD5R (vdd),`
326	255	creep	`.CLAMPC (dummy_clampc),`
327			`.PAD (data_out[7])`
328	252	creep	`);`
329
330	255	creep	`BT4P address_pad0(`
331			`.A (addressIO[0]),`
332	258	creep	`.EN (1'b0),`
333			`.GND5O (gnd),`
334			`.GND5R (gnd),`
335			`.VDD5O (vdd),`
336			`.VDD5R (vdd),`
337	255	creep	`.CLAMPC (dummy_clampc),`
338			`.PAD (address[0])`
339	252	creep	`);`
340
341	255	creep	`BT4P address_pad1(`
342			`.A (addressIO[1]),`
343	258	creep	`.EN (1'b0),`
344			`.GND5O (gnd),`
345			`.GND5R (gnd),`
346			`.VDD5O (vdd),`
347			`.VDD5R (vdd),`
348	255	creep	`.CLAMPC (dummy_clampc),`
349			`.PAD (address[1])`
350	252	creep	`);`
351	255	creep	`BT4P address_pad2(`
352			`.A (addressIO[2]),`
353	258	creep	`.EN (1'b0),`
354			`.GND5O (gnd),`
355			`.GND5R (gnd),`
356			`.VDD5O (vdd),`
357			`.VDD5R (vdd),`
358	255	creep	`.CLAMPC (dummy_clampc),`
359			`.PAD (address[2])`
360			`);`
361			`BT4P address_pad3(`
362			`.A (addressIO[3]),`
363	258	creep	`.EN (1'b0),`
364			`.GND5O (gnd),`
365			`.GND5R (gnd),`
366			`.VDD5O (vdd),`
367			`.VDD5R (vdd),`
368	255	creep	`.CLAMPC (dummy_clampc),`
369			`.PAD (address[3])`
370			`);`
371			`BT4P address_pad4(`
372			`.A (addressIO[4]),`
373	258	creep	`.EN (1'b0),`
374			`.GND5O (gnd),`
375			`.GND5R (gnd),`
376			`.VDD5O (vdd),`
377			`.VDD5R (vdd),`
378	255	creep	`.CLAMPC (dummy_clampc),`
379			`.PAD (address[4])`
380			`);`
381			`BT4P address_pad5(`
382			`.A (addressIO[5]),`
383	258	creep	`.EN (1'b0),`
384			`.GND5O (gnd),`
385			`.GND5R (gnd),`
386			`.VDD5O (vdd),`
387			`.VDD5R (vdd),`
388	255	creep	`.CLAMPC (dummy_clampc),`
389			`.PAD (address[5])`
390			`);`
391			`BT4P address_pad6(`
392			`.A (addressIO[6]),`
393	258	creep	`.EN (1'b0),`
394			`.GND5O (gnd),`
395			`.GND5R (gnd),`
396			`.VDD5O (vdd),`
397			`.VDD5R (vdd),`
398	255	creep	`.CLAMPC (dummy_clampc),`
399			`.PAD (address[6])`
400			`);`
401			`BT4P address_pad7(`
402			`.A (addressIO[7]),`
403	258	creep	`.EN (1'b0),`
404			`.GND5O (gnd),`
405			`.GND5R (gnd),`
406			`.VDD5O (vdd),`
407			`.VDD5R (vdd),`
408	255	creep	`.CLAMPC (dummy_clampc),`
409			`.PAD (address[7])`
410			`);`
411			`BT4P address_pad8(`
412			`.A (addressIO[8]),`
413	258	creep	`.EN (1'b0),`
414			`.GND5O (gnd),`
415			`.GND5R (gnd),`
416			`.VDD5O (vdd),`
417			`.VDD5R (vdd),`
418	255	creep	`.CLAMPC (dummy_clampc),`
419			`.PAD (address[8])`
420			`);`
421			`BT4P address_pad9(`
422			`.A (addressIO[9]),`
423	258	creep	`.EN (1'b0),`
424			`.GND5O (gnd),`
425			`.GND5R (gnd),`
426			`.VDD5O (vdd),`
427			`.VDD5R (vdd),`
428	255	creep	`.CLAMPC (dummy_clampc),`
429			`.PAD (address[9])`
430			`);`
431			`BT4P address_pad10(`
432			`.A (addressIO[10]),`
433	258	creep	`.EN (1'b0),`
434			`.GND5O (gnd),`
435			`.GND5R (gnd),`
436			`.VDD5O (vdd),`
437			`.VDD5R (vdd),`
438	255	creep	`.CLAMPC (dummy_clampc),`
439			`.PAD (address[10])`
440			`);`
441			`BT4P address_pad11(`
442			`.A (addressIO[11]),`
443	258	creep	`.EN (1'b0),`
444			`.GND5O (gnd),`
445			`.GND5R (gnd),`
446			`.VDD5O (vdd),`
447			`.VDD5R (vdd),`
448	255	creep	`.CLAMPC (dummy_clampc),`
449			`.PAD (address[11])`
450			`);`
451	252	creep
452	255	creep	`BT4P address_pad12(`
453			`.A (addressIO[12]),`
454	258	creep	`.EN (1'b0),`
455			`.GND5O (gnd),`
456			`.GND5R (gnd),`
457			`.VDD5O (vdd),`
458			`.VDD5R (vdd),`
459	255	creep	`.CLAMPC (dummy_clampc),`
460			`.PAD (address[12])`
461	252	creep	`);`
462
463	255	creep	`CORNERCLMP left_up_pad (`
464			`.CLAMPC (dummy_clampc),`
465	258	creep	`.VDD5O (vdd),`
466			`.VDD5R (vdd),`
467			`.GND5O (gnd),`
468			`.GND5R (gnd)`
469	252	creep	`);`
470
471	255	creep	`CORNERCLMP left_down_pad (`
472			`.CLAMPC (dummy_clampc),`
473	258	creep	`.VDD5O (vdd),`
474			`.VDD5R (vdd),`
475			`.GND5O (gnd),`
476			`.GND5R (gnd)`
477	252	creep	`);`
478
479	255	creep	`CORNERCLMP right_up_pad (`
480			`.CLAMPC (dummy_clampc),`
481	258	creep	`.VDD5O (vdd),`
482			`.VDD5R (vdd),`
483			`.GND5O (gnd),`
484			`.GND5R (gnd)`
485	252	creep	`);`
486
487	255	creep	`CORNERCLMP right_down_pad (`
488			`.CLAMPC (dummy_clampc),`
489	258	creep	`.VDD5O (vdd),`
490			`.VDD5R (vdd),`
491			`.GND5O (gnd),`
492			`.GND5R (gnd)`
493	252	creep	`);`
494
495	255	creep	`GND5ALLPADP gnd_pad_left (`
496			`.CLAMPC (dummy_clampc),`
497	258	creep	`.VDD5O (vdd),`
498			`.VDD5R (vdd),`
499			`.GND (gnd)`
500	252	creep	`);`

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