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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6532.v] - Blame information for rev 192

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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// t6532 IP Core                                                      ////
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////                                                                    ////
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//// This file is part of the t2600 project                             ////
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//// http://www.opencores.org/cores/t2600/                              ////
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////                                                                    ////
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//// Description                                                        ////
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//// 6532 top level                                                     ////
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////                                                                    ////
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//// TODO:                                                              ////
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//// - Add the timer, ram and i/o                                       ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
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////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
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//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
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//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
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//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module t6532(clk, io_lines, enable, address, data);
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        parameter [3:0] DATA_SIZE = 4'd8;
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        parameter [3:0] ADDR_SIZE = 4'd7; // this is the *local* addr_size
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        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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        input clk;
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        input [15:0] io_lines;
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        input enable;
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        input [ADDR_SIZE_:0] address;
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        inout [DATA_SIZE_:0] data;
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endmodule

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