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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t6532 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// 6532 top level                                                     ////
////                                                                    ////
//// TODO:                                                              ////
//// - Add the timer, ram and i/o                                       ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module t6532(clk, io_lines, enable, rw_mem, address, data);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd7; // this is the *local* addr_size
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
 
        input clk; // master clock signal, 1.19mhz
        input [15:0] io_lines; // inputs from the keyboard controller
        input enable; // since the address bus is shared an enable signal is used
        input rw_mem; // read == 0, write == 1
        input [ADDR_SIZE_:0] address; // system address bus
        inout [DATA_SIZE_:0] data; // controler <=> riot data bus
 
        reg [DATA_SIZE_:0] ram [8'h80:8'hFF]; // the ram itself. TODO: test the memory compiler
        reg [DATA_SIZE_:0] port_a;
        reg [DATA_SIZE_:0] port_b;
        reg [DATA_SIZE_:0] ddra;
        reg [DATA_SIZE_:0] timer; // the timer
        reg c1_timer; // 1 clock cycle counter enable
        reg c8_timer; // 8 clock cycles counter enable
        reg c64_timer; // 64 clock cycles counter enable
        reg c1024_timer; // 1024 clock cycles counter enable
        reg [10:0] counter; // also called the prescaler
        reg flipped; // a flag to remember if the timer already flipped
 
        reg reading; // combinational logic for easing the control over timers
        reg writing;
        reg writing_at_timer;
 
        reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
 
        assign data = (rw_mem) ? 8'bZ: data_drv; // if under writing the bus receives the data from cpu, else local data.  
 
        always @(posedge clk) begin // I/O handling
                port_b[0] <= ~io_lines[0]; // these two are not actually switches
                port_b[1] <= ~io_lines[1];
 
                if (io_lines[3]) begin // these are.
                        port_b[3] <= !port_b[3];
                end
                if (io_lines[6]) begin
                        port_b[6] <= !port_b[6];
                end
                if (io_lines[7]) begin
                        port_b[7] <= !port_b[7];
                end
 
                port_a[0] <= (ddra[0] == 0) ? io_lines[8] : port_a[0];
                port_a[1] <= (ddra[1] == 0) ? io_lines[9] : port_a[1];
                port_a[2] <= (ddra[2] == 0) ? io_lines[10] : port_a[2];
                port_a[3] <= (ddra[3] == 0) ? io_lines[11] : port_a[3];
                port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
                port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
                port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
                port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
 
        end
 
        always @(posedge clk) begin // R/W register/memory handling
                if (reading) begin // reading! 
                        case (address)
                                10'h280: data_drv <= port_a;
                                10'h281: data_drv <= ddra;
                                10'h282: data_drv <= port_b;
                                10'h283: data_drv <= 8'h00; // portb ddr is always input
                                10'h284: data_drv <= timer;
                                default: data_drv <= ram[address];
                        endcase
                end
                else if (writing) begin // writing! 
                        case (address)
                                10'h294: begin
                                        c1_timer <= 1;
                                        c8_timer <= 0;
                                        c64_timer <= 0;
                                        c1024_timer <= 0;
                                        timer <= data;
                                        flipped <= 0;
                                        counter <= 1;
                                end
                                10'h295: begin
                                        c1_timer <= 0;
                                        c8_timer <= 1;
                                        c64_timer <= 0;
                                        c1024_timer <= 0;
                                        timer <= data;
                                        flipped <= 0;
                                        counter <= 8;
                                end
                                10'h296: begin
                                        c1_timer <= 0;
                                        c8_timer <= 0;
                                        c64_timer <= 1;
                                        c1024_timer <= 0;
                                        timer <= data;
                                        flipped <= 0;
                                        counter <= 64;
                                end
                                10'h297: begin
                                        c1_timer <= 0;
                                        c8_timer <= 0;
                                        c64_timer <= 0;
                                        c1024_timer <= 1;
                                        timer <= data;
                                        flipped <= 0;
                                        counter <= 1024;
                                end
                                default: begin
                                        ram[address] <= data;
                                end
                        endcase
                end
        end
 
        always @(posedge clk) begin // timer!
                if (!writing_at_timer) begin
                        if (counter == 0) begin
                                timer <= timer - 1;
 
                                if (timer == 0) begin
                                        flipped <= 1'b1;
                                end
 
                                if (c1_timer || flipped) begin
                                        counter <= 1;
                                end
                                if (c8_timer) begin
                                        counter <= 8;
                                end
                                if (c64_timer) begin
                                        counter <= 64;
                                end
                                if (c1024_timer) begin
                                        counter <= 1024;
                                end
                        end
                        else begin
                                counter <= counter - 1;
                        end
                end
        end
 
        always @(*) begin// logic for easier controlling
                reading = 1'b0;
                writing = 1'b0;
                writing_at_timer = 1'b0;
 
                if (enable && rw_mem == 0) begin
                        reading = 1'b1;
                end
                else if (enable && rw_mem) begin
                        writing = 1'b1;
 
                        if (address == 10'h294 || address == 10'h295 || address == 10'h296 || address == 10'h297) begin
                                writing_at_timer = 1'b1;
                        end
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	192	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t6532 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6532 top level ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Add the timer, ram and i/o ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	193	creep	`module t6532(clk, io_lines, enable, rw_mem, address, data);`
48	192	creep	`parameter [3:0] DATA_SIZE = 4'd8;`
49			`parameter [3:0] ADDR_SIZE = 4'd7; // this is the local addr_size`
50
51			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;`
52			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;`
53
54	197	creep	`input clk; // master clock signal, 1.19mhz`
55			`input [15:0] io_lines; // inputs from the keyboard controller`
56			`input enable; // since the address bus is shared an enable signal is used`
57			`input rw_mem; // read == 0, write == 1`
58			`input [ADDR_SIZE_:0] address; // system address bus`
59			`inout [DATA_SIZE_:0] data; // controler <=> riot data bus`
60	193	creep
61	197	creep	`reg [DATA_SIZE_:0] ram [8'h80:8'hFF]; // the ram itself. TODO: test the memory compiler`
62	194	creep	`reg [DATA_SIZE_:0] port_a;`
63			`reg [DATA_SIZE_:0] port_b;`
64			`reg [DATA_SIZE_:0] ddra;`
65	197	creep	`reg [DATA_SIZE_:0] timer; // the timer`
66			`reg c1_timer; // 1 clock cycle counter enable`
67			`reg c8_timer; // 8 clock cycles counter enable`
68			`reg c64_timer; // 64 clock cycles counter enable`
69			`reg c1024_timer; // 1024 clock cycles counter enable`
70			`reg [10:0] counter; // also called the prescaler`
71			`reg flipped; // a flag to remember if the timer already flipped`
72
73			`reg reading; // combinational logic for easing the control over timers`
74			`reg writing;`
75			`reg writing_at_timer;`
76	196	creep
77	197	creep	`reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus`
78	193	creep
79	197	creep	`assign data = (rw_mem) ? 8'bZ: data_drv; // if under writing the bus receives the data from cpu, else local data.`
80	193	creep
81	197	creep	`always @(posedge clk) begin // I/O handling`
82	194	creep	`port_b[0] <= ~io_lines[0]; // these two are not actually switches`
83			`port_b[1] <= ~io_lines[1];`
84
85			`if (io_lines[3]) begin // these are.`
86			`port_b[3] <= !port_b[3];`
87			`end`
88			`if (io_lines[6]) begin`
89			`port_b[6] <= !port_b[6];`
90			`end`
91			`if (io_lines[7]) begin`
92			`port_b[7] <= !port_b[7];`
93			`end`
94	193	creep
95	194	creep	`port_a[0] <= (ddra[0] == 0) ? io_lines[8] : port_a[0];`
96			`port_a[1] <= (ddra[1] == 0) ? io_lines[9] : port_a[1];`
97			`port_a[2] <= (ddra[2] == 0) ? io_lines[10] : port_a[2];`
98			`port_a[3] <= (ddra[3] == 0) ? io_lines[11] : port_a[3];`
99			`port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];`
100			`port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];`
101			`port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];`
102			`port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];`
103	197	creep
104			`end`
105	194	creep
106	197	creep	`always @(posedge clk) begin // R/W register/memory handling`
107			`if (reading) begin // reading!`
108	193	creep	`case (address)`
109	197	creep	`10'h280: data_drv <= port_a;`
110			`10'h281: data_drv <= ddra;`
111			`10'h282: data_drv <= port_b;`
112			`10'h283: data_drv <= 8'h00; // portb ddr is always input`
113			`10'h284: data_drv <= timer;`
114			`default: data_drv <= ram[address];`
115	193	creep	`endcase`
116			`end`
117	197	creep	`else if (writing) begin // writing!`
118			`case (address)`
119			`10'h294: begin`
120			`c1_timer <= 1;`
121			`c8_timer <= 0;`
122			`c64_timer <= 0;`
123			`c1024_timer <= 0;`
124			`timer <= data;`
125			`flipped <= 0;`
126			`counter <= 1;`
127			`end`
128			`10'h295: begin`
129			`c1_timer <= 0;`
130			`c8_timer <= 1;`
131			`c64_timer <= 0;`
132			`c1024_timer <= 0;`
133			`timer <= data;`
134			`flipped <= 0;`
135			`counter <= 8;`
136			`end`
137			`10'h296: begin`
138			`c1_timer <= 0;`
139			`c8_timer <= 0;`
140			`c64_timer <= 1;`
141			`c1024_timer <= 0;`
142			`timer <= data;`
143			`flipped <= 0;`
144			`counter <= 64;`
145			`end`
146			`10'h297: begin`
147			`c1_timer <= 0;`
148			`c8_timer <= 0;`
149			`c64_timer <= 0;`
150			`c1024_timer <= 1;`
151			`timer <= data;`
152			`flipped <= 0;`
153			`counter <= 1024;`
154			`end`
155			`default: begin`
156			`ram[address] <= data;`
157			`end`
158			`endcase`
159			`end`
160	193	creep	`end`
161
162	197	creep	`always @(posedge clk) begin // timer!`
163			`if (!writing_at_timer) begin`
164			`if (counter == 0) begin`
165			`timer <= timer - 1;`
166
167			`if (timer == 0) begin`
168			`flipped <= 1'b1;`
169			`end`
170
171			`if (c1_timer \|\| flipped) begin`
172			`counter <= 1;`
173			`end`
174			`if (c8_timer) begin`
175			`counter <= 8;`
176			`end`
177			`if (c64_timer) begin`
178			`counter <= 64;`
179			`end`
180			`if (c1024_timer) begin`
181			`counter <= 1024;`
182			`end`
183			`end`
184			`else begin`
185			`counter <= counter - 1;`
186			`end`
187			`end`
188			`end`
189
190			`always @(*) begin// logic for easier controlling`
191			`reading = 1'b0;`
192			`writing = 1'b0;`
193			`writing_at_timer = 1'b0;`
194
195			`if (enable && rw_mem == 0) begin`
196			`reading = 1'b1;`
197			`end`
198			`else if (enable && rw_mem) begin`
199			`writing = 1'b1;`
200
201			`if (address == 10'h294 \|\| address == 10'h295 \|\| address == 10'h296 \|\| address == 10'h297) begin`
202			`writing_at_timer = 1'b1;`
203			`end`
204			`end`
205			`end`
206	192	creep
207			`endmodule`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6532.v] - Blame information for rev 197