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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// VGA controller                                                     ////
////                                                                    ////
//// TODO:                                                              ////
//// - Feed the controller with data                                    ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module vga_controller ( reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
 
input reset;
input clk_50;
input [8:0] SW;
output reg [3:0] VGA_R;
output reg [3:0] VGA_G;
output reg [3:0] VGA_B;
output [9:0] LEDR;
output reg VGA_VS;
output reg VGA_HS;
 
 
reg clk_25;
reg [9:0] hc;
reg [9:0] vc;
reg vsenable;
wire vidon;
 
assign LEDR = SW;
 
always @ (posedge clk_50 or negedge reset)
begin
        if (!reset) begin
                clk_25 <= 0;
        end
        else begin
                clk_25 <= !clk_25;
        end
end
 
always @ (posedge clk_25 or negedge reset)
begin
        if (!reset) begin
                hc <= 0;
                VGA_HS <= 1;
                vsenable <= 0;
        end
        else if (hc < 640) begin
                hc <= hc + 1;
                vsenable <= 0;
                VGA_HS <= 1;
        end
        else if (hc < 640 + 16) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96) begin
                VGA_HS <= 0;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96 + 48) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else begin
                VGA_HS <= 1;
                hc <= 0;
                vsenable <= 1;
        end
end
 
always @ (posedge clk_25 or negedge reset)
begin
        if (!reset) begin
                vc <= 0;
                VGA_VS <= 1;
        end
        else begin
                if (vsenable == 1) begin
                        vc <= vc + 1;
                end
                if (vc < 480) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11 + 2) begin
                        VGA_VS <= 0;
                end
                else if (vc < 480 + 11 + 2 + 31) begin
                        VGA_VS <= 1;
                end
                else begin
                        vc <= 0;
                        VGA_VS <= 1;
                end
        end
end
 
always @ (posedge clk_25)
begin
        if (vidon == 1) begin
                if (hc < 320) begin
                        if (vc < 240) begin
                                VGA_R[0] <= 1;
                                VGA_G[0] <= 1;
                                VGA_B[0] <= 1;
                                VGA_R[1] <= 1;
                                VGA_G[1] <= 1;
                                VGA_B[1] <= 1;
                                VGA_R[2] <= 1;
                                VGA_G[2] <= 1;
                                VGA_B[2] <= 1;
                                VGA_R[3] <= 1;
                                VGA_G[3] <= 1;
                                VGA_B[3] <= 1;
                        end
                        else begin
                                VGA_R[0] <= 0;
                                VGA_G[0] <= 0;
                                VGA_B[0] <= 1;
                                VGA_R[1] <= 0;
                                VGA_G[1] <= 0;
                                VGA_B[1] <= 1;
                                VGA_R[2] <= 0;
                                VGA_G[2] <= 0;
                                VGA_B[2] <= 1;
                                VGA_R[3] <= 0;
                                VGA_G[3] <= 0;
                                VGA_B[3] <= 1;
                        end
                end
                else begin
                        if (vc < 240) begin
                                VGA_R[0] <= 1;
                                VGA_G[0] <= 0;
                                VGA_B[0] <= 0;
                                VGA_R[1] <= 1;
                                VGA_G[1] <= 0;
                                VGA_B[1] <= 0;
                                VGA_R[2] <= 1;
                                VGA_G[2] <= 0;
                                VGA_B[2] <= 0;
                                VGA_R[3] <= 1;
                                VGA_G[3] <= 0;
                                VGA_B[3] <= 0;
                        end
                        else begin
                                VGA_R[0] <= 0;
                                VGA_G[0] <= 1;
                                VGA_B[0] <= 0;
                                VGA_R[1] <= 0;
                                VGA_G[1] <= 1;
                                VGA_B[1] <= 0;
                                VGA_R[2] <= 0;
                                VGA_G[2] <= 1;
                                VGA_B[2] <= 0;
                                VGA_R[3] <= 0;
                                VGA_G[3] <= 1;
                                VGA_B[3] <= 0;
                        end
                end
        end
        else begin
                VGA_R[0] <= 0;
                VGA_G[0] <= 0;
                VGA_B[0] <= 0;
                VGA_R[1] <= 0;
                VGA_G[1] <= 0;
                VGA_B[1] <= 0;
                VGA_R[2] <= 0;
                VGA_G[2] <= 0;
                VGA_B[2] <= 0;
                VGA_R[3] <= 0;
                VGA_G[3] <= 0;
                VGA_B[3] <= 0;
        end
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
 
endmodule

Line No.	Rev	Author	Line
1	221	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// VGA controller ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Feed the controller with data ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	222	creep	`module vga_controller ( reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);`
48	221	creep
49	223	gabrielosh	`input reset;`
50			`input clk_50;`
51			`input [8:0] SW;`
52			`output reg [3:0] VGA_R;`
53			`output reg [3:0] VGA_G;`
54			`output reg [3:0] VGA_B;`
55			`output [9:0] LEDR;`
56			`output reg VGA_VS;`
57			`output reg VGA_HS;`
58	222	creep
59
60	221	creep	`reg clk_25;`
61			`reg [9:0] hc;`
62			`reg [9:0] vc;`
63			`reg vsenable;`
64			`wire vidon;`
65
66			`assign LEDR = SW;`
67
68			`always @ (posedge clk_50 or negedge reset)`
69			`begin`
70			`if (!reset) begin`
71			`clk_25 <= 0;`
72			`end`
73			`else begin`
74			`clk_25 <= !clk_25;`
75			`end`
76			`end`
77
78			`always @ (posedge clk_25 or negedge reset)`
79			`begin`
80			`if (!reset) begin`
81			`hc <= 0;`
82			`VGA_HS <= 1;`
83			`vsenable <= 0;`
84			`end`
85			`else if (hc < 640) begin`
86			`hc <= hc + 1;`
87			`vsenable <= 0;`
88			`VGA_HS <= 1;`
89			`end`
90			`else if (hc < 640 + 16) begin`
91			`VGA_HS <= 1;`
92			`hc <= hc + 1;`
93			`vsenable <= 0;`
94			`end`
95			`else if (hc < 640 + 16 + 96) begin`
96			`VGA_HS <= 0;`
97			`hc <= hc + 1;`
98			`vsenable <= 0;`
99			`end`
100			`else if (hc < 640 + 16 + 96 + 48) begin`
101			`VGA_HS <= 1;`
102			`hc <= hc + 1;`
103			`vsenable <= 0;`
104			`end`
105			`else begin`
106			`VGA_HS <= 1;`
107			`hc <= 0;`
108			`vsenable <= 1;`
109			`end`
110			`end`
111
112			`always @ (posedge clk_25 or negedge reset)`
113			`begin`
114			`if (!reset) begin`
115			`vc <= 0;`
116			`VGA_VS <= 1;`
117			`end`
118			`else begin`
119			`if (vsenable == 1) begin`
120			`vc <= vc + 1;`
121			`end`
122			`if (vc < 480) begin`
123			`VGA_VS <= 1;`
124			`end`
125			`else if (vc < 480 + 11) begin`
126			`VGA_VS <= 1;`
127			`end`
128			`else if (vc < 480 + 11 + 2) begin`
129			`VGA_VS <= 0;`
130			`end`
131			`else if (vc < 480 + 11 + 2 + 31) begin`
132			`VGA_VS <= 1;`
133			`end`
134			`else begin`
135			`vc <= 0;`
136			`VGA_VS <= 1;`
137			`end`
138			`end`
139			`end`
140
141			`always @ (posedge clk_25)`
142			`begin`
143			`if (vidon == 1) begin`
144			`if (hc < 320) begin`
145			`if (vc < 240) begin`
146			`VGA_R[0] <= 1;`
147			`VGA_G[0] <= 1;`
148			`VGA_B[0] <= 1;`
149			`VGA_R[1] <= 1;`
150			`VGA_G[1] <= 1;`
151			`VGA_B[1] <= 1;`
152			`VGA_R[2] <= 1;`
153			`VGA_G[2] <= 1;`
154			`VGA_B[2] <= 1;`
155			`VGA_R[3] <= 1;`
156			`VGA_G[3] <= 1;`
157			`VGA_B[3] <= 1;`
158			`end`
159			`else begin`
160			`VGA_R[0] <= 0;`
161			`VGA_G[0] <= 0;`
162			`VGA_B[0] <= 1;`
163			`VGA_R[1] <= 0;`
164			`VGA_G[1] <= 0;`
165			`VGA_B[1] <= 1;`
166			`VGA_R[2] <= 0;`
167			`VGA_G[2] <= 0;`
168			`VGA_B[2] <= 1;`
169			`VGA_R[3] <= 0;`
170			`VGA_G[3] <= 0;`
171			`VGA_B[3] <= 1;`
172			`end`
173			`end`
174			`else begin`
175			`if (vc < 240) begin`
176			`VGA_R[0] <= 1;`
177			`VGA_G[0] <= 0;`
178			`VGA_B[0] <= 0;`
179			`VGA_R[1] <= 1;`
180			`VGA_G[1] <= 0;`
181			`VGA_B[1] <= 0;`
182			`VGA_R[2] <= 1;`
183			`VGA_G[2] <= 0;`
184			`VGA_B[2] <= 0;`
185			`VGA_R[3] <= 1;`
186			`VGA_G[3] <= 0;`
187			`VGA_B[3] <= 0;`
188			`end`
189			`else begin`
190			`VGA_R[0] <= 0;`
191			`VGA_G[0] <= 1;`
192			`VGA_B[0] <= 0;`
193			`VGA_R[1] <= 0;`
194			`VGA_G[1] <= 1;`
195			`VGA_B[1] <= 0;`
196			`VGA_R[2] <= 0;`
197			`VGA_G[2] <= 1;`
198			`VGA_B[2] <= 0;`
199			`VGA_R[3] <= 0;`
200			`VGA_G[3] <= 1;`
201			`VGA_B[3] <= 0;`
202			`end`
203			`end`
204			`end`
205			`else begin`
206			`VGA_R[0] <= 0;`
207			`VGA_G[0] <= 0;`
208			`VGA_B[0] <= 0;`
209			`VGA_R[1] <= 0;`
210			`VGA_G[1] <= 0;`
211			`VGA_B[1] <= 0;`
212			`VGA_R[2] <= 0;`
213			`VGA_G[2] <= 0;`
214			`VGA_B[2] <= 0;`
215			`VGA_R[3] <= 0;`
216			`VGA_G[3] <= 0;`
217			`VGA_B[3] <= 0;`
218			`end`
219			`end`
220
221			`assign vidon = (hc < 640 && vc < 480) ? 1 : 0;`
222
223			`endmodule`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Blame information for rev 223