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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// VGA controller                                                     ////
////                                                                    ////
//// TODO:                                                              ////
//// - Feed the controller with data                                    ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module vga_controller ( reset, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
 
input reset;
input clk_50;
input [8:0] SW;
input [479:0] line;
input [4:0] vert_counter;
output reg [3:0] VGA_R;
output reg [3:0] VGA_G;
output reg [3:0] VGA_B;
output [9:0] LEDR;
output reg VGA_VS;
output reg VGA_HS;
 
reg clk_25;
reg [9:0] hc;
reg [9:0] vc;
reg vsenable;
wire vidon;
 
assign LEDR[8:0] = SW;
assign LEDR[9] = reset;
 
always @ (posedge clk_50 or negedge reset)
begin
        if (!reset) begin
                clk_25 <= 0;
        end
        else begin
                clk_25 <= !clk_25;
        end
end
 
always @ (posedge clk_25 or negedge reset)
begin
        if (!reset) begin
                hc <= 0;
                VGA_HS <= 1;
                vsenable <= 0;
        end
        else if (hc < 640) begin
                hc <= hc + 1;
                vsenable <= 0;
                VGA_HS <= 1;
        end
        else if (hc < 640 + 16) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96) begin
                VGA_HS <= 0;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96 + 48) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else begin
                VGA_HS <= 1;
                hc <= 0;
                vsenable <= 1;
        end
end
 
always @ (posedge clk_25 or negedge reset)
begin
        if (!reset) begin
                vc <= 0;
                VGA_VS <= 1;
        end
        else begin
                if (vsenable == 1) begin
                        vc <= vc + 1;
                end
                if (vc < 480) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11 + 2) begin
                        VGA_VS <= 0;
                end
                else if (vc < 480 + 11 + 2 + 31) begin
                        VGA_VS <= 1;
                end
                else begin
                        vc <= 0;
                        VGA_VS <= 1;
                end
        end
end
 
always @ (posedge clk_25)
begin
        if (vidon == 1) begin
                if (hc < 40) begin
                        if (vert_counter < 10) begin
                                /*VGA_R[0] <= line[hc*12];
                                VGA_R[1] <= line[hc*12+1];
                                VGA_R[2] <= line[hc*12+2];
                                VGA_R[3] <= line[hc*12+3];
                                VGA_G[0] <= line[hc*12+4];
                                VGA_G[1] <= line[hc*12+5];
                                VGA_G[2] <= line[hc*12+6];
                                VGA_G[3] <= line[hc*12+7];
                                VGA_B[0] <= line[hc*12+8];
                                VGA_B[1] <= line[hc*12+9];
                                VGA_B[2] <= line[hc*12+10];
                                VGA_B[3] <= line[hc*12+11];*/
                                VGA_R[0] <= 1;
                                VGA_R[1] <= 0;
                                VGA_R[2] <= 1;
                                VGA_R[3] <= 0;
                                VGA_G[0] <= 1;
                                VGA_G[1] <= 0;
                                VGA_G[2] <= 1;
                                VGA_G[3] <= 0;
                                VGA_B[0] <= 1;
                                VGA_B[1] <= 0;
                                VGA_B[2] <= 1;
                                VGA_B[3] <= 0;
                        end
                        else begin
                                VGA_R[0] <= 0;
                                VGA_G[0] <= 0;
                                VGA_B[0] <= 0;
                                VGA_R[1] <= 0;
                                VGA_G[1] <= 0;
                                VGA_B[1] <= 0;
                                VGA_R[2] <= 0;
                                VGA_G[2] <= 0;
                                VGA_B[2] <= 0;
                                VGA_R[3] <= 0;
                                VGA_G[3] <= 0;
                                VGA_B[3] <= 0;
                end
                end
                else begin
                        VGA_R[0] <= 0;
                        VGA_G[0] <= 0;
                        VGA_B[0] <= 0;
                        VGA_R[1] <= 0;
                        VGA_G[1] <= 0;
                        VGA_B[1] <= 0;
                        VGA_R[2] <= 0;
                        VGA_G[2] <= 0;
                        VGA_B[2] <= 0;
                        VGA_R[3] <= 0;
                        VGA_G[3] <= 0;
                        VGA_B[3] <= 0;
                end
 
/*                      if (vc < 240) begin
                                VGA_R[0] <= 1;
                                VGA_G[0] <= 1;
                                VGA_B[0] <= 1;
                                VGA_R[1] <= 1;
                                VGA_G[1] <= 1;
                                VGA_B[1] <= 1;
                                VGA_R[2] <= 1;
                                VGA_G[2] <= 1;
                                VGA_B[2] <= 1;
                                VGA_R[3] <= 1;
                                VGA_G[3] <= 1;
                                VGA_B[3] <= 1;
                        end
                        else begin
                                VGA_R[0] <= 0;
                                VGA_G[0] <= 0;
                                VGA_B[0] <= 1;
                                VGA_R[1] <= 0;
                                VGA_G[1] <= 0;
                                VGA_B[1] <= 1;
                                VGA_R[2] <= 0;
                                VGA_G[2] <= 0;
                                VGA_B[2] <= 1;
                                VGA_R[3] <= 0;
                                VGA_G[3] <= 0;
                                VGA_B[3] <= 1;
                        end
                end
                else begin
                        if (vc < 240) begin
                                VGA_R[0] <= 1;
                                VGA_G[0] <= 0;
                                VGA_B[0] <= 0;
                                VGA_R[1] <= 1;
                                VGA_G[1] <= 0;
                                VGA_B[1] <= 0;
                                VGA_R[2] <= 1;
                                VGA_G[2] <= 0;
                                VGA_B[2] <= 0;
                                VGA_R[3] <= 1;
                                VGA_G[3] <= 0;
                                VGA_B[3] <= 0;
                        end
                        else begin
                                VGA_R[0] <= 0;
                                VGA_G[0] <= 1;
                                VGA_B[0] <= 0;
                                VGA_R[1] <= 0;
                                VGA_G[1] <= 1;
                                VGA_B[1] <= 0;
                                VGA_R[2] <= 0;
                                VGA_G[2] <= 1;
                                VGA_B[2] <= 0;
                                VGA_R[3] <= 0;
                                VGA_G[3] <= 1;
                                VGA_B[3] <= 0;
                        end
                end
        end
        */
        end
        else begin
                VGA_R[0] <= 0;
                VGA_G[0] <= 0;
                VGA_B[0] <= 0;
                VGA_R[1] <= 0;
                VGA_G[1] <= 0;
                VGA_B[1] <= 0;
                VGA_R[2] <= 0;
                VGA_G[2] <= 0;
                VGA_B[2] <= 0;
                VGA_R[3] <= 0;
                VGA_G[3] <= 0;
                VGA_B[3] <= 0;
        end
 
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
 
endmodule

Line No.	Rev	Author	Line
1	221	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// VGA controller ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Feed the controller with data ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	225	gabrielosh	`module vga_controller ( reset, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);`
48	221	creep
49	223	gabrielosh	`input reset;`
50			`input clk_50;`
51	224	creep	`input [8:0] SW;`
52	225	gabrielosh	`input [479:0] line;`
53			`input [4:0] vert_counter;`
54	223	gabrielosh	`output reg [3:0] VGA_R;`
55			`output reg [3:0] VGA_G;`
56			`output reg [3:0] VGA_B;`
57			`output [9:0] LEDR;`
58			`output reg VGA_VS;`
59			`output reg VGA_HS;`
60	222	creep
61	221	creep	`reg clk_25;`
62			`reg [9:0] hc;`
63			`reg [9:0] vc;`
64			`reg vsenable;`
65			`wire vidon;`
66
67	225	gabrielosh	`assign LEDR[8:0] = SW;`
68			`assign LEDR[9] = reset;`
69	221	creep
70			`always @ (posedge clk_50 or negedge reset)`
71			`begin`
72			`if (!reset) begin`
73			`clk_25 <= 0;`
74			`end`
75			`else begin`
76			`clk_25 <= !clk_25;`
77			`end`
78			`end`
79
80			`always @ (posedge clk_25 or negedge reset)`
81			`begin`
82			`if (!reset) begin`
83			`hc <= 0;`
84			`VGA_HS <= 1;`
85			`vsenable <= 0;`
86			`end`
87			`else if (hc < 640) begin`
88			`hc <= hc + 1;`
89			`vsenable <= 0;`
90			`VGA_HS <= 1;`
91			`end`
92			`else if (hc < 640 + 16) begin`
93			`VGA_HS <= 1;`
94			`hc <= hc + 1;`
95			`vsenable <= 0;`
96			`end`
97			`else if (hc < 640 + 16 + 96) begin`
98			`VGA_HS <= 0;`
99			`hc <= hc + 1;`
100			`vsenable <= 0;`
101			`end`
102			`else if (hc < 640 + 16 + 96 + 48) begin`
103			`VGA_HS <= 1;`
104			`hc <= hc + 1;`
105			`vsenable <= 0;`
106			`end`
107			`else begin`
108			`VGA_HS <= 1;`
109			`hc <= 0;`
110			`vsenable <= 1;`
111			`end`
112			`end`
113
114			`always @ (posedge clk_25 or negedge reset)`
115			`begin`
116			`if (!reset) begin`
117			`vc <= 0;`
118			`VGA_VS <= 1;`
119			`end`
120			`else begin`
121			`if (vsenable == 1) begin`
122			`vc <= vc + 1;`
123			`end`
124			`if (vc < 480) begin`
125			`VGA_VS <= 1;`
126			`end`
127			`else if (vc < 480 + 11) begin`
128			`VGA_VS <= 1;`
129			`end`
130			`else if (vc < 480 + 11 + 2) begin`
131			`VGA_VS <= 0;`
132			`end`
133			`else if (vc < 480 + 11 + 2 + 31) begin`
134			`VGA_VS <= 1;`
135			`end`
136			`else begin`
137			`vc <= 0;`
138			`VGA_VS <= 1;`
139			`end`
140			`end`
141			`end`
142
143			`always @ (posedge clk_25)`
144			`begin`
145			`if (vidon == 1) begin`
146	225	gabrielosh	`if (hc < 40) begin`
147			`if (vert_counter < 10) begin`
148			`/VGA_R[0] <= line[hc12];`
149			`VGA_R[1] <= line[hc*12+1];`
150			`VGA_R[2] <= line[hc*12+2];`
151			`VGA_R[3] <= line[hc*12+3];`
152			`VGA_G[0] <= line[hc*12+4];`
153			`VGA_G[1] <= line[hc*12+5];`
154			`VGA_G[2] <= line[hc*12+6];`
155			`VGA_G[3] <= line[hc*12+7];`
156			`VGA_B[0] <= line[hc*12+8];`
157			`VGA_B[1] <= line[hc*12+9];`
158			`VGA_B[2] <= line[hc*12+10];`
159			`VGA_B[3] <= line[hc12+11];/`
160	221	creep	`VGA_R[0] <= 1;`
161	225	gabrielosh	`VGA_R[1] <= 0;`
162			`VGA_R[2] <= 1;`
163			`VGA_R[3] <= 0;`
164	221	creep	`VGA_G[0] <= 1;`
165	225	gabrielosh	`VGA_G[1] <= 0;`
166			`VGA_G[2] <= 1;`
167			`VGA_G[3] <= 0;`
168	221	creep	`VGA_B[0] <= 1;`
169	225	gabrielosh	`VGA_B[1] <= 0;`
170			`VGA_B[2] <= 1;`
171			`VGA_B[3] <= 0;`
172			`end`
173			`else begin`
174			`VGA_R[0] <= 0;`
175			`VGA_G[0] <= 0;`
176			`VGA_B[0] <= 0;`
177			`VGA_R[1] <= 0;`
178			`VGA_G[1] <= 0;`
179			`VGA_B[1] <= 0;`
180			`VGA_R[2] <= 0;`
181			`VGA_G[2] <= 0;`
182			`VGA_B[2] <= 0;`
183			`VGA_R[3] <= 0;`
184			`VGA_G[3] <= 0;`
185			`VGA_B[3] <= 0;`
186			`end`
187			`end`
188			`else begin`
189			`VGA_R[0] <= 0;`
190			`VGA_G[0] <= 0;`
191			`VGA_B[0] <= 0;`
192			`VGA_R[1] <= 0;`
193			`VGA_G[1] <= 0;`
194			`VGA_B[1] <= 0;`
195			`VGA_R[2] <= 0;`
196			`VGA_G[2] <= 0;`
197			`VGA_B[2] <= 0;`
198			`VGA_R[3] <= 0;`
199			`VGA_G[3] <= 0;`
200			`VGA_B[3] <= 0;`
201			`end`
202
203			`/* if (vc < 240) begin`
204			`VGA_R[0] <= 1;`
205			`VGA_G[0] <= 1;`
206			`VGA_B[0] <= 1;`
207	221	creep	`VGA_R[1] <= 1;`
208			`VGA_G[1] <= 1;`
209			`VGA_B[1] <= 1;`
210			`VGA_R[2] <= 1;`
211			`VGA_G[2] <= 1;`
212			`VGA_B[2] <= 1;`
213			`VGA_R[3] <= 1;`
214			`VGA_G[3] <= 1;`
215			`VGA_B[3] <= 1;`
216			`end`
217			`else begin`
218			`VGA_R[0] <= 0;`
219			`VGA_G[0] <= 0;`
220			`VGA_B[0] <= 1;`
221			`VGA_R[1] <= 0;`
222			`VGA_G[1] <= 0;`
223			`VGA_B[1] <= 1;`
224			`VGA_R[2] <= 0;`
225			`VGA_G[2] <= 0;`
226			`VGA_B[2] <= 1;`
227			`VGA_R[3] <= 0;`
228			`VGA_G[3] <= 0;`
229			`VGA_B[3] <= 1;`
230			`end`
231			`end`
232			`else begin`
233			`if (vc < 240) begin`
234			`VGA_R[0] <= 1;`
235			`VGA_G[0] <= 0;`
236			`VGA_B[0] <= 0;`
237			`VGA_R[1] <= 1;`
238			`VGA_G[1] <= 0;`
239			`VGA_B[1] <= 0;`
240			`VGA_R[2] <= 1;`
241			`VGA_G[2] <= 0;`
242			`VGA_B[2] <= 0;`
243			`VGA_R[3] <= 1;`
244			`VGA_G[3] <= 0;`
245			`VGA_B[3] <= 0;`
246			`end`
247			`else begin`
248			`VGA_R[0] <= 0;`
249			`VGA_G[0] <= 1;`
250			`VGA_B[0] <= 0;`
251			`VGA_R[1] <= 0;`
252			`VGA_G[1] <= 1;`
253			`VGA_B[1] <= 0;`
254			`VGA_R[2] <= 0;`
255			`VGA_G[2] <= 1;`
256			`VGA_B[2] <= 0;`
257			`VGA_R[3] <= 0;`
258			`VGA_G[3] <= 1;`
259			`VGA_B[3] <= 0;`
260			`end`
261			`end`
262			`end`
263	225	gabrielosh	`*/`
264			`end`
265	221	creep	`else begin`
266			`VGA_R[0] <= 0;`
267			`VGA_G[0] <= 0;`
268			`VGA_B[0] <= 0;`
269			`VGA_R[1] <= 0;`
270			`VGA_G[1] <= 0;`
271			`VGA_B[1] <= 0;`
272			`VGA_R[2] <= 0;`
273			`VGA_G[2] <= 0;`
274			`VGA_B[2] <= 0;`
275			`VGA_R[3] <= 0;`
276			`VGA_G[3] <= 0;`
277			`VGA_B[3] <= 0;`
278			`end`
279	225	gabrielosh
280	221	creep	`end`
281
282			`assign vidon = (hc < 640 && vc < 480) ? 1 : 0;`
283
284			`endmodule`

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