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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Blame information for rev 247

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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// VGA controller                                                     ////
////                                                                    ////
//// TODO:                                                              ////
//// - Feed the controller with data                                    ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module vga_controller ( reset_n, clk_50, pixel, read_data, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, read_addr);
 
input reset_n;
input clk_50;
input [8:0] SW;
input [2:0] pixel;
input [2:0] read_data;
output reg [3:0] VGA_R;
output reg [3:0] VGA_G;
output reg [3:0] VGA_B;
output [9:0] LEDR;
output reg VGA_VS;
output reg VGA_HS;
output reg [10:0] read_addr;
 
reg clk_25;
reg [9:0] hc;
reg [9:0] vc;
reg vsenable;
wire vidon;
 
reg [11:0] vid_data;
 
assign LEDR[8:0] = SW;
assign LEDR[9] = reset_n;
 
always @ (posedge clk_50 or negedge reset_n)
begin
        if (!reset_n) begin
                clk_25 <= 0;
        end
        else begin
                clk_25 <= !clk_25;
        end
end
 
always @ (posedge clk_25 or negedge reset_n)
begin
        if (!reset_n) begin
                hc <= 0;
                VGA_HS <= 1;
                vsenable <= 0;
        end
        else if (hc < 640) begin
                hc <= hc + 1;
                vsenable <= 0;
                VGA_HS <= 1;
        end
        else if (hc < 640 + 16) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96) begin
                VGA_HS <= 0;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else if (hc < 640 + 16 + 96 + 48) begin
                VGA_HS <= 1;
                hc <= hc + 1;
                vsenable <= 0;
        end
        else begin
                VGA_HS <= 1;
                hc <= 0;
                vsenable <= 1;
        end
end
 
always @ (posedge clk_25 or negedge reset_n)
begin
        if (!reset_n) begin
                vc <= 0;
                VGA_VS <= 1;
        end
        else begin
                if (vsenable == 1) begin
                        vc <= vc + 1;
                end
                if (vc < 480) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11) begin
                        VGA_VS <= 1;
                end
                else if (vc < 480 + 11 + 2) begin
                        VGA_VS <= 0;
                end
                else if (vc < 480 + 11 + 2 + 31) begin
                        VGA_VS <= 1;
                end
                else begin
                        vc <= 0;
                        VGA_VS <= 1;
                end
        end
end
 
always @ (posedge clk_25) begin
        //if (reset_n == 1'b0) begin
                VGA_R[0] <= 0;
                VGA_G[0] <= 0;
                VGA_B[0] <= 0;
                VGA_R[1] <= 0;
                VGA_G[1] <= 0;
                VGA_B[1] <= 0;
                VGA_R[2] <= 0;
                VGA_G[2] <= 0;
                VGA_B[2] <= 0;
                VGA_R[3] <= 0;
                VGA_G[3] <= 0;
                VGA_B[3] <= 0;
        //end
        //else
        if (vidon == 1) begin
                if (hc < 480 && vc < 400) begin
                        VGA_R[0] <= vid_data[0];
                        VGA_R[1] <= vid_data[1];
                        VGA_R[2] <= vid_data[2];
                        VGA_R[3] <= vid_data[3];
                        VGA_G[0] <= vid_data[4];
                        VGA_G[1] <= vid_data[5];
                        VGA_G[2] <= vid_data[6];
                        VGA_G[3] <= vid_data[7];
                        VGA_B[0] <= vid_data[8];
                        VGA_B[1] <= vid_data[9];
                        VGA_B[2] <= vid_data[10];
                        VGA_B[3] <= vid_data[11];
                end
        end
end
 
always @ (*) begin
        if (hc < 400 && vc < 480) begin
                read_addr = hc/10 + (vc/10)*48;
 
                //case (read_data)
                //      default: begin
                                vid_data = 12'd10;
                //      end
                //endcase
        end
        else begin
                read_addr = 10'd0;
                vid_data = 12'b101010101010;
        end
 
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
 
endmodule

Line No.	Rev	Author	Line
1	221	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// VGA controller ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Feed the controller with data ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	233	creep	`module vga_controller ( reset_n, clk_50, pixel, read_data, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, read_addr);`
48	221	creep
49	227	creep	`input reset_n;`
50	223	gabrielosh	`input clk_50;`
51	224	creep	`input [8:0] SW;`
52	233	creep	`input [2:0] pixel;`
53			`input [2:0] read_data;`
54	223	gabrielosh	`output reg [3:0] VGA_R;`
55			`output reg [3:0] VGA_G;`
56			`output reg [3:0] VGA_B;`
57			`output [9:0] LEDR;`
58			`output reg VGA_VS;`
59			`output reg VGA_HS;`
60	233	creep	`output reg [10:0] read_addr;`
61	222	creep
62	221	creep	`reg clk_25;`
63			`reg [9:0] hc;`
64			`reg [9:0] vc;`
65			`reg vsenable;`
66			`wire vidon;`
67
68	233	creep	`reg [11:0] vid_data;`
69
70	225	gabrielosh	`assign LEDR[8:0] = SW;`
71	227	creep	`assign LEDR[9] = reset_n;`
72	221	creep
73	227	creep	`always @ (posedge clk_50 or negedge reset_n)`
74	221	creep	`begin`
75	227	creep	`if (!reset_n) begin`
76	221	creep	`clk_25 <= 0;`
77			`end`
78			`else begin`
79			`clk_25 <= !clk_25;`
80			`end`
81			`end`
82
83	227	creep	`always @ (posedge clk_25 or negedge reset_n)`
84	221	creep	`begin`
85	227	creep	`if (!reset_n) begin`
86	221	creep	`hc <= 0;`
87			`VGA_HS <= 1;`
88			`vsenable <= 0;`
89			`end`
90			`else if (hc < 640) begin`
91			`hc <= hc + 1;`
92			`vsenable <= 0;`
93			`VGA_HS <= 1;`
94			`end`
95			`else if (hc < 640 + 16) begin`
96			`VGA_HS <= 1;`
97			`hc <= hc + 1;`
98			`vsenable <= 0;`
99			`end`
100			`else if (hc < 640 + 16 + 96) begin`
101			`VGA_HS <= 0;`
102			`hc <= hc + 1;`
103			`vsenable <= 0;`
104			`end`
105			`else if (hc < 640 + 16 + 96 + 48) begin`
106			`VGA_HS <= 1;`
107			`hc <= hc + 1;`
108			`vsenable <= 0;`
109			`end`
110			`else begin`
111			`VGA_HS <= 1;`
112			`hc <= 0;`
113			`vsenable <= 1;`
114			`end`
115			`end`
116
117	227	creep	`always @ (posedge clk_25 or negedge reset_n)`
118	221	creep	`begin`
119	227	creep	`if (!reset_n) begin`
120	221	creep	`vc <= 0;`
121			`VGA_VS <= 1;`
122			`end`
123			`else begin`
124			`if (vsenable == 1) begin`
125			`vc <= vc + 1;`
126			`end`
127			`if (vc < 480) begin`
128			`VGA_VS <= 1;`
129			`end`
130			`else if (vc < 480 + 11) begin`
131			`VGA_VS <= 1;`
132			`end`
133			`else if (vc < 480 + 11 + 2) begin`
134			`VGA_VS <= 0;`
135			`end`
136			`else if (vc < 480 + 11 + 2 + 31) begin`
137			`VGA_VS <= 1;`
138			`end`
139			`else begin`
140			`vc <= 0;`
141			`VGA_VS <= 1;`
142			`end`
143			`end`
144			`end`
145
146	233	creep	`always @ (posedge clk_25) begin`
147			`//if (reset_n == 1'b0) begin`
148			`VGA_R[0] <= 0;`
149			`VGA_G[0] <= 0;`
150			`VGA_B[0] <= 0;`
151			`VGA_R[1] <= 0;`
152			`VGA_G[1] <= 0;`
153			`VGA_B[1] <= 0;`
154			`VGA_R[2] <= 0;`
155			`VGA_G[2] <= 0;`
156			`VGA_B[2] <= 0;`
157			`VGA_R[3] <= 0;`
158			`VGA_G[3] <= 0;`
159			`VGA_B[3] <= 0;`
160			`//end`
161			`//else`
162			`if (vidon == 1) begin`
163			`if (hc < 480 && vc < 400) begin`
164			`VGA_R[0] <= vid_data[0];`
165			`VGA_R[1] <= vid_data[1];`
166			`VGA_R[2] <= vid_data[2];`
167			`VGA_R[3] <= vid_data[3];`
168			`VGA_G[0] <= vid_data[4];`
169			`VGA_G[1] <= vid_data[5];`
170			`VGA_G[2] <= vid_data[6];`
171			`VGA_G[3] <= vid_data[7];`
172			`VGA_B[0] <= vid_data[8];`
173			`VGA_B[1] <= vid_data[9];`
174			`VGA_B[2] <= vid_data[10];`
175			`VGA_B[3] <= vid_data[11];`
176			`end`
177			`end`
178			`end`
179	232	creep
180	233	creep	`always @ (*) begin`
181			`if (hc < 400 && vc < 480) begin`
182			`read_addr = hc/10 + (vc/10)*48;`
183
184			`//case (read_data)`
185			`// default: begin`
186			`vid_data = 12'd10;`
187			`// end`
188			`//endcase`
189	232	creep	`end`
190			`else begin`
191	233	creep	`read_addr = 10'd0;`
192			`vid_data = 12'b101010101010;`
193	232	creep	`end`
194	233	creep
195	232	creep	`end`
196
197	221	creep	`assign vidon = (hc < 640 && vc < 480) ? 1 : 0;`
198
199			`endmodule`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Blame information for rev 247