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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [video.v] - Blame information for rev 215

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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// Video module                                                       ////
////                                                                    ////
//// TODO:                                                              ////
//// - Everything?                                                      ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module video(clk, reset_n, io_lines, enable, mem_rw, address, data);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
 
        input clk; // master clock signal, 1.19mhz
        input reset_n;
        input [15:0] io_lines; // inputs from the keyboard controller
        input enable; // since the address bus is shared an enable signal is used
        input mem_rw; // read == 0, write == 1
        input [ADDR_SIZE_:0] address; // system address bus
        inout [DATA_SIZE_:0] data; // controler <=> riot data bus
 
        reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
 
        assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data. 
 
        reg VSYNC; // vertical sync set-clear
        reg VBLANK; //  1 1 1 vertical blank set-clear
        reg WSYNC; //  s t r o b e wait for leading edge of horizontal blank
        reg RSYNC; //  s t r o b e reset horizontal sync counter
        reg NUSIZ0; //  1 1 1 1 1 1 number-size player-missile 0
        reg NUSIZ1; //  1 1 1 1 1 1 number-size player-missile 1
        reg COLUP0; //  1 1 1 1 1 1 1 color-lum player 0
        reg COLUP1; //  1 1 1 1 1 1 1 color-lum player 1
        reg COLUPF; //  1 1 1 1 1 1 1 color-lum playfield
        reg COLUBK; //  1 1 1 1 1 1 1 color-lum background
        reg CTRLPF; //  1 1 1 1 1 control playfield ball size & collisions
        reg REFP0; //  1 reflect player 0
        reg REFP1; //  1 reflect player 1
        reg PF0; //  1 1 1 1 playfield register byte 0
        reg PF1; //  1 1 1 1 1 1 1 1 playfield register byte 1
        reg PF2; //  1 1 1 1 1 1 1 1 playfield register byte 2
        reg RESP0; //  s t r o b e reset player 0
        reg RESP1; //  s t r o b e reset player 1
        reg RESM0; //  s t r o b e reset missile 0
        reg RESM1; //  s t r o b e reset missile 1
        reg RESBL; //  s t r o b e reset ball
        reg AUDC0; //  1 1 1 1 audio control 0
        reg AUDC1; //  1 1 1 1 1 audio control 1
        reg AUDF0; //  1 1 1 1 1 audio frequency 0
        reg AUDF1; //  1 1 1 1 audio frequency 1
        reg AUDV0; //  1 1 1 1 audio volume 0
        reg AUDV1; //  1 1 1 1 audio volume 1
        reg GRP0; //  1 1 1 1 1 1 1 1 graphics player 0
        reg GRP1; //  1 1 1 1 1 1 1 1 graphics player 1
        reg ENAM0; //  1 graphics (enable) missile 0
        reg ENAM1; //  1 graphics (enable) missile 1
        reg ENABL; //  1 graphics (enable) ball
        reg HMP0; //  1 1 1 1 horizontal motion player 0
        reg HMP1; //  1 1 1 1 horizontal motion player 1
        reg HMM0; //  1 1 1 1 horizontal motion missile 0
        reg HMM1; //  1 1 1 1 horizontal motion missile 1
        reg HMBL; //  1 1 1 1 horizontal motion ball
        reg VDELP0; //  1 vertical delay player 0
        reg VDEL01; //  1 vertical delay player 1
        reg VDELBL; //  1 vertical delay ball
        reg RESMP0; //  1 reset missile 0 to player 0
        reg RESMP1; //  1 reset missile 1 to player 1
        reg HMOVE; //  s t r o b e apply horizontal motion
        reg HMCLR; //  s t r o b e clear horizontal motion registers
        reg CXCLR ; // s t r o b e clear collision latches 
 
        always @(posedge clk  or negedge reset_n) begin // R/W register/memory handling
                if (reset_n == 1'b0) begin
                        data_drv <= 8'h00;
                end
                else begin
                        if (reading) begin // reading! 
                                case (address)
                                        10'h280: data_drv <= port_a;
                                        10'h281: data_drv <= ddra;
                                        10'h282: data_drv <= port_b;
                                        10'h283: data_drv <= 8'h00; // portb ddr is always input
                                        10'h284: data_drv <= timer;
                                        default: data_drv <= ram[address];
                                endcase
                        end
                        else if (writing) begin // writing! 
                                case (address)
                                        10'h281: begin
                                                ddra <= data;
                                        end
                                        10'h294: begin
                                                c1_timer <= 1'b1;
                                                c8_timer <= 1'b0;
                                                c64_timer <= 1'b0;
                                                c1024_timer <= 1'b0;
                                                timer <= data;
                                                flipped <= 1'b0;
                                                counter <= 11'd1;
                                        end
                                        10'h295: begin
                                                c1_timer <= 1'b0;
                                                c8_timer <= 1'b1;
                                                c64_timer <= 1'b0;
                                                c1024_timer <= 1'b0;
                                                timer <= data;
                                                flipped <= 1'b0;
                                                counter <= 11'd7;
                                        end
                                        10'h296: begin
                                                c1_timer <= 1'b0;
                                                c8_timer <= 1'b0;
                                                c64_timer <= 1'b1;
                                                c1024_timer <= 1'b0;
                                                timer <= data;
                                                flipped <= 1'b0;
                                                counter <= 11'd63;
                                        end
                                        10'h297: begin
                                                c1_timer <= 1'b0;
                                                c8_timer <= 1'b0;
                                                c64_timer <= 1'b0;
                                                c1024_timer <= 1'b1;
                                                timer <= data;
                                                flipped <= 1'b0;
                                                counter <= 11'd1023;
                                        end
                                        default: begin
                                                ram[address] <= data;
                                        end
                                endcase
                        end
 
                        if (!writing_at_timer) begin
                                if (flipped || timer == 8'd0) begin // finished counting
                                        counter <= 11'd0;
                                        timer <= timer - 8'd1;
                                        flipped <= 1'b1;
                                end
                                else begin
                                        if (counter == 11'd0) begin
                                                timer <= timer - 8'd1;
 
                                                if (c1_timer) begin
                                                        counter <= 11'd0;
                                                end
                                                if (c8_timer) begin
                                                        counter <= 11'd7;
                                                end
                                                if (c64_timer) begin
                                                        counter <= 11'd63;
                                                end
                                                if (c1024_timer) begin
                                                        counter <= 11'd1023;
                                                end
                                        end
                                        else begin
                                                counter <= counter - 11'd1;
                                        end
                                end
                        end
                end
        end
 
        always @(*) begin // logic for easier controlling
                reading = 1'b0;
                writing = 1'b0;
                writing_at_timer = 1'b0;
 
                if (enable && reset_n) begin
                        if (mem_rw == 1'b0) begin
                                reading = 1'b1;
                        end
                        else begin
                                writing = 1'b1;
 
                                if ( (address == 10'h294) || (address == 10'h295) || (address == 10'h296) || (address == 10'h297) ) begin
                                        writing_at_timer = 1'b1;
                                end
                        end
                end
        end
 
endmodule
 

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [video.v] - Blame information for rev 215

Line No.	Rev	Author	Line
1	215	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Video module ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Everything? ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`module video(clk, reset_n, io_lines, enable, mem_rw, address, data);`
48			`parameter [3:0] DATA_SIZE = 4'd8;`
49			`parameter [3:0] ADDR_SIZE = 4'd10; // this is the local addr_size`
50
51			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;`
52			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;`
53
54			`input clk; // master clock signal, 1.19mhz`
55			`input reset_n;`
56			`input [15:0] io_lines; // inputs from the keyboard controller`
57			`input enable; // since the address bus is shared an enable signal is used`
58			`input mem_rw; // read == 0, write == 1`
59			`input [ADDR_SIZE_:0] address; // system address bus`
60			`inout [DATA_SIZE_:0] data; // controler <=> riot data bus`
61
62			`reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus`
63
64			`assign data = (mem_rw \|\| !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.`
65
66			`reg VSYNC; // vertical sync set-clear`
67			`reg VBLANK; // 1 1 1 vertical blank set-clear`
68			`reg WSYNC; // s t r o b e wait for leading edge of horizontal blank`
69			`reg RSYNC; // s t r o b e reset horizontal sync counter`
70			`reg NUSIZ0; // 1 1 1 1 1 1 number-size player-missile 0`
71			`reg NUSIZ1; // 1 1 1 1 1 1 number-size player-missile 1`
72			`reg COLUP0; // 1 1 1 1 1 1 1 color-lum player 0`
73			`reg COLUP1; // 1 1 1 1 1 1 1 color-lum player 1`
74			`reg COLUPF; // 1 1 1 1 1 1 1 color-lum playfield`
75			`reg COLUBK; // 1 1 1 1 1 1 1 color-lum background`
76			`reg CTRLPF; // 1 1 1 1 1 control playfield ball size & collisions`
77			`reg REFP0; // 1 reflect player 0`
78			`reg REFP1; // 1 reflect player 1`
79			`reg PF0; // 1 1 1 1 playfield register byte 0`
80			`reg PF1; // 1 1 1 1 1 1 1 1 playfield register byte 1`
81			`reg PF2; // 1 1 1 1 1 1 1 1 playfield register byte 2`
82			`reg RESP0; // s t r o b e reset player 0`
83			`reg RESP1; // s t r o b e reset player 1`
84			`reg RESM0; // s t r o b e reset missile 0`
85			`reg RESM1; // s t r o b e reset missile 1`
86			`reg RESBL; // s t r o b e reset ball`
87			`reg AUDC0; // 1 1 1 1 audio control 0`
88			`reg AUDC1; // 1 1 1 1 1 audio control 1`
89			`reg AUDF0; // 1 1 1 1 1 audio frequency 0`
90			`reg AUDF1; // 1 1 1 1 audio frequency 1`
91			`reg AUDV0; // 1 1 1 1 audio volume 0`
92			`reg AUDV1; // 1 1 1 1 audio volume 1`
93			`reg GRP0; // 1 1 1 1 1 1 1 1 graphics player 0`
94			`reg GRP1; // 1 1 1 1 1 1 1 1 graphics player 1`
95			`reg ENAM0; // 1 graphics (enable) missile 0`
96			`reg ENAM1; // 1 graphics (enable) missile 1`
97			`reg ENABL; // 1 graphics (enable) ball`
98			`reg HMP0; // 1 1 1 1 horizontal motion player 0`
99			`reg HMP1; // 1 1 1 1 horizontal motion player 1`
100			`reg HMM0; // 1 1 1 1 horizontal motion missile 0`
101			`reg HMM1; // 1 1 1 1 horizontal motion missile 1`
102			`reg HMBL; // 1 1 1 1 horizontal motion ball`
103			`reg VDELP0; // 1 vertical delay player 0`
104			`reg VDEL01; // 1 vertical delay player 1`
105			`reg VDELBL; // 1 vertical delay ball`
106			`reg RESMP0; // 1 reset missile 0 to player 0`
107			`reg RESMP1; // 1 reset missile 1 to player 1`
108			`reg HMOVE; // s t r o b e apply horizontal motion`
109			`reg HMCLR; // s t r o b e clear horizontal motion registers`
110			`reg CXCLR ; // s t r o b e clear collision latches`
111
112			`always @(posedge clk or negedge reset_n) begin // R/W register/memory handling`
113			`if (reset_n == 1'b0) begin`
114			`data_drv <= 8'h00;`
115			`end`
116			`else begin`
117			`if (reading) begin // reading!`
118			`case (address)`
119			`10'h280: data_drv <= port_a;`
120			`10'h281: data_drv <= ddra;`
121			`10'h282: data_drv <= port_b;`
122			`10'h283: data_drv <= 8'h00; // portb ddr is always input`
123			`10'h284: data_drv <= timer;`
124			`default: data_drv <= ram[address];`
125			`endcase`
126			`end`
127			`else if (writing) begin // writing!`
128			`case (address)`
129			`10'h281: begin`
130			`ddra <= data;`
131			`end`
132			`10'h294: begin`
133			`c1_timer <= 1'b1;`
134			`c8_timer <= 1'b0;`
135			`c64_timer <= 1'b0;`
136			`c1024_timer <= 1'b0;`
137			`timer <= data;`
138			`flipped <= 1'b0;`
139			`counter <= 11'd1;`
140			`end`
141			`10'h295: begin`
142			`c1_timer <= 1'b0;`
143			`c8_timer <= 1'b1;`
144			`c64_timer <= 1'b0;`
145			`c1024_timer <= 1'b0;`
146			`timer <= data;`
147			`flipped <= 1'b0;`
148			`counter <= 11'd7;`
149			`end`
150			`10'h296: begin`
151			`c1_timer <= 1'b0;`
152			`c8_timer <= 1'b0;`
153			`c64_timer <= 1'b1;`
154			`c1024_timer <= 1'b0;`
155			`timer <= data;`
156			`flipped <= 1'b0;`
157			`counter <= 11'd63;`
158			`end`
159			`10'h297: begin`
160			`c1_timer <= 1'b0;`
161			`c8_timer <= 1'b0;`
162			`c64_timer <= 1'b0;`
163			`c1024_timer <= 1'b1;`
164			`timer <= data;`
165			`flipped <= 1'b0;`
166			`counter <= 11'd1023;`
167			`end`
168			`default: begin`
169			`ram[address] <= data;`
170			`end`
171			`endcase`
172			`end`
173
174			`if (!writing_at_timer) begin`
175			`if (flipped \|\| timer == 8'd0) begin // finished counting`
176			`counter <= 11'd0;`
177			`timer <= timer - 8'd1;`
178			`flipped <= 1'b1;`
179			`end`
180			`else begin`
181			`if (counter == 11'd0) begin`
182			`timer <= timer - 8'd1;`
183
184			`if (c1_timer) begin`
185			`counter <= 11'd0;`
186			`end`
187			`if (c8_timer) begin`
188			`counter <= 11'd7;`
189			`end`
190			`if (c64_timer) begin`
191			`counter <= 11'd63;`
192			`end`
193			`if (c1024_timer) begin`
194			`counter <= 11'd1023;`
195			`end`
196			`end`
197			`else begin`
198			`counter <= counter - 11'd1;`
199			`end`
200			`end`
201			`end`
202			`end`
203			`end`
204
205			`always @(*) begin // logic for easier controlling`
206			`reading = 1'b0;`
207			`writing = 1'b0;`
208			`writing_at_timer = 1'b0;`
209
210			`if (enable && reset_n) begin`
211			`if (mem_rw == 1'b0) begin`
212			`reading = 1'b1;`
213			`end`
214			`else begin`
215			`writing = 1'b1;`
216
217			`if ( (address == 10'h294) \|\| (address == 10'h295) \|\| (address == 10'h296) \|\| (address == 10'h297) ) begin`
218			`writing_at_timer = 1'b1;`
219			`end`
220			`end`
221			`end`
222			`end`
223
224			`endmodule`
225