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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// Video module                                                       ////
////                                                                    ////
//// TODO:                                                              ////
//// - Everything?                                                      ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module video(clk, reset_n, io_lines, enable, mem_rw, address, data);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
 
        input clk; // master clock signal, 1.19mhz
        input reset_n;
        input [15:0] io_lines; // inputs from the keyboard controller
        input enable; // since the address bus is shared an enable signal is used
        input mem_rw; // read == 0, write == 1
        input [ADDR_SIZE_:0] address; // system address bus
        inout [DATA_SIZE_:0] data; // controler <=> riot data bus
 
        reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
 
        assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data. 
 
        reg VSYNC; // vertical sync set-clear
        reg [2:0] VBLANK; // vertical blank set-clear
        reg WSYNC; //  s t r o b e wait for leading edge of horizontal blank
        reg RSYNC; //  s t r o b e reset horizontal sync counter
        reg [5:0] NUSIZ0; //  number-size player-missile 0
        reg [5:0] NUSIZ1; //  number-size player-missile 1
        reg [6:0] COLUP0; //  color-lum player 0
        reg [6:0] COLUP1; //  color-lum player 1
        reg [6:0] COLUPF; //  color-lum playfield
        reg [6:0] COLUBK; //  color-lum background
        reg [4:0] CTRLPF; //  control playfield ball size & collisions
        reg REFP0; //  reflect player 0
        reg REFP1; //  reflect player 1
        reg [3:0] PF0; //  playfield register byte 0
        reg [7:0] PF1; //  playfield register byte 1
        reg [7:0] PF2; //  playfield register byte 2
        reg RESP0; //  s t r o b e reset player 0
        reg RESP1; //  s t r o b e reset player 1
        reg RESM0; //  s t r o b e reset missile 0
        reg RESM1; //  s t r o b e reset missile 1
        reg RESBL; //  s t r o b e reset ball
        reg [3:0] AUDC0; //  audio control 0
        reg [4:0] AUDC1; //  audio control 1
        reg [4:0] AUDF0; //  audio frequency 0
        reg [3:0] AUDF1; //  audio frequency 1
        reg [3:0] AUDV0; //  audio volume 0
        reg [3:0] AUDV1; //  audio volume 1
        reg [7:0] GRP0; //  graphics player 0
        reg [7:0] GRP1; //  graphics player 1
        reg ENAM0; //  graphics (enable) missile 0
        reg ENAM1; //  graphics (enable) missile 1
        reg ENABL; //  graphics (enable) ball
        reg [3:0] HMP0; //  horizontal motion player 0
        reg [3:0] HMP1; //  horizontal motion player 1
        reg [3:0] HMM0; //  horizontal motion missile 0
        reg [3:0] HMM1; //  horizontal motion missile 1
        reg [3:0] HMBL; //  horizontal motion ball
        reg VDELP0; //  vertical delay player 0
        reg VDEL01; //  vertical delay player 1
        reg VDELBL; //  vertical delay ball
        reg RESMP0; //  reset missile 0 to player 0
        reg RESMP1; //  reset missile 1 to player 1
        reg HMOVE; //  s t r o b e apply horizontal motion
        reg HMCLR; //  s t r o b e clear horizontal motion registers
        reg CXCLR ; // s t r o b e clear collision latches
 
        reg [1:0] CXM0P; // read collision MO P1 M0 P0
        reg [1:0] CXM1P; // read collision M1 P0 M1 P1
        reg [1:0] CXP0FB; // read collision P0 PF P0 BL
        reg [1:0] CXP1FB; // read collision P1 PF P1 BL
        reg [1:0] CXM0FB; // read collision M0 PF M0 BL
        reg [1:0] CXM1FB; // read collision M1 PF M1 BL
        reg CXBLPF; // read collision BL PF unused
        reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
        reg INPT0; // read pot port
        reg INPT1; // read pot port
        reg INPT2; // read pot port
        reg INPT3; // read pot port
        reg INPT4; // read input
        reg INPT5; // read input 
 
        always @(posedge clk  or negedge reset_n) begin
                if (reset_n == 1'b0) begin
                        data_drv <= 8'h00;
                end
                else begin
                        if (mem_rw == 1'b0) begin // reading! 
                                case (address)
                                        6'h00: data_drv <= {CXM0P, 6'b000000};
                                        6'h01: data_drv <= {CXM1P, 6'b000000};
                                        6'h02: data_drv <= {CXP0FB, 6'b000000};
                                        6'h03: data_drv <= {CXP1FB, 6'b000000};
                                        6'h04: data_drv <= {CXM0FB, 6'b000000};
                                        6'h05: data_drv <= {CXM1FB, 6'b000000};
                                        6'h06: data_drv <= {CXBLPF, 7'b000000};
                                        6'h07: data_drv <= {CXPPMM, 6'b000000};
                                        6'h08: data_drv <= {INPT0, 7'b000000};
                                        6'h09: data_drv <= {INPT1, 7'b000000};
                                        6'h0A: data_drv <= {INPT2, 7'b000000};
                                        6'h0B: data_drv <= {INPT3, 7'b000000};
                                        6'h0C: data_drv <= {INPT4, 7'b000000};
                                        6'h0D: data_drv <= {INPT5, 7'b000000};
                                        default: ;
                                endcase
                        end
                        else begin // writing! 
                                case (address)
                                        6'h00: begin
                                                VSYNC <= data;
                                        end
                                        6'h01: begin
                                                VBLANK <= data;
                                        end
                                        6'h02: begin
                                                WSYNC <= data;
                                        end
                                        6'h03: begin
                                                RSYNC <= data;
                                        end
                                        6'h04: begin
                                                NUSIZ0 <= data;
                                        end
                                        6'h05: begin
                                                NUSIZ1 <= data;
                                        end
                                        6'h06: begin
                                                COLUP0 <= data;
                                        end
                                        6'h07: begin
                                                COLUP1 <= data;
                                        end
                                        6'h08: begin
                                                COLUPF <= data;
                                        end
                                        6'h09: begin
                                                COLUBK <= data;
                                        end
                                        6'h0a: begin
                                                CTRLPF <= data;
                                        end
                                        6'h0b: begin
                                                NUSIZ1 <= data;
                                        end
                                        6'h0c: begin
                                                NUSIZ1 <= data;
                                        end
                                        default: begin
                                        end
                                endcase
                        end
                end
        end
 
endmodule
 

Line No.	Rev	Author	Line
1	215	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Video module ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Everything? ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`module video(clk, reset_n, io_lines, enable, mem_rw, address, data);`
48			`parameter [3:0] DATA_SIZE = 4'd8;`
49			`parameter [3:0] ADDR_SIZE = 4'd10; // this is the local addr_size`
50
51			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;`
52			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;`
53
54			`input clk; // master clock signal, 1.19mhz`
55			`input reset_n;`
56			`input [15:0] io_lines; // inputs from the keyboard controller`
57			`input enable; // since the address bus is shared an enable signal is used`
58			`input mem_rw; // read == 0, write == 1`
59			`input [ADDR_SIZE_:0] address; // system address bus`
60			`inout [DATA_SIZE_:0] data; // controler <=> riot data bus`
61
62			`reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus`
63
64			`assign data = (mem_rw \|\| !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.`
65
66			`reg VSYNC; // vertical sync set-clear`
67	216	creep	`reg [2:0] VBLANK; // vertical blank set-clear`
68	215	creep	`reg WSYNC; // s t r o b e wait for leading edge of horizontal blank`
69			`reg RSYNC; // s t r o b e reset horizontal sync counter`
70	216	creep	`reg [5:0] NUSIZ0; // number-size player-missile 0`
71			`reg [5:0] NUSIZ1; // number-size player-missile 1`
72			`reg [6:0] COLUP0; // color-lum player 0`
73			`reg [6:0] COLUP1; // color-lum player 1`
74			`reg [6:0] COLUPF; // color-lum playfield`
75			`reg [6:0] COLUBK; // color-lum background`
76			`reg [4:0] CTRLPF; // control playfield ball size & collisions`
77			`reg REFP0; // reflect player 0`
78			`reg REFP1; // reflect player 1`
79			`reg [3:0] PF0; // playfield register byte 0`
80			`reg [7:0] PF1; // playfield register byte 1`
81			`reg [7:0] PF2; // playfield register byte 2`
82	215	creep	`reg RESP0; // s t r o b e reset player 0`
83			`reg RESP1; // s t r o b e reset player 1`
84			`reg RESM0; // s t r o b e reset missile 0`
85			`reg RESM1; // s t r o b e reset missile 1`
86			`reg RESBL; // s t r o b e reset ball`
87	216	creep	`reg [3:0] AUDC0; // audio control 0`
88			`reg [4:0] AUDC1; // audio control 1`
89			`reg [4:0] AUDF0; // audio frequency 0`
90			`reg [3:0] AUDF1; // audio frequency 1`
91			`reg [3:0] AUDV0; // audio volume 0`
92			`reg [3:0] AUDV1; // audio volume 1`
93			`reg [7:0] GRP0; // graphics player 0`
94			`reg [7:0] GRP1; // graphics player 1`
95			`reg ENAM0; // graphics (enable) missile 0`
96			`reg ENAM1; // graphics (enable) missile 1`
97			`reg ENABL; // graphics (enable) ball`
98			`reg [3:0] HMP0; // horizontal motion player 0`
99			`reg [3:0] HMP1; // horizontal motion player 1`
100			`reg [3:0] HMM0; // horizontal motion missile 0`
101			`reg [3:0] HMM1; // horizontal motion missile 1`
102			`reg [3:0] HMBL; // horizontal motion ball`
103			`reg VDELP0; // vertical delay player 0`
104			`reg VDEL01; // vertical delay player 1`
105			`reg VDELBL; // vertical delay ball`
106			`reg RESMP0; // reset missile 0 to player 0`
107			`reg RESMP1; // reset missile 1 to player 1`
108	215	creep	`reg HMOVE; // s t r o b e apply horizontal motion`
109			`reg HMCLR; // s t r o b e clear horizontal motion registers`
110	216	creep	`reg CXCLR ; // s t r o b e clear collision latches`
111	215	creep
112	216	creep	`reg [1:0] CXM0P; // read collision MO P1 M0 P0`
113			`reg [1:0] CXM1P; // read collision M1 P0 M1 P1`
114			`reg [1:0] CXP0FB; // read collision P0 PF P0 BL`
115			`reg [1:0] CXP1FB; // read collision P1 PF P1 BL`
116			`reg [1:0] CXM0FB; // read collision M0 PF M0 BL`
117			`reg [1:0] CXM1FB; // read collision M1 PF M1 BL`
118			`reg CXBLPF; // read collision BL PF unused`
119			`reg [1:0] CXPPMM; // read collision P0 P1 M0 M1`
120			`reg INPT0; // read pot port`
121			`reg INPT1; // read pot port`
122			`reg INPT2; // read pot port`
123			`reg INPT3; // read pot port`
124			`reg INPT4; // read input`
125			`reg INPT5; // read input`
126
127			`always @(posedge clk or negedge reset_n) begin`
128	215	creep	`if (reset_n == 1'b0) begin`
129			`data_drv <= 8'h00;`
130			`end`
131			`else begin`
132	216	creep	`if (mem_rw == 1'b0) begin // reading!`
133	215	creep	`case (address)`
134	216	creep	`6'h00: data_drv <= {CXM0P, 6'b000000};`
135			`6'h01: data_drv <= {CXM1P, 6'b000000};`
136			`6'h02: data_drv <= {CXP0FB, 6'b000000};`
137			`6'h03: data_drv <= {CXP1FB, 6'b000000};`
138			`6'h04: data_drv <= {CXM0FB, 6'b000000};`
139			`6'h05: data_drv <= {CXM1FB, 6'b000000};`
140			`6'h06: data_drv <= {CXBLPF, 7'b000000};`
141			`6'h07: data_drv <= {CXPPMM, 6'b000000};`
142			`6'h08: data_drv <= {INPT0, 7'b000000};`
143			`6'h09: data_drv <= {INPT1, 7'b000000};`
144			`6'h0A: data_drv <= {INPT2, 7'b000000};`
145			`6'h0B: data_drv <= {INPT3, 7'b000000};`
146			`6'h0C: data_drv <= {INPT4, 7'b000000};`
147			`6'h0D: data_drv <= {INPT5, 7'b000000};`
148			`default: ;`
149	215	creep	`endcase`
150			`end`
151	216	creep	`else begin // writing!`
152	215	creep	`case (address)`
153	216	creep	`6'h00: begin`
154			`VSYNC <= data;`
155	215	creep	`end`
156	216	creep	`6'h01: begin`
157			`VBLANK <= data;`
158	215	creep	`end`
159	216	creep	`6'h02: begin`
160			`WSYNC <= data;`
161	215	creep	`end`
162	216	creep	`6'h03: begin`
163			`RSYNC <= data;`
164	215	creep	`end`
165	216	creep	`6'h04: begin`
166			`NUSIZ0 <= data;`
167			`end`
168			`6'h05: begin`
169			`NUSIZ1 <= data;`
170			`end`
171			`6'h06: begin`
172			`COLUP0 <= data;`
173			`end`
174			`6'h07: begin`
175			`COLUP1 <= data;`
176			`end`
177			`6'h08: begin`
178			`COLUPF <= data;`
179			`end`
180			`6'h09: begin`
181			`COLUBK <= data;`
182			`end`
183			`6'h0a: begin`
184			`CTRLPF <= data;`
185			`end`
186			`6'h0b: begin`
187			`NUSIZ1 <= data;`
188			`end`
189			`6'h0c: begin`
190			`NUSIZ1 <= data;`
191			`end`
192	215	creep	`default: begin`
193			`end`
194			`endcase`
195			`end`
196			`end`
197			`end`
198
199			`endmodule`
200

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [video.v] - Blame information for rev 216