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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// Video module                                                       ////
////                                                                    ////
//// TODO:                                                              ////
//// - Collision detection                                              ////
//// - Pixel output                                                     ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel, write_addr, write_data, write_enable_n);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
 
        input clk; // master clock signal, 1.19mhz
        input reset_n;
        input [15:0] io_lines; // inputs from the keyboard controller
        input enable; // since the address bus is shared an enable signal is used
        input mem_rw; // read == 0, write == 1
        input [ADDR_SIZE_:0] address; // system address bus
        inout [DATA_SIZE_:0] data; // controler <=> video data bus
        output reg [2:0] pixel;
        output reg [10:0] write_addr; // for the video memory
        output reg [2:0] write_data;
        output reg write_enable_n;
 
        reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
 
        assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data. 
 
        reg VSYNC; // vertical sync set-clear
        reg [2:0] VBLANK; // vertical blank set-clear
        reg WSYNC; //  SEMI-strobe wait for leading edge of horizontal blank
        reg RSYNC; //  s t r o b e reset horizontal sync counter
        reg [5:0] NUSIZ0; //  number-size player-missile 0
        reg [5:0] NUSIZ1; //  number-size player-missile 1
        reg [6:0] COLUP0; //  color-lum player 0
        reg [6:0] COLUP1; //  color-lum player 1
        reg [6:0] COLUPF; //  color-lum playfield
        reg [6:0] COLUBK; //  color-lum background
        reg [4:0] CTRLPF; //  control playfield ball size & collisions
                // D0 = REF (reflect playfield)
                // D1 = SCORE (left half of playfield gets color of player 0, right half gets color of player 1)
                // D2 = PFP (playfield gets priority over players so they can move behind the playfield)
                // D4 & D5 = BALL SIZE
        reg REFP0; //  reflect player 0
        reg REFP1; //  reflect player 1
        reg [3:0] PF0; //  playfield register byte 0
        reg [7:0] PF1; //  playfield register byte 1
        reg [7:0] PF2; //  playfield register byte 2
        //reg RESP0; //  s t r o b e reset player 0
        reg RESP1; //  s t r o b e reset player 1
        reg RESM0; //  s t r o b e reset missile 0
        reg RESM1; //  s t r o b e reset missile 1
        reg RESBL; //  s t r o b e reset ball
        reg [3:0] AUDC0; //  audio control 0
        reg [4:0] AUDC1; //  audio control 1
        reg [4:0] AUDF0; //  audio frequency 0
        reg [3:0] AUDF1; //  audio frequency 1
        reg [3:0] AUDV0; //  audio volume 0
        reg [3:0] AUDV1; //  audio volume 1
        reg [7:0] GRP0; //  graphics player 0
        reg [7:0] GRP1; //  graphics player 1
        reg ENAM0; //  graphics (enable) missile 0
        reg ENAM1; //  graphics (enable) missile 1
        reg ENABL; //  graphics (enable) ball
        reg [3:0] HMP0; //  horizontal motion player 0
        reg [3:0] HMP1; //  horizontal motion player 1
        reg [3:0] HMM0; //  horizontal motion missile 0
        reg [3:0] HMM1; //  horizontal motion missile 1
        reg [3:0] HMBL; //  horizontal motion ball
        reg VDELP0; //  vertical delay player 0
        reg VDEL01; //  vertical delay player 1
        reg VDELBL; //  vertical delay ball
        reg RESMP0; //  reset missile 0 to player 0
        reg RESMP1; //  reset missile 1 to player 1
        reg HMOVE; //  s t r o b e apply horizontal motion
        reg HMCLR; //  s t r o b e clear horizontal motion registers
 
        reg [1:0] CXM0P; // read collision MO P1 M0 P0
        reg [1:0] CXM1P; // read collision M1 P0 M1 P1
        reg [1:0] CXP0FB; // read collision P0 PF P0 BL
        reg [1:0] CXP1FB; // read collision P1 PF P1 BL
        reg [1:0] CXM0FB; // read collision M0 PF M0 BL
        reg [1:0] CXM1FB; // read collision M1 PF M1 BL
        reg CXBLPF; // read collision BL PF unused
        reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
        reg INPT0; // read pot port
        reg INPT1; // read pot port
        reg INPT2; // read pot port
        reg INPT3; // read pot port
        reg INPT4; // read input
        reg INPT5; // read input
 
        reg [8:0] vert_counter;
        reg [7:0] hor_counter;
 
        always @(posedge clk  or negedge reset_n) begin
                if (reset_n == 1'b0) begin
                        hor_counter <= 8'd0;
                        vert_counter <= 9'd0;
                end
                else begin
                        if (hor_counter == 8'd227) begin
                                hor_counter <= 8'd0;
                                WSYNC <= 1'b0; // TODO: check this on stella pdf
 
                                if (vert_counter == 9'd261) begin
                                        vert_counter <= 9'd0;
                                end
                                else begin
                                        vert_counter <= vert_counter + 9'd1;
                                end
                        end
                        else begin
                                hor_counter <= hor_counter + 6'd1;
                        end
                end
        end
 
        always @(posedge clk  or negedge reset_n) begin
                if (reset_n == 1'b0) begin
                        data_drv <= 8'h00;
                        WSYNC <= 1'b0;
                end
                else if (enable == 1'b1) begin
                        if (mem_rw == 1'b0) begin // reading! 
                                case (address)
                                        6'h00: data_drv <= {CXM0P, 6'b000000};
                                        6'h01: data_drv <= {CXM1P, 6'b000000};
                                        6'h02: data_drv <= {CXP0FB, 6'b000000};
                                        6'h03: data_drv <= {CXP1FB, 6'b000000};
                                        6'h04: data_drv <= {CXM0FB, 6'b000000};
                                        6'h05: data_drv <= {CXM1FB, 6'b000000};
                                        6'h06: data_drv <= {CXBLPF, 7'b000000};
                                        6'h07: data_drv <= {CXPPMM, 6'b000000};
                                        6'h08: data_drv <= {INPT0, 7'b000000};
                                        6'h09: data_drv <= {INPT1, 7'b000000};
                                        6'h0A: data_drv <= {INPT2, 7'b000000};
                                        6'h0B: data_drv <= {INPT3, 7'b000000};
                                        6'h0C: data_drv <= {INPT4, 7'b000000};
                                        6'h0D: data_drv <= {INPT5, 7'b000000};
                                        default: ;
                                endcase
                        end
                        else begin // writing! 
                                case (address)
                                        6'h00: begin
                                                VSYNC <= data[1];
                                        end
                                        6'h01: begin
                                                VBLANK <= {data[7:6], data[1]};
                                        end
                                        6'h02: begin
                                                WSYNC <= 1'b1; // STROBE
                                        end
                                        6'h03: begin
                                                RSYNC <= 1'b1; // STROBE
                                        end
                                        6'h04: begin
                                                NUSIZ0 <= data[5:0];
                                        end
                                        6'h05: begin
                                                NUSIZ1 <= data[5:0];
                                        end
                                        6'h06: begin
                                                COLUP0 <= data[7:1];
                                        end
                                        6'h07: begin
                                                COLUP1 <= data[7:1];
                                        end
                                        6'h08: begin
                                                COLUPF <= data[7:1];
                                        end
                                        6'h09: begin
                                                COLUBK <= data[7:1];
                                        end
                                        6'h0a: begin
                                                CTRLPF <= {data[5:4], data[2:0]};
                                        end
                                        6'h0b: begin
                                                REFP0 <= data[3];
                                        end
                                        6'h0c: begin
                                                REFP1 <= data[3];
                                        end
                                        6'h0d: begin
                                                PF0 <= data[7:4 ];
                                        end
                                        6'h0e: begin
                                                PF1 <= data;
                                        end
                                        6'h0f: begin
                                                PF2 <= data;
                                        end
                                        6'h10: begin
                                                //RESP0 <= 1'b1; // STROBE
                                        end
                                        6'h11: begin
                                                RESP1 <= 1'b1; // STROBE
                                        end
                                        6'h12: begin
                                                RESM0 <= 1'b1; // STROBE
                                        end
                                        6'h13: begin
                                                RESM1 <= 1'b1; // STROBE
                                        end
                                        6'h14: begin
                                                RESBL <= 1'b1; // STROBE
                                        end
                                        6'h15: begin
                                                AUDC0 <= data[3:0];
                                        end
                                        6'h16: begin
                                                AUDC1 <= data[4:0];
                                        end
                                        6'h17: begin
                                                AUDF0 <= data[4:0];
                                        end
                                        6'h18: begin
                                                AUDF1 <= data[3:0];
                                        end
                                        6'h19: begin
                                                AUDV0 <= data[3:0];
                                        end
                                        6'h1A: begin
                                                AUDV1 <= data[3:0];
                                        end
                                        6'h1B: begin
                                                GRP0 <= data;
                                        end
                                        6'h1C: begin
                                                GRP1 <= data;
                                        end
                                        6'h1D: begin
                                                ENAM0 <= data[1];
                                        end
                                        6'h1E: begin
                                                ENAM1 <= data[1];
                                        end
                                        6'h1F: begin
                                                ENABL <= data[1];
                                        end
                                        6'h20: begin
                                                HMP0 <= data[7:4];
                                        end
                                        6'h21: begin
                                                HMP1 <= data[7:4];
                                        end
                                        6'h22: begin
                                                HMM0 <= data[7:4];
                                        end
                                        6'h23: begin
                                                HMM1 <= data[7:4];
                                        end
                                        6'h24: begin
                                                HMBL <= data[7:4];
                                        end
                                        6'h25: begin
                                                VDELP0 <= data[0];
                                        end
                                        6'h26: begin
                                                VDEL01 <= data[0];
                                        end
                                        6'h27: begin
                                                VDELBL <= data[0];
                                        end
                                        6'h28: begin
                                                RESMP0 <= data[1];
                                        end
                                        6'h29: begin
                                                RESMP1 <= data[1];
                                        end
                                        6'h2a: begin
                                                HMOVE <= 1'b1; // STROBE
                                        end
                                        6'h2b: begin
                                                HMCLR <= 1'b1; // STROBE
                                        end
                                        6'h2c: begin // cxclr STROBE
                                                CXM0P <= 2'b0; // read collision MO P1 M0 P0
                                                CXM1P <= 2'b0; // read collision M1 P0 M1 P1
                                                CXP0FB <= 2'b0; // read collision P0 PF P0 BL
                                                CXP1FB <= 2'b0; // read collision P1 PF P1 BL
                                                CXM0FB <= 2'b0; // read collision M0 PF M0 BL
                                                CXM1FB <= 2'b0; // read collision M1 PF M1 BL
                                                CXBLPF <= 2'b0; // read collision BL PF unused
                                                CXPPMM <= 2'b0; // read collision P0 P1 M0 M1
                                        end
                                        default: begin
                                        end
                                endcase
                        end
                end
        end
 
reg draw_p0;
reg draw_p1;
reg draw_m0;
reg draw_m1;
reg draw_bl;
 
always @ (*) begin // always combinational block that handles strobe register
        draw_p0 = 1'b0;
        draw_p1 = 1'b0;
        draw_m0 = 1'b0;
        draw_m1 = 1'b0;
        draw_bl = 1'b0;
 
        if (enable == 1'b1 && mem_rw == 1'b1) begin // writing! 
                case (address)
                        6'h10: begin
                                draw_p0 = 1'b1;
                        end
                        6'h11: begin
                                draw_p1 = 1'b1;
                        end
                        6'h12: begin
                                draw_m0 = 1'b1;
                        end
                        6'h13: begin
                                draw_m1 = 1'b1;
                        end
                        6'h14: begin
                                draw_bl = 1'b1;
                        end
                endcase
        end
end
 
 
always @(*) begin // comb logic
        if (hor_counter < 68 || vert_counter < 40 || vert_counter > 232) begin
                pixel = 3'd0;
                write_enable_n = 1'b1;
                write_addr = 0;
                write_data = vert_counter[2:0];
        end
        else begin
                write_enable_n = 1'b0;
                write_addr = (hor_counter - 68) + (vert_counter - 40)*160;
                write_data = 3'd4;
 
                if (CTRLPF[2] == 1'b1) begin // playfield gets priority over players so they can move behind the playfield
                                // Priority Objects
                                // 1            PF, BL
                                // 2            P0, M0
                                // 3            P1, M1
                                // 4            BK
 
                end
                else begin // regular priority
                                // Priority     Objects
                                // 1            P0, M0
                                // 2            P1, M1
                                // 3            BL, PF
                                // 4            BK
                        if (CTRLPF[0] == 1'b1) begin// reflected PF
                                if (ENABL == 1'b1) begin // the ball is enabled
 
                                end
                                else begin
                                        if (vert_counter < 4) begin
                                                pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                        else if (vert_counter < 12) begin
                                                pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                        else if (vert_counter < 20) begin
                                                pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                        else if (vert_counter < 28) begin
                                                pixel = (PF2[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                        else if (vert_counter < 36) begin
                                                pixel = (PF1[vert_counter - 28] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                        else begin
                                                pixel = (PF0[vert_counter - 36] == 1'b1) ? COLUPF : COLUBK;
                                        end
                                end
                        end
                        else begin
                                if (vert_counter < 4) begin
                                        pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
                                end
                                else if (vert_counter < 12) begin
                                        pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
                                end
                                else if (vert_counter < 20) begin
                                        pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
                                end
                                else if (vert_counter < 24) begin
                                        pixel = (PF0[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
                                end
                                else if (vert_counter < 32) begin
                                        pixel = (PF1[vert_counter - 24] == 1'b1) ? COLUPF : COLUBK;
                                end
                                else begin
                                        pixel = (PF2[vert_counter - 32] == 1'b1) ? COLUPF : COLUBK;
                                end
                        end
                end
                // 1: ordem de avaliacao
                // 2: pinta da cor do objeto
                // 3: senao pinta de bk
 
                        pixel = 3'd4;
 
        end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	215	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Video module ////`
10			`//// ////`
11			`//// TODO: ////`
12	235	creep	`//// - Collision detection ////`
13			`//// - Pixel output ////`
14			`//// ////`
15	215	creep	`//// Author(s): ////`
16			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
17			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
18			`//// ////`
19			`////////////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`////////////////////////////////////////////////////////////////////////////`
45
46			`include "timescale.v"
47
48	235	creep	`module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel, write_addr, write_data, write_enable_n);`
49	215	creep	`parameter [3:0] DATA_SIZE = 4'd8;`
50			`parameter [3:0] ADDR_SIZE = 4'd10; // this is the local addr_size`
51
52			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;`
53			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;`
54
55			`input clk; // master clock signal, 1.19mhz`
56			`input reset_n;`
57			`input [15:0] io_lines; // inputs from the keyboard controller`
58			`input enable; // since the address bus is shared an enable signal is used`
59			`input mem_rw; // read == 0, write == 1`
60			`input [ADDR_SIZE_:0] address; // system address bus`
61	235	creep	`inout [DATA_SIZE_:0] data; // controler <=> video data bus`
62			`output reg [2:0] pixel;`
63			`output reg [10:0] write_addr; // for the video memory`
64			`output reg [2:0] write_data;`
65			`output reg write_enable_n;`
66
67	215	creep	`reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus`
68
69			`assign data = (mem_rw \|\| !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.`
70
71			`reg VSYNC; // vertical sync set-clear`
72	216	creep	`reg [2:0] VBLANK; // vertical blank set-clear`
73	222	creep	`reg WSYNC; // SEMI-strobe wait for leading edge of horizontal blank`
74	215	creep	`reg RSYNC; // s t r o b e reset horizontal sync counter`
75	216	creep	`reg [5:0] NUSIZ0; // number-size player-missile 0`
76			`reg [5:0] NUSIZ1; // number-size player-missile 1`
77			`reg [6:0] COLUP0; // color-lum player 0`
78			`reg [6:0] COLUP1; // color-lum player 1`
79			`reg [6:0] COLUPF; // color-lum playfield`
80			`reg [6:0] COLUBK; // color-lum background`
81			`reg [4:0] CTRLPF; // control playfield ball size & collisions`
82	221	creep	`// D0 = REF (reflect playfield)`
83			`// D1 = SCORE (left half of playfield gets color of player 0, right half gets color of player 1)`
84			`// D2 = PFP (playfield gets priority over players so they can move behind the playfield)`
85			`// D4 & D5 = BALL SIZE`
86	216	creep	`reg REFP0; // reflect player 0`
87			`reg REFP1; // reflect player 1`
88			`reg [3:0] PF0; // playfield register byte 0`
89			`reg [7:0] PF1; // playfield register byte 1`
90			`reg [7:0] PF2; // playfield register byte 2`
91	235	creep	`//reg RESP0; // s t r o b e reset player 0`
92	215	creep	`reg RESP1; // s t r o b e reset player 1`
93			`reg RESM0; // s t r o b e reset missile 0`
94			`reg RESM1; // s t r o b e reset missile 1`
95			`reg RESBL; // s t r o b e reset ball`
96	216	creep	`reg [3:0] AUDC0; // audio control 0`
97			`reg [4:0] AUDC1; // audio control 1`
98			`reg [4:0] AUDF0; // audio frequency 0`
99			`reg [3:0] AUDF1; // audio frequency 1`
100			`reg [3:0] AUDV0; // audio volume 0`
101			`reg [3:0] AUDV1; // audio volume 1`
102			`reg [7:0] GRP0; // graphics player 0`
103			`reg [7:0] GRP1; // graphics player 1`
104			`reg ENAM0; // graphics (enable) missile 0`
105			`reg ENAM1; // graphics (enable) missile 1`
106			`reg ENABL; // graphics (enable) ball`
107			`reg [3:0] HMP0; // horizontal motion player 0`
108			`reg [3:0] HMP1; // horizontal motion player 1`
109			`reg [3:0] HMM0; // horizontal motion missile 0`
110			`reg [3:0] HMM1; // horizontal motion missile 1`
111			`reg [3:0] HMBL; // horizontal motion ball`
112			`reg VDELP0; // vertical delay player 0`
113			`reg VDEL01; // vertical delay player 1`
114			`reg VDELBL; // vertical delay ball`
115			`reg RESMP0; // reset missile 0 to player 0`
116			`reg RESMP1; // reset missile 1 to player 1`
117	215	creep	`reg HMOVE; // s t r o b e apply horizontal motion`
118			`reg HMCLR; // s t r o b e clear horizontal motion registers`
119
120	216	creep	`reg [1:0] CXM0P; // read collision MO P1 M0 P0`
121			`reg [1:0] CXM1P; // read collision M1 P0 M1 P1`
122			`reg [1:0] CXP0FB; // read collision P0 PF P0 BL`
123			`reg [1:0] CXP1FB; // read collision P1 PF P1 BL`
124			`reg [1:0] CXM0FB; // read collision M0 PF M0 BL`
125			`reg [1:0] CXM1FB; // read collision M1 PF M1 BL`
126			`reg CXBLPF; // read collision BL PF unused`
127			`reg [1:0] CXPPMM; // read collision P0 P1 M0 M1`
128			`reg INPT0; // read pot port`
129			`reg INPT1; // read pot port`
130			`reg INPT2; // read pot port`
131			`reg INPT3; // read pot port`
132			`reg INPT4; // read input`
133	222	creep	`reg INPT5; // read input`
134	216	creep
135	235	creep	`reg [8:0] vert_counter;`
136			`reg [7:0] hor_counter;`
137	222	creep
138	216	creep	`always @(posedge clk or negedge reset_n) begin`
139	215	creep	`if (reset_n == 1'b0) begin`
140	235	creep	`hor_counter <= 8'd0;`
141			`vert_counter <= 9'd0;`
142	222	creep	`end`
143			`else begin`
144	235	creep	`if (hor_counter == 8'd227) begin`
145			`hor_counter <= 8'd0;`
146			`WSYNC <= 1'b0; // TODO: check this on stella pdf`
147
148			`if (vert_counter == 9'd261) begin`
149			`vert_counter <= 9'd0;`
150			`end`
151			`else begin`
152			`vert_counter <= vert_counter + 9'd1;`
153			`end`
154	222	creep	`end`
155			`else begin`
156			`hor_counter <= hor_counter + 6'd1;`
157			`end`
158			`end`
159			`end`
160
161			`always @(posedge clk or negedge reset_n) begin`
162			`if (reset_n == 1'b0) begin`
163	215	creep	`data_drv <= 8'h00;`
164	222	creep	`WSYNC <= 1'b0;`
165	215	creep	`end`
166	235	creep	`else if (enable == 1'b1) begin`
167	216	creep	`if (mem_rw == 1'b0) begin // reading!`
168	215	creep	`case (address)`
169	216	creep	`6'h00: data_drv <= {CXM0P, 6'b000000};`
170			`6'h01: data_drv <= {CXM1P, 6'b000000};`
171			`6'h02: data_drv <= {CXP0FB, 6'b000000};`
172			`6'h03: data_drv <= {CXP1FB, 6'b000000};`
173			`6'h04: data_drv <= {CXM0FB, 6'b000000};`
174			`6'h05: data_drv <= {CXM1FB, 6'b000000};`
175			`6'h06: data_drv <= {CXBLPF, 7'b000000};`
176			`6'h07: data_drv <= {CXPPMM, 6'b000000};`
177			`6'h08: data_drv <= {INPT0, 7'b000000};`
178			`6'h09: data_drv <= {INPT1, 7'b000000};`
179			`6'h0A: data_drv <= {INPT2, 7'b000000};`
180			`6'h0B: data_drv <= {INPT3, 7'b000000};`
181			`6'h0C: data_drv <= {INPT4, 7'b000000};`
182			`6'h0D: data_drv <= {INPT5, 7'b000000};`
183			`default: ;`
184	215	creep	`endcase`
185			`end`
186	216	creep	`else begin // writing!`
187	215	creep	`case (address)`
188	216	creep	`6'h00: begin`
189	217	creep	`VSYNC <= data[1];`
190	215	creep	`end`
191	216	creep	`6'h01: begin`
192	217	creep	`VBLANK <= {data[7:6], data[1]};`
193	215	creep	`end`
194	216	creep	`6'h02: begin`
195	217	creep	`WSYNC <= 1'b1; // STROBE`
196	215	creep	`end`
197	216	creep	`6'h03: begin`
198	217	creep	`RSYNC <= 1'b1; // STROBE`
199	215	creep	`end`
200	216	creep	`6'h04: begin`
201	217	creep	`NUSIZ0 <= data[5:0];`
202	216	creep	`end`
203			`6'h05: begin`
204	217	creep	`NUSIZ1 <= data[5:0];`
205	216	creep	`end`
206			`6'h06: begin`
207	217	creep	`COLUP0 <= data[7:1];`
208	216	creep	`end`
209			`6'h07: begin`
210	217	creep	`COLUP1 <= data[7:1];`
211	216	creep	`end`
212			`6'h08: begin`
213	217	creep	`COLUPF <= data[7:1];`
214	216	creep	`end`
215			`6'h09: begin`
216	217	creep	`COLUBK <= data[7:1];`
217	216	creep	`end`
218			`6'h0a: begin`
219	217	creep	`CTRLPF <= {data[5:4], data[2:0]};`
220	216	creep	`end`
221			`6'h0b: begin`
222	217	creep	`REFP0 <= data[3];`
223	216	creep	`end`
224			`6'h0c: begin`
225	217	creep	`REFP1 <= data[3];`
226	216	creep	`end`
227	217	creep	`6'h0d: begin`
228			`PF0 <= data[7:4 ];`
229			`end`
230			`6'h0e: begin`
231			`PF1 <= data;`
232			`end`
233			`6'h0f: begin`
234			`PF2 <= data;`
235			`end`
236			`6'h10: begin`
237	235	creep	`//RESP0 <= 1'b1; // STROBE`
238	217	creep	`end`
239			`6'h11: begin`
240			`RESP1 <= 1'b1; // STROBE`
241			`end`
242			`6'h12: begin`
243			`RESM0 <= 1'b1; // STROBE`
244			`end`
245			`6'h13: begin`
246			`RESM1 <= 1'b1; // STROBE`
247			`end`
248			`6'h14: begin`
249			`RESBL <= 1'b1; // STROBE`
250			`end`
251			`6'h15: begin`
252			`AUDC0 <= data[3:0];`
253			`end`
254			`6'h16: begin`
255			`AUDC1 <= data[4:0];`
256			`end`
257			`6'h17: begin`
258			`AUDF0 <= data[4:0];`
259			`end`
260			`6'h18: begin`
261			`AUDF1 <= data[3:0];`
262			`end`
263			`6'h19: begin`
264			`AUDV0 <= data[3:0];`
265			`end`
266			`6'h1A: begin`
267			`AUDV1 <= data[3:0];`
268			`end`
269			`6'h1B: begin`
270			`GRP0 <= data;`
271			`end`
272			`6'h1C: begin`
273			`GRP1 <= data;`
274			`end`
275			`6'h1D: begin`
276			`ENAM0 <= data[1];`
277			`end`
278			`6'h1E: begin`
279			`ENAM1 <= data[1];`
280			`end`
281			`6'h1F: begin`
282			`ENABL <= data[1];`
283			`end`
284			`6'h20: begin`
285			`HMP0 <= data[7:4];`
286			`end`
287			`6'h21: begin`
288			`HMP1 <= data[7:4];`
289			`end`
290			`6'h22: begin`
291			`HMM0 <= data[7:4];`
292			`end`
293			`6'h23: begin`
294			`HMM1 <= data[7:4];`
295			`end`
296			`6'h24: begin`
297			`HMBL <= data[7:4];`
298			`end`
299			`6'h25: begin`
300			`VDELP0 <= data[0];`
301			`end`
302			`6'h26: begin`
303			`VDEL01 <= data[0];`
304			`end`
305			`6'h27: begin`
306			`VDELBL <= data[0];`
307			`end`
308			`6'h28: begin`
309			`RESMP0 <= data[1];`
310			`end`
311			`6'h29: begin`
312			`RESMP1 <= data[1];`
313			`end`
314			`6'h2a: begin`
315			`HMOVE <= 1'b1; // STROBE`
316			`end`
317			`6'h2b: begin`
318			`HMCLR <= 1'b1; // STROBE`
319			`end`
320	221	creep	`6'h2c: begin // cxclr STROBE`
321			`CXM0P <= 2'b0; // read collision MO P1 M0 P0`
322			`CXM1P <= 2'b0; // read collision M1 P0 M1 P1`
323			`CXP0FB <= 2'b0; // read collision P0 PF P0 BL`
324			`CXP1FB <= 2'b0; // read collision P1 PF P1 BL`
325			`CXM0FB <= 2'b0; // read collision M0 PF M0 BL`
326			`CXM1FB <= 2'b0; // read collision M1 PF M1 BL`
327			`CXBLPF <= 2'b0; // read collision BL PF unused`
328			`CXPPMM <= 2'b0; // read collision P0 P1 M0 M1`
329	217	creep	`end`
330	215	creep	`default: begin`
331			`end`
332			`endcase`
333			`end`
334			`end`
335			`end`
336	235	creep
337			`reg draw_p0;`
338			`reg draw_p1;`
339			`reg draw_m0;`
340			`reg draw_m1;`
341			`reg draw_bl;`
342
343			`always @ (*) begin // always combinational block that handles strobe register`
344			`draw_p0 = 1'b0;`
345			`draw_p1 = 1'b0;`
346			`draw_m0 = 1'b0;`
347			`draw_m1 = 1'b0;`
348			`draw_bl = 1'b0;`
349
350			`if (enable == 1'b1 && mem_rw == 1'b1) begin // writing!`
351			`case (address)`
352			`6'h10: begin`
353			`draw_p0 = 1'b1;`
354			`end`
355			`6'h11: begin`
356			`draw_p1 = 1'b1;`
357			`end`
358			`6'h12: begin`
359			`draw_m0 = 1'b1;`
360			`end`
361			`6'h13: begin`
362			`draw_m1 = 1'b1;`
363			`end`
364			`6'h14: begin`
365			`draw_bl = 1'b1;`
366			`end`
367			`endcase`
368			`end`
369			`end`
370
371
372			`always @(*) begin // comb logic`
373			`if (hor_counter < 68 \|\| vert_counter < 40 \|\| vert_counter > 232) begin`
374			`pixel = 3'd0;`
375			`write_enable_n = 1'b1;`
376			`write_addr = 0;`
377			`write_data = vert_counter[2:0];`
378			`end`
379			`else begin`
380			`write_enable_n = 1'b0;`
381			`write_addr = (hor_counter - 68) + (vert_counter - 40)*160;`
382			`write_data = 3'd4;`
383
384			`if (CTRLPF[2] == 1'b1) begin // playfield gets priority over players so they can move behind the playfield`
385			`// Priority Objects`
386			`// 1 PF, BL`
387			`// 2 P0, M0`
388			`// 3 P1, M1`
389			`// 4 BK`
390
391			`end`
392			`else begin // regular priority`
393			`// Priority Objects`
394			`// 1 P0, M0`
395			`// 2 P1, M1`
396			`// 3 BL, PF`
397			`// 4 BK`
398			`if (CTRLPF[0] == 1'b1) begin// reflected PF`
399			`if (ENABL == 1'b1) begin // the ball is enabled`
400
401			`end`
402			`else begin`
403			`if (vert_counter < 4) begin`
404			`pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;`
405			`end`
406			`else if (vert_counter < 12) begin`
407			`pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;`
408			`end`
409			`else if (vert_counter < 20) begin`
410			`pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;`
411			`end`
412			`else if (vert_counter < 28) begin`
413			`pixel = (PF2[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;`
414			`end`
415			`else if (vert_counter < 36) begin`
416			`pixel = (PF1[vert_counter - 28] == 1'b1) ? COLUPF : COLUBK;`
417			`end`
418			`else begin`
419			`pixel = (PF0[vert_counter - 36] == 1'b1) ? COLUPF : COLUBK;`
420			`end`
421			`end`
422			`end`
423			`else begin`
424			`if (vert_counter < 4) begin`
425			`pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;`
426			`end`
427			`else if (vert_counter < 12) begin`
428			`pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;`
429			`end`
430			`else if (vert_counter < 20) begin`
431			`pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;`
432			`end`
433			`else if (vert_counter < 24) begin`
434			`pixel = (PF0[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;`
435			`end`
436			`else if (vert_counter < 32) begin`
437			`pixel = (PF1[vert_counter - 24] == 1'b1) ? COLUPF : COLUBK;`
438			`end`
439			`else begin`
440			`pixel = (PF2[vert_counter - 32] == 1'b1) ? COLUPF : COLUBK;`
441			`end`
442			`end`
443			`end`
444			`// 1: ordem de avaliacao`
445			`// 2: pinta da cor do objeto`
446			`// 3: senao pinta de bk`
447
448			`pixel = 3'd4;`
449
450			`end`
451			`end`
452
453	215	creep
454			`endmodule`
455

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