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[/] [t80/] [trunk/] [rtl/] [vhdl/] [DebugSystem.vhd] - Blame information for rev 12

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-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
-- that can be synthesized and used with
-- the NoICE debugger that can be found at
-- http://www.noicedebugger.com/
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity DebugSystem is
        port(
                Reset_n         : in std_logic;
                Clk                     : in std_logic;
                NMI_n           : in std_logic;
                RXD0            : in std_logic;
                CTS0            : in std_logic;
                DSR0            : in std_logic;
                RI0                     : in std_logic;
                DCD0            : in std_logic;
                RXD1            : in std_logic;
                CTS1            : in std_logic;
                DSR1            : in std_logic;
                RI1                     : in std_logic;
                DCD1            : in std_logic;
                TXD0            : out std_logic;
                RTS0            : out std_logic;
                DTR0            : out std_logic;
                TXD1            : out std_logic;
                RTS1            : out std_logic;
                DTR1            : out std_logic
        );
end entity DebugSystem;
 
architecture struct of DebugSystem is
 
        signal M1_n                     : std_logic;
        signal MREQ_n           : std_logic;
        signal IORQ_n           : std_logic;
        signal RD_n                     : std_logic;
        signal WR_n                     : std_logic;
        signal RFSH_n           : std_logic;
        signal HALT_n           : std_logic;
        signal WAIT_n           : std_logic;
        signal INT_n            : std_logic;
        signal RESET_s          : std_logic;
        signal BUSRQ_n          : std_logic;
        signal BUSAK_n          : std_logic;
        signal A                        : std_logic_vector(15 downto 0);
        signal D                        : std_logic_vector(7 downto 0);
        signal ROM_D            : std_logic_vector(7 downto 0);
        signal SRAM_D           : std_logic_vector(7 downto 0);
        signal UART0_D          : std_logic_vector(7 downto 0);
        signal UART1_D          : std_logic_vector(7 downto 0);
        signal CPU_D            : std_logic_vector(7 downto 0);
 
        signal Mirror           : std_logic;
 
        signal IOWR_n           : std_logic;
        signal RAMCS_n          : std_logic;
        signal UART0CS_n        : std_logic;
        signal UART1CS_n        : std_logic;
 
        signal BaudOut0         : std_logic;
        signal BaudOut1         : std_logic;
 
begin
 
        Wait_n <= '1';
        BusRq_n <= '1';
        INT_n <= '1';
 
        process (Reset_n, Clk)
        begin
                if Reset_n = '0' then
                        Reset_s <= '0';
                        Mirror <= '0';
                elsif Clk'event and Clk = '1' then
                        Reset_s <= '1';
                        if IORQ_n = '0' and A(7 downto 4) = "1111" then
                                Mirror <= D(0);
                        end if;
                end if;
        end process;
 
        IOWR_n <= WR_n or IORQ_n;
        RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
        UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
        UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
 
        CPU_D <=
                SRAM_D when RAMCS_n = '0' else
                UART0_D when UART0CS_n = '0' else
                UART1_D when UART1CS_n = '0' else
                ROM_D;
 
        u0 : entity work.T80s
                        generic map(Mode => 1)
                        port map(
                                RESET_n => RESET_s,
                                CLK_n => Clk,
                                WAIT_n => WAIT_n,
                                INT_n => INT_n,
                                NMI_n => NMI_n,
                                BUSRQ_n => BUSRQ_n,
                                M1_n => M1_n,
                                MREQ_n => MREQ_n,
                                IORQ_n => IORQ_n,
                                RD_n => RD_n,
                                WR_n => WR_n,
                                RFSH_n => RFSH_n,
                                HALT_n => HALT_n,
                                BUSAK_n => BUSAK_n,
                                A => A,
                                DI => CPU_D,
                                DO => D);
 
        u1 : entity work.MonZ80
                        port map(
                                Clk => Clk,
                                A => A(10 downto 0),
                                D => ROM_D);
 
        u2 : entity work.SSRAM
                        generic map(
                                AddrWidth => 12)
                        port map(
                                Clk => Clk,
                                CE_n => RAMCS_n,
                                WE_n => WR_n,
                                A => A(11 downto 0),
                                DIn => D,
                                DOut => SRAM_D);
 
        u3 : entity work.T16450
                        port map(
                                MR_n => Reset_s,
                                XIn => Clk,
                                RClk => BaudOut0,
                                CS_n => UART0CS_n,
                                Rd_n => RD_n,
                                Wr_n => IOWR_n,
                                A => A(2 downto 0),
                                D_In => D,
                                D_Out => UART0_D,
                                SIn => RXD0,
                                CTS_n => CTS0,
                                DSR_n => DSR0,
                                RI_n => RI0,
                                DCD_n => DCD0,
                                SOut => TXD0,
                                RTS_n => RTS0,
                                DTR_n => DTR0,
                                OUT1_n => open,
                                OUT2_n => open,
                                BaudOut => BaudOut0,
                                Intr => open);
 
        u4 : entity work.T16450
                        port map(
                                MR_n => Reset_s,
                                XIn => Clk,
                                RClk => BaudOut1,
                                CS_n => UART1CS_n,
                                Rd_n => RD_n,
                                Wr_n => IOWR_n,
                                A => A(2 downto 0),
                                D_In => D,
                                D_Out => UART1_D,
                                SIn => RXD1,
                                CTS_n => CTS1,
                                DSR_n => DSR1,
                                RI_n => RI1,
                                DCD_n => DCD1,
                                SOut => TXD1,
                                RTS_n => RTS1,
                                DTR_n => DTR1,
                                OUT1_n => open,
                                OUT2_n => open,
                                BaudOut => BaudOut1,
                                Intr => open);
 
end;

Line No.	Rev	Author	Line
1	12	jesus	`-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs`
2			`-- that can be synthesized and used with`
3			`-- the NoICE debugger that can be found at`
4			`-- http://www.noicedebugger.com/`
5
6			`library IEEE;`
7			`use IEEE.std_logic_1164.all;`
8
9			`entity DebugSystem is`
10			`port(`
11			`Reset_n : in std_logic;`
12			`Clk : in std_logic;`
13			`NMI_n : in std_logic;`
14			`RXD0 : in std_logic;`
15			`CTS0 : in std_logic;`
16			`DSR0 : in std_logic;`
17			`RI0 : in std_logic;`
18			`DCD0 : in std_logic;`
19			`RXD1 : in std_logic;`
20			`CTS1 : in std_logic;`
21			`DSR1 : in std_logic;`
22			`RI1 : in std_logic;`
23			`DCD1 : in std_logic;`
24			`TXD0 : out std_logic;`
25			`RTS0 : out std_logic;`
26			`DTR0 : out std_logic;`
27			`TXD1 : out std_logic;`
28			`RTS1 : out std_logic;`
29			`DTR1 : out std_logic`
30			`);`
31			`end entity DebugSystem;`
32
33			`architecture struct of DebugSystem is`
34
35			`signal M1_n : std_logic;`
36			`signal MREQ_n : std_logic;`
37			`signal IORQ_n : std_logic;`
38			`signal RD_n : std_logic;`
39			`signal WR_n : std_logic;`
40			`signal RFSH_n : std_logic;`
41			`signal HALT_n : std_logic;`
42			`signal WAIT_n : std_logic;`
43			`signal INT_n : std_logic;`
44			`signal RESET_s : std_logic;`
45			`signal BUSRQ_n : std_logic;`
46			`signal BUSAK_n : std_logic;`
47			`signal A : std_logic_vector(15 downto 0);`
48			`signal D : std_logic_vector(7 downto 0);`
49			`signal ROM_D : std_logic_vector(7 downto 0);`
50			`signal SRAM_D : std_logic_vector(7 downto 0);`
51			`signal UART0_D : std_logic_vector(7 downto 0);`
52			`signal UART1_D : std_logic_vector(7 downto 0);`
53			`signal CPU_D : std_logic_vector(7 downto 0);`
54
55			`signal Mirror : std_logic;`
56
57			`signal IOWR_n : std_logic;`
58			`signal RAMCS_n : std_logic;`
59			`signal UART0CS_n : std_logic;`
60			`signal UART1CS_n : std_logic;`
61
62			`signal BaudOut0 : std_logic;`
63			`signal BaudOut1 : std_logic;`
64
65			`begin`
66
67			`Wait_n <= '1';`
68			`BusRq_n <= '1';`
69			`INT_n <= '1';`
70
71			`process (Reset_n, Clk)`
72			`begin`
73			`if Reset_n = '0' then`
74			`Reset_s <= '0';`
75			`Mirror <= '0';`
76			`elsif Clk'event and Clk = '1' then`
77			`Reset_s <= '1';`
78			`if IORQ_n = '0' and A(7 downto 4) = "1111" then`
79			`Mirror <= D(0);`
80			`end if;`
81			`end if;`
82			`end process;`
83
84			`IOWR_n <= WR_n or IORQ_n;`
85			`RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;`
86			`UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';`
87			`UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';`
88
89			`CPU_D <=`
90			`SRAM_D when RAMCS_n = '0' else`
91			`UART0_D when UART0CS_n = '0' else`
92			`UART1_D when UART1CS_n = '0' else`
93			`ROM_D;`
94
95			`u0 : entity work.T80s`
96			`generic map(Mode => 1)`
97			`port map(`
98			`RESET_n => RESET_s,`
99			`CLK_n => Clk,`
100			`WAIT_n => WAIT_n,`
101			`INT_n => INT_n,`
102			`NMI_n => NMI_n,`
103			`BUSRQ_n => BUSRQ_n,`
104			`M1_n => M1_n,`
105			`MREQ_n => MREQ_n,`
106			`IORQ_n => IORQ_n,`
107			`RD_n => RD_n,`
108			`WR_n => WR_n,`
109			`RFSH_n => RFSH_n,`
110			`HALT_n => HALT_n,`
111			`BUSAK_n => BUSAK_n,`
112			`A => A,`
113			`DI => CPU_D,`
114			`DO => D);`
115
116			`u1 : entity work.MonZ80`
117			`port map(`
118			`Clk => Clk,`
119			`A => A(10 downto 0),`
120			`D => ROM_D);`
121
122			`u2 : entity work.SSRAM`
123			`generic map(`
124			`AddrWidth => 12)`
125			`port map(`
126			`Clk => Clk,`
127			`CE_n => RAMCS_n,`
128			`WE_n => WR_n,`
129			`A => A(11 downto 0),`
130			`DIn => D,`
131			`DOut => SRAM_D);`
132
133			`u3 : entity work.T16450`
134			`port map(`
135			`MR_n => Reset_s,`
136			`XIn => Clk,`
137			`RClk => BaudOut0,`
138			`CS_n => UART0CS_n,`
139			`Rd_n => RD_n,`
140			`Wr_n => IOWR_n,`
141			`A => A(2 downto 0),`
142			`D_In => D,`
143			`D_Out => UART0_D,`
144			`SIn => RXD0,`
145			`CTS_n => CTS0,`
146			`DSR_n => DSR0,`
147			`RI_n => RI0,`
148			`DCD_n => DCD0,`
149			`SOut => TXD0,`
150			`RTS_n => RTS0,`
151			`DTR_n => DTR0,`
152			`OUT1_n => open,`
153			`OUT2_n => open,`
154			`BaudOut => BaudOut0,`
155			`Intr => open);`
156
157			`u4 : entity work.T16450`
158			`port map(`
159			`MR_n => Reset_s,`
160			`XIn => Clk,`
161			`RClk => BaudOut1,`
162			`CS_n => UART1CS_n,`
163			`Rd_n => RD_n,`
164			`Wr_n => IOWR_n,`
165			`A => A(2 downto 0),`
166			`D_In => D,`
167			`D_Out => UART1_D,`
168			`SIn => RXD1,`
169			`CTS_n => CTS1,`
170			`DSR_n => DSR1,`
171			`RI_n => RI1,`
172			`DCD_n => DCD1,`
173			`SOut => TXD1,`
174			`RTS_n => RTS1,`
175			`DTR_n => DTR1,`
176			`OUT1_n => open,`
177			`OUT2_n => open,`
178			`BaudOut => BaudOut1,`
179			`Intr => open);`
180
181			`end;`

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[/] [t80/] [trunk/] [rtl/] [vhdl/] [DebugSystem.vhd] - Blame information for rev 12