| 1 |
7 |
jesus |
--
|
| 2 |
|
|
-- Z80 compatible microprocessor core
|
| 3 |
|
|
--
|
| 4 |
15 |
jesus |
-- Version : 0235
|
| 5 |
7 |
jesus |
--
|
| 6 |
15 |
jesus |
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
| 7 |
7 |
jesus |
--
|
| 8 |
|
|
-- All rights reserved
|
| 9 |
|
|
--
|
| 10 |
|
|
-- Redistribution and use in source and synthezised forms, with or without
|
| 11 |
|
|
-- modification, are permitted provided that the following conditions are met:
|
| 12 |
|
|
--
|
| 13 |
|
|
-- Redistributions of source code must retain the above copyright notice,
|
| 14 |
|
|
-- this list of conditions and the following disclaimer.
|
| 15 |
|
|
--
|
| 16 |
|
|
-- Redistributions in synthesized form must reproduce the above copyright
|
| 17 |
|
|
-- notice, this list of conditions and the following disclaimer in the
|
| 18 |
|
|
-- documentation and/or other materials provided with the distribution.
|
| 19 |
|
|
--
|
| 20 |
|
|
-- Neither the name of the author nor the names of other contributors may
|
| 21 |
|
|
-- be used to endorse or promote products derived from this software without
|
| 22 |
|
|
-- specific prior written permission.
|
| 23 |
|
|
--
|
| 24 |
|
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
| 25 |
|
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
| 26 |
|
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
| 27 |
|
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
| 28 |
|
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
| 29 |
|
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
| 30 |
|
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
| 31 |
|
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
| 32 |
|
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
| 33 |
|
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
| 34 |
|
|
-- POSSIBILITY OF SUCH DAMAGE.
|
| 35 |
|
|
--
|
| 36 |
|
|
-- Please report bugs to the author, but before you do so, please
|
| 37 |
|
|
-- make sure that this is not a derivative work and that
|
| 38 |
|
|
-- you have the latest version of this file.
|
| 39 |
|
|
--
|
| 40 |
|
|
-- The latest version of this file can be found at:
|
| 41 |
15 |
jesus |
-- http://www.opencores.org/cvsweb.shtml/t80/
|
| 42 |
7 |
jesus |
--
|
| 43 |
|
|
-- Limitations :
|
| 44 |
|
|
--
|
| 45 |
|
|
-- File history :
|
| 46 |
|
|
--
|
| 47 |
|
|
-- 0208 : First complete release
|
| 48 |
|
|
--
|
| 49 |
|
|
-- 0211 : Fixed IM 1
|
| 50 |
|
|
--
|
| 51 |
|
|
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
| 52 |
|
|
--
|
| 53 |
15 |
jesus |
-- 0235 : Added IM 2 fix by Mike Johnson
|
| 54 |
|
|
--
|
| 55 |
7 |
jesus |
|
| 56 |
|
|
library IEEE;
|
| 57 |
|
|
use IEEE.std_logic_1164.all;
|
| 58 |
|
|
use IEEE.numeric_std.all;
|
| 59 |
|
|
use work.T80_Pack.all;
|
| 60 |
|
|
|
| 61 |
|
|
entity T80_MCode is
|
| 62 |
|
|
generic(
|
| 63 |
|
|
Mode : integer := 0
|
| 64 |
|
|
);
|
| 65 |
|
|
port(
|
| 66 |
|
|
IR : in std_logic_vector(7 downto 0);
|
| 67 |
|
|
ISet : in std_logic_vector(1 downto 0);
|
| 68 |
|
|
MCycle : in std_logic_vector(2 downto 0);
|
| 69 |
|
|
F : in std_logic_vector(7 downto 0);
|
| 70 |
|
|
NMICycle : in std_logic;
|
| 71 |
|
|
IntCycle : in std_logic;
|
| 72 |
|
|
MCycles : out std_logic_vector(2 downto 0);
|
| 73 |
|
|
TStates : out std_logic_vector(2 downto 0);
|
| 74 |
|
|
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
| 75 |
|
|
Inc_PC : out std_logic;
|
| 76 |
|
|
Inc_WZ : out std_logic;
|
| 77 |
|
|
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
| 78 |
|
|
Read_To_Reg : out std_logic;
|
| 79 |
|
|
Read_To_Acc : out std_logic;
|
| 80 |
|
|
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
| 81 |
|
|
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
| 82 |
|
|
ALU_Op : out std_logic_vector(3 downto 0);
|
| 83 |
|
|
-- (ir)ADD, (ir)ADC, (ir)SUB, (ir)SBC, (ir)AND, (ir)XOR, (ir)OR, (ir)CP, ADD, ADC, SUB, SBC, DAA, RLD, RRD, CP
|
| 84 |
|
|
Rot_Op : out std_logic;
|
| 85 |
|
|
Bit_Op : out std_logic_vector(1 downto 0); -- None, BIT, SET, RES
|
| 86 |
|
|
Save_ALU : out std_logic;
|
| 87 |
|
|
PreserveC : out std_logic;
|
| 88 |
|
|
Arith16 : out std_logic;
|
| 89 |
|
|
Set_Addr_To : out AddressOutput; -- aXY,aIOA,aSP,aBC,aDE,aZI,aNone
|
| 90 |
|
|
IORQ : out std_logic;
|
| 91 |
|
|
Jump : out std_logic;
|
| 92 |
|
|
JumpE : out std_logic;
|
| 93 |
|
|
JumpXY : out std_logic;
|
| 94 |
|
|
Call : out std_logic;
|
| 95 |
|
|
RstP : out std_logic;
|
| 96 |
|
|
LDZ : out std_logic;
|
| 97 |
|
|
LDW : out std_logic;
|
| 98 |
|
|
LDSPHL : out std_logic;
|
| 99 |
|
|
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
| 100 |
|
|
ExchangeDH : out std_logic;
|
| 101 |
|
|
ExchangeRp : out std_logic;
|
| 102 |
|
|
ExchangeAF : out std_logic;
|
| 103 |
|
|
ExchangeRS : out std_logic;
|
| 104 |
|
|
I_DJNZ : out std_logic;
|
| 105 |
|
|
I_CPL : out std_logic;
|
| 106 |
|
|
I_CCF : out std_logic;
|
| 107 |
|
|
I_SCF : out std_logic;
|
| 108 |
|
|
I_RETN : out std_logic;
|
| 109 |
|
|
I_BT : out std_logic;
|
| 110 |
|
|
I_BC : out std_logic;
|
| 111 |
|
|
I_BTR : out std_logic;
|
| 112 |
|
|
I_RLD : out std_logic;
|
| 113 |
|
|
I_RRD : out std_logic;
|
| 114 |
|
|
I_INRC : out std_logic;
|
| 115 |
|
|
SetDI : out std_logic;
|
| 116 |
|
|
SetEI : out std_logic;
|
| 117 |
|
|
IMode : out std_logic_vector(1 downto 0);
|
| 118 |
|
|
Halt : out std_logic;
|
| 119 |
|
|
Write : out std_logic
|
| 120 |
|
|
);
|
| 121 |
|
|
end T80_MCode;
|
| 122 |
|
|
|
| 123 |
|
|
architecture rtl of T80_MCode is
|
| 124 |
|
|
|
| 125 |
|
|
function is_cc_true(
|
| 126 |
|
|
F : std_logic_vector(7 downto 0);
|
| 127 |
|
|
cc : bit_vector(2 downto 0)
|
| 128 |
|
|
) return boolean is
|
| 129 |
|
|
begin
|
| 130 |
|
|
case cc is
|
| 131 |
|
|
when "000" => return F(6) = '0'; -- NZ
|
| 132 |
|
|
when "001" => return F(6) = '1'; -- Z
|
| 133 |
|
|
when "010" => return F(0) = '0'; -- NC
|
| 134 |
|
|
when "011" => return F(0) = '1'; -- C
|
| 135 |
|
|
when "100" => return F(2) = '0'; -- PO
|
| 136 |
|
|
when "101" => return F(2) = '1'; -- PE
|
| 137 |
|
|
when "110" => return F(7) = '0'; -- P
|
| 138 |
|
|
when "111" => return F(7) = '1'; -- M
|
| 139 |
|
|
end case;
|
| 140 |
|
|
end;
|
| 141 |
|
|
|
| 142 |
|
|
begin
|
| 143 |
|
|
|
| 144 |
|
|
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
| 145 |
|
|
variable DDD : std_logic_vector(2 downto 0);
|
| 146 |
|
|
variable SSS : std_logic_vector(2 downto 0);
|
| 147 |
|
|
variable DPair : std_logic_vector(1 downto 0);
|
| 148 |
|
|
variable IRB : bit_vector(7 downto 0);
|
| 149 |
|
|
begin
|
| 150 |
|
|
DDD := IR(5 downto 3);
|
| 151 |
|
|
SSS := IR(2 downto 0);
|
| 152 |
|
|
DPair := IR(5 downto 4);
|
| 153 |
|
|
IRB := to_bitvector(IR);
|
| 154 |
|
|
|
| 155 |
|
|
MCycles <= "001";
|
| 156 |
|
|
if MCycle = "001" then
|
| 157 |
|
|
TStates <= "100";
|
| 158 |
|
|
else
|
| 159 |
|
|
TStates <= "011";
|
| 160 |
|
|
end if;
|
| 161 |
|
|
Prefix <= "00";
|
| 162 |
|
|
Inc_PC <= '0';
|
| 163 |
|
|
Inc_WZ <= '0';
|
| 164 |
|
|
IncDec_16 <= "0000";
|
| 165 |
|
|
Read_To_Acc <= '0';
|
| 166 |
|
|
Read_To_Reg <= '0';
|
| 167 |
|
|
Set_BusB_To <= "0000";
|
| 168 |
|
|
Set_BusA_To <= "0000";
|
| 169 |
|
|
ALU_Op <= "0000";
|
| 170 |
|
|
Rot_Op <= '0';
|
| 171 |
|
|
Bit_Op <= "00";
|
| 172 |
|
|
Save_ALU <= '0';
|
| 173 |
|
|
PreserveC <= '0';
|
| 174 |
|
|
Arith16 <= '0';
|
| 175 |
|
|
IORQ <= '0';
|
| 176 |
|
|
Set_Addr_To <= aNone;
|
| 177 |
|
|
Jump <= '0';
|
| 178 |
|
|
JumpE <= '0';
|
| 179 |
|
|
JumpXY <= '0';
|
| 180 |
|
|
Call <= '0';
|
| 181 |
|
|
RstP <= '0';
|
| 182 |
|
|
LDZ <= '0';
|
| 183 |
|
|
LDW <= '0';
|
| 184 |
|
|
LDSPHL <= '0';
|
| 185 |
|
|
Special_LD <= "000";
|
| 186 |
|
|
ExchangeDH <= '0';
|
| 187 |
|
|
ExchangeRp <= '0';
|
| 188 |
|
|
ExchangeAF <= '0';
|
| 189 |
|
|
ExchangeRS <= '0';
|
| 190 |
|
|
I_DJNZ <= '0';
|
| 191 |
|
|
I_CPL <= '0';
|
| 192 |
|
|
I_CCF <= '0';
|
| 193 |
|
|
I_SCF <= '0';
|
| 194 |
|
|
I_RETN <= '0';
|
| 195 |
|
|
I_BT <= '0';
|
| 196 |
|
|
I_BC <= '0';
|
| 197 |
|
|
I_BTR <= '0';
|
| 198 |
|
|
I_RLD <= '0';
|
| 199 |
|
|
I_RRD <= '0';
|
| 200 |
|
|
I_INRC <= '0';
|
| 201 |
|
|
SetDI <= '0';
|
| 202 |
|
|
SetEI <= '0';
|
| 203 |
|
|
IMode <= "11";
|
| 204 |
|
|
Halt <= '0';
|
| 205 |
|
|
Write <= '0';
|
| 206 |
|
|
|
| 207 |
|
|
case ISet is
|
| 208 |
|
|
when "00" =>
|
| 209 |
|
|
|
| 210 |
|
|
------------------------------------------------------------------------------
|
| 211 |
|
|
--
|
| 212 |
|
|
-- Unprefixed instructions
|
| 213 |
|
|
--
|
| 214 |
|
|
------------------------------------------------------------------------------
|
| 215 |
|
|
|
| 216 |
|
|
case IRB is
|
| 217 |
|
|
-- 8 BIT LOAD GROUP
|
| 218 |
|
|
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|
| 219 |
|
|
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|
| 220 |
|
|
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|
| 221 |
|
|
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|
| 222 |
|
|
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|
| 223 |
|
|
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|
| 224 |
|
|
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
|
| 225 |
|
|
-- LD r,r'
|
| 226 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 227 |
|
|
ExchangeRp <= '1';
|
| 228 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 229 |
|
|
Read_To_Reg <= '1';
|
| 230 |
|
|
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
|
| 231 |
|
|
-- LD r,n
|
| 232 |
|
|
MCycles <= "010";
|
| 233 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 234 |
|
|
when 2 =>
|
| 235 |
|
|
Inc_PC <= '1';
|
| 236 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 237 |
|
|
Read_To_Reg <= '1';
|
| 238 |
|
|
when others => null;
|
| 239 |
|
|
end case;
|
| 240 |
|
|
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
|
| 241 |
|
|
-- LD r,(HL)
|
| 242 |
|
|
MCycles <= "010";
|
| 243 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 244 |
|
|
when 1 =>
|
| 245 |
|
|
Set_Addr_To <= aXY;
|
| 246 |
|
|
when 2 =>
|
| 247 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 248 |
|
|
Read_To_Reg <= '1';
|
| 249 |
|
|
when others => null;
|
| 250 |
|
|
end case;
|
| 251 |
|
|
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
|
| 252 |
|
|
-- LD (HL),r
|
| 253 |
|
|
MCycles <= "010";
|
| 254 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 255 |
|
|
when 1 =>
|
| 256 |
|
|
Set_Addr_To <= aXY;
|
| 257 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 258 |
|
|
Set_BusB_To(3) <= '0';
|
| 259 |
|
|
when 2 =>
|
| 260 |
|
|
Write <= '1';
|
| 261 |
|
|
when others => null;
|
| 262 |
|
|
end case;
|
| 263 |
|
|
when "00110110" =>
|
| 264 |
|
|
-- LD (HL),n
|
| 265 |
|
|
MCycles <= "011";
|
| 266 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 267 |
|
|
when 2 =>
|
| 268 |
|
|
Inc_PC <= '1';
|
| 269 |
|
|
Set_Addr_To <= aXY;
|
| 270 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 271 |
|
|
Set_BusB_To(3) <= '0';
|
| 272 |
|
|
when 3 =>
|
| 273 |
|
|
Write <= '1';
|
| 274 |
|
|
when others => null;
|
| 275 |
|
|
end case;
|
| 276 |
|
|
when "00001010" =>
|
| 277 |
|
|
-- LD A,(BC)
|
| 278 |
|
|
MCycles <= "010";
|
| 279 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 280 |
|
|
when 1 =>
|
| 281 |
|
|
Set_Addr_To <= aBC;
|
| 282 |
|
|
when 2 =>
|
| 283 |
|
|
Read_To_Acc <= '1';
|
| 284 |
|
|
when others => null;
|
| 285 |
|
|
end case;
|
| 286 |
|
|
when "00011010" =>
|
| 287 |
|
|
-- LD A,(DE)
|
| 288 |
|
|
MCycles <= "010";
|
| 289 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 290 |
|
|
when 1 =>
|
| 291 |
|
|
Set_Addr_To <= aDE;
|
| 292 |
|
|
when 2 =>
|
| 293 |
|
|
Read_To_Acc <= '1';
|
| 294 |
|
|
when others => null;
|
| 295 |
|
|
end case;
|
| 296 |
|
|
when "00111010" =>
|
| 297 |
|
|
-- LD A,(nn)
|
| 298 |
|
|
MCycles <= "100";
|
| 299 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 300 |
|
|
when 2 =>
|
| 301 |
|
|
Inc_PC <= '1';
|
| 302 |
|
|
LDZ <= '1';
|
| 303 |
|
|
when 3 =>
|
| 304 |
|
|
Set_Addr_To <= aZI;
|
| 305 |
|
|
Inc_PC <= '1';
|
| 306 |
|
|
when 4 =>
|
| 307 |
|
|
Read_To_Acc <= '1';
|
| 308 |
|
|
when others => null;
|
| 309 |
|
|
end case;
|
| 310 |
|
|
when "00000010" =>
|
| 311 |
|
|
-- LD (BC),A
|
| 312 |
|
|
MCycles <= "010";
|
| 313 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 314 |
|
|
when 1 =>
|
| 315 |
|
|
Set_Addr_To <= aBC;
|
| 316 |
|
|
Set_BusB_To <= "0111";
|
| 317 |
|
|
when 2 =>
|
| 318 |
|
|
Write <= '1';
|
| 319 |
|
|
when others => null;
|
| 320 |
|
|
end case;
|
| 321 |
|
|
when "00010010" =>
|
| 322 |
|
|
-- LD (DE),A
|
| 323 |
|
|
MCycles <= "010";
|
| 324 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 325 |
|
|
when 1 =>
|
| 326 |
|
|
Set_Addr_To <= aDE;
|
| 327 |
|
|
Set_BusB_To <= "0111";
|
| 328 |
|
|
when 2 =>
|
| 329 |
|
|
Write <= '1';
|
| 330 |
|
|
when others => null;
|
| 331 |
|
|
end case;
|
| 332 |
|
|
when "00110010" =>
|
| 333 |
|
|
-- LD (nn),A
|
| 334 |
|
|
MCycles <= "100";
|
| 335 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 336 |
|
|
when 2 =>
|
| 337 |
|
|
Inc_PC <= '1';
|
| 338 |
|
|
LDZ <= '1';
|
| 339 |
|
|
when 3 =>
|
| 340 |
|
|
Set_Addr_To <= aZI;
|
| 341 |
|
|
Inc_PC <= '1';
|
| 342 |
|
|
Set_BusB_To <= "0111";
|
| 343 |
|
|
when 4 =>
|
| 344 |
|
|
Write <= '1';
|
| 345 |
|
|
when others => null;
|
| 346 |
|
|
end case;
|
| 347 |
|
|
|
| 348 |
|
|
-- 16 BIT LOAD GROUP
|
| 349 |
|
|
when "00000001"|"00010001"|"00100001"|"00110001" =>
|
| 350 |
|
|
-- LD dd,nn
|
| 351 |
|
|
MCycles <= "011";
|
| 352 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 353 |
|
|
when 2 =>
|
| 354 |
|
|
Inc_PC <= '1';
|
| 355 |
|
|
Read_To_Reg <= '1';
|
| 356 |
|
|
if DPAIR = "11" then
|
| 357 |
|
|
Set_BusA_To(3 downto 0) <= "1000";
|
| 358 |
|
|
else
|
| 359 |
|
|
Set_BusA_To(2 downto 1) <= DPAIR;
|
| 360 |
|
|
Set_BusA_To(0) <= '1';
|
| 361 |
|
|
end if;
|
| 362 |
|
|
when 3 =>
|
| 363 |
|
|
Inc_PC <= '1';
|
| 364 |
|
|
Read_To_Reg <= '1';
|
| 365 |
|
|
if DPAIR = "11" then
|
| 366 |
|
|
Set_BusA_To(3 downto 0) <= "1001";
|
| 367 |
|
|
else
|
| 368 |
|
|
Set_BusA_To(2 downto 1) <= DPAIR;
|
| 369 |
|
|
Set_BusA_To(0) <= '0';
|
| 370 |
|
|
end if;
|
| 371 |
|
|
when others => null;
|
| 372 |
|
|
end case;
|
| 373 |
|
|
when "00101010" =>
|
| 374 |
|
|
-- LD HL,(nn)
|
| 375 |
|
|
MCycles <= "101";
|
| 376 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 377 |
|
|
when 2 =>
|
| 378 |
|
|
Inc_PC <= '1';
|
| 379 |
|
|
LDZ <= '1';
|
| 380 |
|
|
when 3 =>
|
| 381 |
|
|
Set_Addr_To <= aZI;
|
| 382 |
|
|
Inc_PC <= '1';
|
| 383 |
|
|
LDW <= '1';
|
| 384 |
|
|
when 4 =>
|
| 385 |
|
|
Set_BusA_To(2 downto 0) <= "101"; -- L
|
| 386 |
|
|
Read_To_Reg <= '1';
|
| 387 |
|
|
Inc_WZ <= '1';
|
| 388 |
|
|
Set_Addr_To <= aZI;
|
| 389 |
|
|
when 5 =>
|
| 390 |
|
|
Set_BusA_To(2 downto 0) <= "100"; -- H
|
| 391 |
|
|
Read_To_Reg <= '1';
|
| 392 |
|
|
when others => null;
|
| 393 |
|
|
end case;
|
| 394 |
|
|
when "00100010" =>
|
| 395 |
|
|
-- LD (nn),HL
|
| 396 |
|
|
MCycles <= "101";
|
| 397 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 398 |
|
|
when 2 =>
|
| 399 |
|
|
Inc_PC <= '1';
|
| 400 |
|
|
LDZ <= '1';
|
| 401 |
|
|
when 3 =>
|
| 402 |
|
|
Set_Addr_To <= aZI;
|
| 403 |
|
|
Inc_PC <= '1';
|
| 404 |
|
|
LDW <= '1';
|
| 405 |
|
|
Set_BusB_To <= "0101"; -- L
|
| 406 |
|
|
when 4 =>
|
| 407 |
|
|
Inc_WZ <= '1';
|
| 408 |
|
|
Set_Addr_To <= aZI;
|
| 409 |
|
|
Write <= '1';
|
| 410 |
|
|
Set_BusB_To <= "0100"; -- H
|
| 411 |
|
|
when 5 =>
|
| 412 |
|
|
Write <= '1';
|
| 413 |
|
|
when others => null;
|
| 414 |
|
|
end case;
|
| 415 |
|
|
when "11111001" =>
|
| 416 |
|
|
-- LD SP,HL
|
| 417 |
|
|
TStates <= "110";
|
| 418 |
|
|
LDSPHL <= '1';
|
| 419 |
|
|
when "11000101"|"11010101"|"11100101"|"11110101" =>
|
| 420 |
|
|
-- PUSH qq
|
| 421 |
|
|
MCycles <= "011";
|
| 422 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 423 |
|
|
when 1 =>
|
| 424 |
|
|
TStates <= "101";
|
| 425 |
|
|
IncDec_16 <= "1111";
|
| 426 |
|
|
Set_Addr_TO <= aSP;
|
| 427 |
|
|
if DPAIR = "11" then
|
| 428 |
|
|
Set_BusB_To <= "0111";
|
| 429 |
|
|
else
|
| 430 |
|
|
Set_BusB_To(2 downto 1) <= DPAIR;
|
| 431 |
|
|
Set_BusB_To(0) <= '0';
|
| 432 |
|
|
Set_BusB_To(3) <= '0';
|
| 433 |
|
|
end if;
|
| 434 |
|
|
when 2 =>
|
| 435 |
|
|
IncDec_16 <= "1111";
|
| 436 |
|
|
Set_Addr_To <= aSP;
|
| 437 |
|
|
if DPAIR = "11" then
|
| 438 |
|
|
Set_BusB_To <= "1011";
|
| 439 |
|
|
else
|
| 440 |
|
|
Set_BusB_To(2 downto 1) <= DPAIR;
|
| 441 |
|
|
Set_BusB_To(0) <= '1';
|
| 442 |
|
|
Set_BusB_To(3) <= '0';
|
| 443 |
|
|
end if;
|
| 444 |
|
|
Write <= '1';
|
| 445 |
|
|
when 3 =>
|
| 446 |
|
|
Write <= '1';
|
| 447 |
|
|
when others => null;
|
| 448 |
|
|
end case;
|
| 449 |
|
|
when "11000001"|"11010001"|"11100001"|"11110001" =>
|
| 450 |
|
|
-- POP qq
|
| 451 |
|
|
MCycles <= "011";
|
| 452 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 453 |
|
|
when 1 =>
|
| 454 |
|
|
TStates <= "101";
|
| 455 |
|
|
Set_Addr_To <= aSP;
|
| 456 |
|
|
when 2 =>
|
| 457 |
|
|
IncDec_16 <= "0111";
|
| 458 |
|
|
Set_Addr_To <= aSP;
|
| 459 |
|
|
Read_To_Reg <= '1';
|
| 460 |
|
|
if DPAIR = "11" then
|
| 461 |
|
|
Set_BusA_To(3 downto 0) <= "1011";
|
| 462 |
|
|
else
|
| 463 |
|
|
Set_BusA_To(2 downto 1) <= DPAIR;
|
| 464 |
|
|
Set_BusA_To(0) <= '1';
|
| 465 |
|
|
end if;
|
| 466 |
|
|
when 3 =>
|
| 467 |
|
|
IncDec_16 <= "0111";
|
| 468 |
|
|
Read_To_Reg <= '1';
|
| 469 |
|
|
if DPAIR = "11" then
|
| 470 |
|
|
Set_BusA_To(3 downto 0) <= "0111";
|
| 471 |
|
|
else
|
| 472 |
|
|
Set_BusA_To(2 downto 1) <= DPAIR;
|
| 473 |
|
|
Set_BusA_To(0) <= '0';
|
| 474 |
|
|
end if;
|
| 475 |
|
|
when others => null;
|
| 476 |
|
|
end case;
|
| 477 |
|
|
|
| 478 |
|
|
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
|
| 479 |
|
|
when "11101011" =>
|
| 480 |
|
|
-- EX DE,HL
|
| 481 |
|
|
ExchangeDH <= '1';
|
| 482 |
|
|
when "00001000" =>
|
| 483 |
|
|
-- EX AF,AF'
|
| 484 |
|
|
ExchangeAF <= '1';
|
| 485 |
|
|
when "11011001" =>
|
| 486 |
|
|
-- EXX
|
| 487 |
|
|
ExchangeRS <= '1';
|
| 488 |
|
|
when "11100011" =>
|
| 489 |
|
|
-- EX (SP),HL
|
| 490 |
|
|
MCycles <= "101";
|
| 491 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 492 |
|
|
when 1 =>
|
| 493 |
|
|
Set_Addr_To <= aSP;
|
| 494 |
|
|
when 2 =>
|
| 495 |
|
|
Read_To_Reg <= '1';
|
| 496 |
|
|
Set_BusA_To <= "0101";
|
| 497 |
|
|
Set_BusB_To <= "0101";
|
| 498 |
|
|
Set_Addr_To <= aSP;
|
| 499 |
|
|
when 3 =>
|
| 500 |
|
|
IncDec_16 <= "0111";
|
| 501 |
|
|
Set_Addr_To <= aSP;
|
| 502 |
|
|
TStates <= "100";
|
| 503 |
|
|
Write <= '1';
|
| 504 |
|
|
when 4 =>
|
| 505 |
|
|
Read_To_Reg <= '1';
|
| 506 |
|
|
Set_BusA_To <= "0100";
|
| 507 |
|
|
Set_BusB_To <= "0100";
|
| 508 |
|
|
Set_Addr_To <= aSP;
|
| 509 |
|
|
when 5 =>
|
| 510 |
|
|
IncDec_16 <= "1111";
|
| 511 |
|
|
TStates <= "101";
|
| 512 |
|
|
Write <= '1';
|
| 513 |
|
|
when others => null;
|
| 514 |
|
|
end case;
|
| 515 |
|
|
|
| 516 |
|
|
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
|
| 517 |
|
|
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|
| 518 |
|
|
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|
| 519 |
|
|
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|
| 520 |
|
|
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|
| 521 |
|
|
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|
| 522 |
|
|
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|
| 523 |
|
|
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|
| 524 |
|
|
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
|
| 525 |
|
|
-- ADD A,r
|
| 526 |
|
|
-- ADC A,r
|
| 527 |
|
|
-- SUB A,r
|
| 528 |
|
|
-- SBC A,r
|
| 529 |
|
|
-- AND A,r
|
| 530 |
|
|
-- OR A,r
|
| 531 |
|
|
-- XOR A,r
|
| 532 |
|
|
-- CP A,r
|
| 533 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 534 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 535 |
|
|
Read_To_Reg <= '1';
|
| 536 |
|
|
Save_ALU <= '1';
|
| 537 |
|
|
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
|
| 538 |
|
|
-- ADD A,(HL)
|
| 539 |
|
|
-- ADC A,(HL)
|
| 540 |
|
|
-- SUB A,(HL)
|
| 541 |
|
|
-- SBC A,(HL)
|
| 542 |
|
|
-- AND A,(HL)
|
| 543 |
|
|
-- OR A,(HL)
|
| 544 |
|
|
-- XOR A,(HL)
|
| 545 |
|
|
-- CP A,(HL)
|
| 546 |
|
|
MCycles <= "010";
|
| 547 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 548 |
|
|
when 1 =>
|
| 549 |
|
|
Set_Addr_To <= aXY;
|
| 550 |
|
|
when 2 =>
|
| 551 |
|
|
Read_To_Reg <= '1';
|
| 552 |
|
|
Save_ALU <= '1';
|
| 553 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 554 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 555 |
|
|
when others => null;
|
| 556 |
|
|
end case;
|
| 557 |
|
|
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
|
| 558 |
|
|
-- ADD A,n
|
| 559 |
|
|
-- ADC A,n
|
| 560 |
|
|
-- SUB A,n
|
| 561 |
|
|
-- SBC A,n
|
| 562 |
|
|
-- AND A,n
|
| 563 |
|
|
-- OR A,n
|
| 564 |
|
|
-- XOR A,n
|
| 565 |
|
|
-- CP A,n
|
| 566 |
|
|
MCycles <= "010";
|
| 567 |
|
|
if MCycle = "010" then
|
| 568 |
|
|
Inc_PC <= '1';
|
| 569 |
|
|
Read_To_Reg <= '1';
|
| 570 |
|
|
Save_ALU <= '1';
|
| 571 |
|
|
Set_BusB_To(2 downto 0) <= SSS;
|
| 572 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 573 |
|
|
end if;
|
| 574 |
|
|
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
|
| 575 |
|
|
-- INC r
|
| 576 |
|
|
Set_BusB_To <= "1010";
|
| 577 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 578 |
|
|
Read_To_Reg <= '1';
|
| 579 |
|
|
Save_ALU <= '1';
|
| 580 |
|
|
PreserveC <= '1';
|
| 581 |
|
|
ALU_Op <= "1000";
|
| 582 |
|
|
when "00110100" =>
|
| 583 |
|
|
-- INC (HL)
|
| 584 |
|
|
MCycles <= "011";
|
| 585 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 586 |
|
|
when 1 =>
|
| 587 |
|
|
Set_Addr_To <= aXY;
|
| 588 |
|
|
when 2 =>
|
| 589 |
|
|
TStates <= "100";
|
| 590 |
|
|
Set_Addr_To <= aXY;
|
| 591 |
|
|
Read_To_Reg <= '1';
|
| 592 |
|
|
Save_ALU <= '1';
|
| 593 |
|
|
PreserveC <= '1';
|
| 594 |
|
|
ALU_Op <= "1000";
|
| 595 |
|
|
Set_BusB_To <= "1010";
|
| 596 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 597 |
|
|
when 3 =>
|
| 598 |
|
|
Write <= '1';
|
| 599 |
|
|
when others => null;
|
| 600 |
|
|
end case;
|
| 601 |
|
|
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
|
| 602 |
|
|
-- DEC r
|
| 603 |
|
|
Set_BusB_To <= "1010";
|
| 604 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 605 |
|
|
Read_To_Reg <= '1';
|
| 606 |
|
|
Save_ALU <= '1';
|
| 607 |
|
|
PreserveC <= '1';
|
| 608 |
|
|
ALU_Op <= "1010";
|
| 609 |
|
|
when "00110101" =>
|
| 610 |
|
|
-- DEC (HL)
|
| 611 |
|
|
MCycles <= "011";
|
| 612 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 613 |
|
|
when 1 =>
|
| 614 |
|
|
Set_Addr_To <= aXY;
|
| 615 |
|
|
when 2 =>
|
| 616 |
|
|
TStates <= "100";
|
| 617 |
|
|
Set_Addr_To <= aXY;
|
| 618 |
|
|
ALU_Op <= "1010";
|
| 619 |
|
|
Read_To_Reg <= '1';
|
| 620 |
|
|
Save_ALU <= '1';
|
| 621 |
|
|
PreserveC <= '1';
|
| 622 |
|
|
Set_BusB_To <= "1010";
|
| 623 |
|
|
Set_BusA_To(2 downto 0) <= DDD;
|
| 624 |
|
|
when 3 =>
|
| 625 |
|
|
Write <= '1';
|
| 626 |
|
|
when others => null;
|
| 627 |
|
|
end case;
|
| 628 |
|
|
|
| 629 |
|
|
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
|
| 630 |
|
|
when "00100111" =>
|
| 631 |
|
|
-- DAA
|
| 632 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 633 |
|
|
Read_To_Reg <= '1';
|
| 634 |
|
|
ALU_Op <= "1100";
|
| 635 |
|
|
Save_ALU <= '1';
|
| 636 |
|
|
when "00101111" =>
|
| 637 |
|
|
-- CPL
|
| 638 |
|
|
I_CPL <= '1';
|
| 639 |
|
|
when "00111111" =>
|
| 640 |
|
|
-- CCF
|
| 641 |
|
|
I_CCF <= '1';
|
| 642 |
|
|
when "00110111" =>
|
| 643 |
|
|
-- SCF
|
| 644 |
|
|
I_SCF <= '1';
|
| 645 |
|
|
when "00000000" =>
|
| 646 |
|
|
if NMICycle = '1' then
|
| 647 |
|
|
-- NMI
|
| 648 |
|
|
MCycles <= "011";
|
| 649 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 650 |
|
|
when 1 =>
|
| 651 |
|
|
TStates <= "101";
|
| 652 |
|
|
IncDec_16 <= "1111";
|
| 653 |
|
|
Set_Addr_To <= aSP;
|
| 654 |
|
|
Set_BusB_To <= "1101";
|
| 655 |
|
|
when 2 =>
|
| 656 |
|
|
TStates <= "100";
|
| 657 |
|
|
Write <= '1';
|
| 658 |
|
|
IncDec_16 <= "1111";
|
| 659 |
|
|
Set_Addr_To <= aSP;
|
| 660 |
|
|
Set_BusB_To <= "1100";
|
| 661 |
|
|
when 3 =>
|
| 662 |
|
|
TStates <= "100";
|
| 663 |
|
|
Write <= '1';
|
| 664 |
|
|
when others => null;
|
| 665 |
|
|
end case;
|
| 666 |
|
|
elsif IntCycle = '1' then
|
| 667 |
|
|
-- INT (IM 2)
|
| 668 |
15 |
jesus |
MCycles <= "101";
|
| 669 |
7 |
jesus |
case to_integer(unsigned(MCycle)) is
|
| 670 |
|
|
when 1 =>
|
| 671 |
|
|
LDZ <= '1';
|
| 672 |
|
|
TStates <= "101";
|
| 673 |
|
|
IncDec_16 <= "1111";
|
| 674 |
|
|
Set_Addr_To <= aSP;
|
| 675 |
|
|
Set_BusB_To <= "1101";
|
| 676 |
|
|
when 2 =>
|
| 677 |
|
|
TStates <= "100";
|
| 678 |
|
|
Write <= '1';
|
| 679 |
|
|
IncDec_16 <= "1111";
|
| 680 |
|
|
Set_Addr_To <= aSP;
|
| 681 |
|
|
Set_BusB_To <= "1100";
|
| 682 |
|
|
when 3 =>
|
| 683 |
|
|
TStates <= "100";
|
| 684 |
|
|
Write <= '1';
|
| 685 |
15 |
jesus |
when 4 =>
|
| 686 |
|
|
Inc_PC <= '1';
|
| 687 |
|
|
LDZ <= '1';
|
| 688 |
|
|
when 5 =>
|
| 689 |
|
|
Jump <= '1';
|
| 690 |
7 |
jesus |
when others => null;
|
| 691 |
|
|
end case;
|
| 692 |
|
|
else
|
| 693 |
|
|
-- NOP
|
| 694 |
|
|
end if;
|
| 695 |
|
|
when "01110110" =>
|
| 696 |
|
|
-- HALT
|
| 697 |
|
|
Halt <= '1';
|
| 698 |
|
|
when "11110011" =>
|
| 699 |
|
|
-- DI
|
| 700 |
|
|
SetDI <= '1';
|
| 701 |
|
|
when "11111011" =>
|
| 702 |
|
|
-- EI
|
| 703 |
|
|
SetEI <= '1';
|
| 704 |
|
|
|
| 705 |
|
|
-- 16 BIT ARITHMETIC GROUP
|
| 706 |
|
|
when "00001001"|"00011001"|"00101001"|"00111001" =>
|
| 707 |
|
|
-- ADD HL,ss
|
| 708 |
|
|
MCycles <= "011";
|
| 709 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 710 |
|
|
when 2 =>
|
| 711 |
|
|
ALU_Op <= "1000";
|
| 712 |
|
|
Read_To_Reg <= '1';
|
| 713 |
|
|
Save_ALU <= '1';
|
| 714 |
|
|
Set_BusA_To(2 downto 0) <= "101";
|
| 715 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 716 |
|
|
when 0|1|2 =>
|
| 717 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 718 |
|
|
Set_BusB_To(0) <= '1';
|
| 719 |
|
|
when others =>
|
| 720 |
|
|
Set_BusB_To <= "1000";
|
| 721 |
|
|
end case;
|
| 722 |
|
|
TStates <= "100";
|
| 723 |
|
|
Arith16 <= '1';
|
| 724 |
|
|
when 3 =>
|
| 725 |
|
|
Read_To_Reg <= '1';
|
| 726 |
|
|
Save_ALU <= '1';
|
| 727 |
|
|
ALU_Op <= "1001";
|
| 728 |
|
|
Set_BusA_To(2 downto 0) <= "100";
|
| 729 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 730 |
|
|
when 0|1|2 =>
|
| 731 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 732 |
|
|
when others =>
|
| 733 |
|
|
Set_BusB_To <= "1001";
|
| 734 |
|
|
end case;
|
| 735 |
|
|
Arith16 <= '1';
|
| 736 |
|
|
when others =>
|
| 737 |
|
|
end case;
|
| 738 |
|
|
when "00000011"|"00010011"|"00100011"|"00110011" =>
|
| 739 |
|
|
-- INC ss
|
| 740 |
|
|
TStates <= "110";
|
| 741 |
|
|
IncDec_16(3 downto 2) <= "01";
|
| 742 |
|
|
IncDec_16(1 downto 0) <= DPair;
|
| 743 |
|
|
when "00001011"|"00011011"|"00101011"|"00111011" =>
|
| 744 |
|
|
-- DEC ss
|
| 745 |
|
|
TStates <= "110";
|
| 746 |
|
|
IncDec_16(3 downto 2) <= "11";
|
| 747 |
|
|
IncDec_16(1 downto 0) <= DPair;
|
| 748 |
|
|
|
| 749 |
|
|
-- ROTATE AND SHIFT GROUP
|
| 750 |
|
|
when "00000111"
|
| 751 |
|
|
-- RLCA
|
| 752 |
|
|
|"00010111"
|
| 753 |
|
|
-- RLA
|
| 754 |
|
|
|"00001111"
|
| 755 |
|
|
-- RRCA
|
| 756 |
|
|
|"00011111" =>
|
| 757 |
|
|
-- RRA
|
| 758 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 759 |
|
|
Rot_Op <= '1';
|
| 760 |
|
|
Read_To_Reg <= '1';
|
| 761 |
|
|
Save_ALU <= '1';
|
| 762 |
|
|
|
| 763 |
|
|
-- JUMP GROUP
|
| 764 |
|
|
when "11000011" =>
|
| 765 |
|
|
-- JP nn
|
| 766 |
|
|
MCycles <= "011";
|
| 767 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 768 |
|
|
when 2 =>
|
| 769 |
|
|
Inc_PC <= '1';
|
| 770 |
|
|
LDZ <= '1';
|
| 771 |
|
|
when 3 =>
|
| 772 |
|
|
Inc_PC <= '1';
|
| 773 |
|
|
Jump <= '1';
|
| 774 |
|
|
when others => null;
|
| 775 |
|
|
end case;
|
| 776 |
|
|
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
|
| 777 |
|
|
-- JP cc,nn
|
| 778 |
|
|
MCycles <= "011";
|
| 779 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 780 |
|
|
when 2 =>
|
| 781 |
|
|
Inc_PC <= '1';
|
| 782 |
|
|
LDZ <= '1';
|
| 783 |
|
|
when 3 =>
|
| 784 |
|
|
Inc_PC <= '1';
|
| 785 |
|
|
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
|
| 786 |
|
|
Jump <= '1';
|
| 787 |
|
|
end if;
|
| 788 |
|
|
when others => null;
|
| 789 |
|
|
end case;
|
| 790 |
|
|
when "00011000" =>
|
| 791 |
|
|
-- JR e
|
| 792 |
|
|
MCycles <= "011";
|
| 793 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 794 |
|
|
when 2 =>
|
| 795 |
|
|
Inc_PC <= '1';
|
| 796 |
|
|
when 3 =>
|
| 797 |
|
|
JumpE <= '1';
|
| 798 |
|
|
TStates <= "101";
|
| 799 |
|
|
when others => null;
|
| 800 |
|
|
end case;
|
| 801 |
|
|
when "00111000" =>
|
| 802 |
|
|
-- JR C,e
|
| 803 |
|
|
MCycles <= "011";
|
| 804 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 805 |
|
|
when 2 =>
|
| 806 |
|
|
Inc_PC <= '1';
|
| 807 |
|
|
if F(0) = '0' then
|
| 808 |
|
|
MCycles <= "010";
|
| 809 |
|
|
end if;
|
| 810 |
|
|
when 3 =>
|
| 811 |
|
|
JumpE <= '1';
|
| 812 |
|
|
TStates <= "101";
|
| 813 |
|
|
when others => null;
|
| 814 |
|
|
end case;
|
| 815 |
|
|
when "00110000" =>
|
| 816 |
|
|
-- JR NC,e
|
| 817 |
|
|
MCycles <= "011";
|
| 818 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 819 |
|
|
when 2 =>
|
| 820 |
|
|
Inc_PC <= '1';
|
| 821 |
|
|
if F(0) = '1' then
|
| 822 |
|
|
MCycles <= "010";
|
| 823 |
|
|
end if;
|
| 824 |
|
|
when 3 =>
|
| 825 |
|
|
JumpE <= '1';
|
| 826 |
|
|
TStates <= "101";
|
| 827 |
|
|
when others => null;
|
| 828 |
|
|
end case;
|
| 829 |
|
|
when "00101000" =>
|
| 830 |
|
|
-- JR Z,e
|
| 831 |
|
|
MCycles <= "011";
|
| 832 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 833 |
|
|
when 2 =>
|
| 834 |
|
|
Inc_PC <= '1';
|
| 835 |
|
|
if F(6) = '0' then
|
| 836 |
|
|
MCycles <= "010";
|
| 837 |
|
|
end if;
|
| 838 |
|
|
when 3 =>
|
| 839 |
|
|
JumpE <= '1';
|
| 840 |
|
|
TStates <= "101";
|
| 841 |
|
|
when others => null;
|
| 842 |
|
|
end case;
|
| 843 |
|
|
when "00100000" =>
|
| 844 |
|
|
-- JR NZ,e
|
| 845 |
|
|
MCycles <= "011";
|
| 846 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 847 |
|
|
when 2 =>
|
| 848 |
|
|
Inc_PC <= '1';
|
| 849 |
|
|
if F(6) = '1' then
|
| 850 |
|
|
MCycles <= "010";
|
| 851 |
|
|
end if;
|
| 852 |
|
|
when 3 =>
|
| 853 |
|
|
JumpE <= '1';
|
| 854 |
|
|
TStates <= "101";
|
| 855 |
|
|
when others => null;
|
| 856 |
|
|
end case;
|
| 857 |
|
|
when "11101001" =>
|
| 858 |
|
|
-- JP (HL)
|
| 859 |
|
|
JumpXY <= '1';
|
| 860 |
|
|
when "00010000" =>
|
| 861 |
|
|
-- DJNZ,e
|
| 862 |
|
|
MCycles <= "011";
|
| 863 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 864 |
|
|
when 1 =>
|
| 865 |
|
|
I_DJNZ <= '1';
|
| 866 |
|
|
Set_BusB_To <= "1010";
|
| 867 |
|
|
Set_BusA_To(2 downto 0) <= "000";
|
| 868 |
|
|
Read_To_Reg <= '1';
|
| 869 |
|
|
Save_ALU <= '1';
|
| 870 |
|
|
ALU_Op <= "1010";
|
| 871 |
|
|
when 2 =>
|
| 872 |
|
|
I_DJNZ <= '1';
|
| 873 |
|
|
Inc_PC <= '1';
|
| 874 |
|
|
when 3 =>
|
| 875 |
|
|
JumpE <= '1';
|
| 876 |
|
|
TStates <= "101";
|
| 877 |
|
|
when others => null;
|
| 878 |
|
|
end case;
|
| 879 |
|
|
|
| 880 |
|
|
-- CALL AND RETURN GROUP
|
| 881 |
|
|
when "11001101" =>
|
| 882 |
|
|
-- CALL nn
|
| 883 |
|
|
MCycles <= "101";
|
| 884 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 885 |
|
|
when 2 =>
|
| 886 |
|
|
Inc_PC <= '1';
|
| 887 |
|
|
LDZ <= '1';
|
| 888 |
|
|
when 3 =>
|
| 889 |
|
|
IncDec_16 <= "1111";
|
| 890 |
|
|
Inc_PC <= '1';
|
| 891 |
|
|
TStates <= "100";
|
| 892 |
|
|
Set_Addr_To <= aSP;
|
| 893 |
|
|
LDW <= '1';
|
| 894 |
|
|
Set_BusB_To <= "1101";
|
| 895 |
|
|
when 4 =>
|
| 896 |
|
|
Write <= '1';
|
| 897 |
|
|
IncDec_16 <= "1111";
|
| 898 |
|
|
Set_Addr_To <= aSP;
|
| 899 |
|
|
Set_BusB_To <= "1100";
|
| 900 |
|
|
when 5 =>
|
| 901 |
|
|
Write <= '1';
|
| 902 |
|
|
Call <= '1';
|
| 903 |
|
|
when others => null;
|
| 904 |
|
|
end case;
|
| 905 |
|
|
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
|
| 906 |
|
|
-- CALL cc,nn
|
| 907 |
|
|
MCycles <= "101";
|
| 908 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 909 |
|
|
when 2 =>
|
| 910 |
|
|
Inc_PC <= '1';
|
| 911 |
|
|
LDZ <= '1';
|
| 912 |
|
|
when 3 =>
|
| 913 |
|
|
Inc_PC <= '1';
|
| 914 |
|
|
LDW <= '1';
|
| 915 |
|
|
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
|
| 916 |
|
|
IncDec_16 <= "1111";
|
| 917 |
|
|
Set_Addr_TO <= aSP;
|
| 918 |
|
|
TStates <= "100";
|
| 919 |
|
|
Set_BusB_To <= "1101";
|
| 920 |
|
|
else
|
| 921 |
|
|
MCycles <= "011";
|
| 922 |
|
|
end if;
|
| 923 |
|
|
when 4 =>
|
| 924 |
|
|
Write <= '1';
|
| 925 |
|
|
IncDec_16 <= "1111";
|
| 926 |
|
|
Set_Addr_To <= aSP;
|
| 927 |
|
|
Set_BusB_To <= "1100";
|
| 928 |
|
|
when 5 =>
|
| 929 |
|
|
Write <= '1';
|
| 930 |
|
|
Call <= '1';
|
| 931 |
|
|
when others => null;
|
| 932 |
|
|
end case;
|
| 933 |
|
|
when "11001001" =>
|
| 934 |
|
|
-- RET
|
| 935 |
|
|
MCycles <= "011";
|
| 936 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 937 |
|
|
when 1 =>
|
| 938 |
|
|
TStates <= "101";
|
| 939 |
|
|
Set_Addr_TO <= aSP;
|
| 940 |
|
|
when 2 =>
|
| 941 |
|
|
IncDec_16 <= "0111";
|
| 942 |
|
|
Set_Addr_To <= aSP;
|
| 943 |
|
|
LDZ <= '1';
|
| 944 |
|
|
when 3 =>
|
| 945 |
|
|
Jump <= '1';
|
| 946 |
|
|
IncDec_16 <= "0111";
|
| 947 |
|
|
when others => null;
|
| 948 |
|
|
end case;
|
| 949 |
|
|
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
|
| 950 |
|
|
-- RET cc
|
| 951 |
|
|
MCycles <= "011";
|
| 952 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 953 |
|
|
when 1 =>
|
| 954 |
|
|
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
|
| 955 |
|
|
Set_Addr_TO <= aSP;
|
| 956 |
|
|
else
|
| 957 |
|
|
MCycles <= "001";
|
| 958 |
|
|
end if;
|
| 959 |
|
|
TStates <= "101";
|
| 960 |
|
|
when 2 =>
|
| 961 |
|
|
IncDec_16 <= "0111";
|
| 962 |
|
|
Set_Addr_To <= aSP;
|
| 963 |
|
|
LDZ <= '1';
|
| 964 |
|
|
when 3 =>
|
| 965 |
|
|
Jump <= '1';
|
| 966 |
|
|
IncDec_16 <= "0111";
|
| 967 |
|
|
when others => null;
|
| 968 |
|
|
end case;
|
| 969 |
|
|
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
|
| 970 |
|
|
-- RST p
|
| 971 |
|
|
MCycles <= "011";
|
| 972 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 973 |
|
|
when 1 =>
|
| 974 |
|
|
TStates <= "101";
|
| 975 |
|
|
IncDec_16 <= "1111";
|
| 976 |
|
|
Set_Addr_To <= aSP;
|
| 977 |
|
|
Set_BusB_To <= "1101";
|
| 978 |
|
|
when 2 =>
|
| 979 |
|
|
Write <= '1';
|
| 980 |
|
|
IncDec_16 <= "1111";
|
| 981 |
|
|
Set_Addr_To <= aSP;
|
| 982 |
|
|
Set_BusB_To <= "1100";
|
| 983 |
|
|
when 3 =>
|
| 984 |
|
|
Write <= '1';
|
| 985 |
|
|
RstP <= '1';
|
| 986 |
|
|
when others => null;
|
| 987 |
|
|
end case;
|
| 988 |
|
|
|
| 989 |
|
|
-- INPUT AND OUTPUT GROUP
|
| 990 |
|
|
when "11011011" =>
|
| 991 |
|
|
-- IN A,(n)
|
| 992 |
|
|
MCycles <= "011";
|
| 993 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 994 |
|
|
when 2 =>
|
| 995 |
|
|
Inc_PC <= '1';
|
| 996 |
|
|
Set_Addr_To <= aIOA;
|
| 997 |
|
|
when 3 =>
|
| 998 |
|
|
Read_To_Acc <= '1';
|
| 999 |
|
|
IORQ <= '1';
|
| 1000 |
|
|
when others => null;
|
| 1001 |
|
|
end case;
|
| 1002 |
|
|
when "11010011" =>
|
| 1003 |
|
|
-- OUT (n),A
|
| 1004 |
|
|
MCycles <= "011";
|
| 1005 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1006 |
|
|
when 2 =>
|
| 1007 |
|
|
Inc_PC <= '1';
|
| 1008 |
|
|
Set_Addr_To <= aIOA;
|
| 1009 |
|
|
Set_BusB_To <= "0111";
|
| 1010 |
|
|
when 3 =>
|
| 1011 |
|
|
Write <= '1';
|
| 1012 |
|
|
IORQ <= '1';
|
| 1013 |
|
|
when others => null;
|
| 1014 |
|
|
end case;
|
| 1015 |
|
|
|
| 1016 |
|
|
------------------------------------------------------------------------------
|
| 1017 |
|
|
------------------------------------------------------------------------------
|
| 1018 |
|
|
-- MULTIBYTE INSTRUCTIONS
|
| 1019 |
|
|
------------------------------------------------------------------------------
|
| 1020 |
|
|
------------------------------------------------------------------------------
|
| 1021 |
|
|
|
| 1022 |
|
|
when "11001011" =>
|
| 1023 |
|
|
if Mode /= 2 then
|
| 1024 |
|
|
Prefix <= "01";
|
| 1025 |
|
|
end if;
|
| 1026 |
|
|
|
| 1027 |
|
|
when "11101101" =>
|
| 1028 |
|
|
if Mode < 2 then
|
| 1029 |
|
|
Prefix <= "10";
|
| 1030 |
|
|
end if;
|
| 1031 |
|
|
|
| 1032 |
|
|
when "11011101"|"11111101" =>
|
| 1033 |
|
|
if Mode < 2 then
|
| 1034 |
|
|
Prefix <= "11";
|
| 1035 |
|
|
end if;
|
| 1036 |
|
|
|
| 1037 |
|
|
end case;
|
| 1038 |
|
|
|
| 1039 |
|
|
when "01" =>
|
| 1040 |
|
|
|
| 1041 |
|
|
------------------------------------------------------------------------------
|
| 1042 |
|
|
--
|
| 1043 |
|
|
-- CB prefixed instructions
|
| 1044 |
|
|
--
|
| 1045 |
|
|
------------------------------------------------------------------------------
|
| 1046 |
|
|
|
| 1047 |
|
|
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
|
| 1048 |
|
|
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
|
| 1049 |
|
|
|
| 1050 |
|
|
case IRB is
|
| 1051 |
|
|
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|
| 1052 |
|
|
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|
| 1053 |
|
|
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|
| 1054 |
|
|
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|
| 1055 |
|
|
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|
| 1056 |
|
|
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|
| 1057 |
|
|
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|
| 1058 |
|
|
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
|
| 1059 |
|
|
-- RLC r
|
| 1060 |
|
|
-- RL r
|
| 1061 |
|
|
-- RRC r
|
| 1062 |
|
|
-- RR r
|
| 1063 |
|
|
-- SLA r
|
| 1064 |
|
|
-- SRA r
|
| 1065 |
|
|
-- SRL r
|
| 1066 |
|
|
-- SLL r (Undocumented)
|
| 1067 |
|
|
Rot_Op <= '1';
|
| 1068 |
|
|
Read_To_Reg <= '1';
|
| 1069 |
|
|
Save_ALU <= '1';
|
| 1070 |
|
|
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
|
| 1071 |
|
|
-- RLC (HL)
|
| 1072 |
|
|
-- RL (HL)
|
| 1073 |
|
|
-- RRC (HL)
|
| 1074 |
|
|
-- RR (HL)
|
| 1075 |
|
|
-- SRA (HL)
|
| 1076 |
|
|
-- SRL (HL)
|
| 1077 |
|
|
-- SLA (HL)
|
| 1078 |
|
|
-- SLL (HL) (Undocumented)
|
| 1079 |
|
|
MCycles <= "011";
|
| 1080 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1081 |
|
|
when 1 =>
|
| 1082 |
|
|
Set_Addr_To <= aXY;
|
| 1083 |
|
|
when 2 =>
|
| 1084 |
|
|
Rot_Op <= '1';
|
| 1085 |
|
|
Read_To_Reg <= '1';
|
| 1086 |
|
|
Save_ALU <= '1';
|
| 1087 |
|
|
Set_Addr_To <= aXY;
|
| 1088 |
|
|
when 3 =>
|
| 1089 |
|
|
Write <= '1';
|
| 1090 |
|
|
TStates <= "011";
|
| 1091 |
|
|
when others =>
|
| 1092 |
|
|
end case;
|
| 1093 |
|
|
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|
| 1094 |
|
|
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|
| 1095 |
|
|
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|
| 1096 |
|
|
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|
| 1097 |
|
|
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|
| 1098 |
|
|
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|
| 1099 |
|
|
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|
| 1100 |
|
|
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
|
| 1101 |
|
|
-- BIT b,r
|
| 1102 |
|
|
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
|
| 1103 |
|
|
Bit_Op <= "01";
|
| 1104 |
|
|
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
|
| 1105 |
|
|
-- BIT b,(HL)
|
| 1106 |
|
|
MCycles <= "010";
|
| 1107 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1108 |
|
|
when 1 =>
|
| 1109 |
|
|
Set_Addr_To <= aXY;
|
| 1110 |
|
|
when 2 =>
|
| 1111 |
|
|
Bit_Op <= "01";
|
| 1112 |
|
|
when others => null;
|
| 1113 |
|
|
end case;
|
| 1114 |
|
|
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|
| 1115 |
|
|
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|
| 1116 |
|
|
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|
| 1117 |
|
|
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|
| 1118 |
|
|
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|
| 1119 |
|
|
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|
| 1120 |
|
|
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|
| 1121 |
|
|
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
|
| 1122 |
|
|
-- SET b,r
|
| 1123 |
|
|
Bit_Op <= "10";
|
| 1124 |
|
|
Read_To_Reg <= '1';
|
| 1125 |
|
|
Save_ALU <= '1';
|
| 1126 |
|
|
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
|
| 1127 |
|
|
-- SET b,(HL)
|
| 1128 |
|
|
MCycles <= "011";
|
| 1129 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1130 |
|
|
when 1 =>
|
| 1131 |
|
|
Set_Addr_To <= aXY;
|
| 1132 |
|
|
when 2 =>
|
| 1133 |
|
|
Bit_Op <= "10";
|
| 1134 |
|
|
Read_To_Reg <= '1';
|
| 1135 |
|
|
Save_ALU <= '1';
|
| 1136 |
|
|
Set_Addr_To <= aXY;
|
| 1137 |
|
|
when 3 =>
|
| 1138 |
|
|
Write <= '1';
|
| 1139 |
|
|
when others => null;
|
| 1140 |
|
|
end case;
|
| 1141 |
|
|
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|
| 1142 |
|
|
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|
| 1143 |
|
|
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|
| 1144 |
|
|
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|
| 1145 |
|
|
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|
| 1146 |
|
|
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|
| 1147 |
|
|
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|
| 1148 |
|
|
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
|
| 1149 |
|
|
-- RES b,r
|
| 1150 |
|
|
Bit_Op <= "11";
|
| 1151 |
|
|
Read_To_Reg <= '1';
|
| 1152 |
|
|
Save_ALU <= '1';
|
| 1153 |
|
|
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
|
| 1154 |
|
|
-- RES b,(HL)
|
| 1155 |
|
|
MCycles <= "011";
|
| 1156 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1157 |
|
|
when 1 =>
|
| 1158 |
|
|
Set_Addr_To <= aXY;
|
| 1159 |
|
|
when 2 =>
|
| 1160 |
|
|
Bit_Op <= "11";
|
| 1161 |
|
|
Read_To_Reg <= '1';
|
| 1162 |
|
|
Save_ALU <= '1';
|
| 1163 |
|
|
Set_Addr_To <= aXY;
|
| 1164 |
|
|
when 3 =>
|
| 1165 |
|
|
Write <= '1';
|
| 1166 |
|
|
when others => null;
|
| 1167 |
|
|
end case;
|
| 1168 |
|
|
end case;
|
| 1169 |
|
|
|
| 1170 |
|
|
when others =>
|
| 1171 |
|
|
|
| 1172 |
|
|
------------------------------------------------------------------------------
|
| 1173 |
|
|
--
|
| 1174 |
|
|
-- ED prefixed instructions
|
| 1175 |
|
|
--
|
| 1176 |
|
|
------------------------------------------------------------------------------
|
| 1177 |
|
|
|
| 1178 |
|
|
case IRB is
|
| 1179 |
|
|
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|
| 1180 |
|
|
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|
| 1181 |
|
|
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|
| 1182 |
|
|
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|
| 1183 |
|
|
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|
| 1184 |
|
|
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|
| 1185 |
|
|
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|
| 1186 |
|
|
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|
| 1187 |
|
|
|
| 1188 |
|
|
|
| 1189 |
|
|
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|
| 1190 |
|
|
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|
| 1191 |
|
|
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|
| 1192 |
|
|
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
|
| 1193 |
|
|
| "10100100"|"10100101"|"10100110"|"10100111"
|
| 1194 |
|
|
| "10101100"|"10101101"|"10101110"|"10101111"
|
| 1195 |
|
|
| "10110100"|"10110101"|"10110110"|"10110111"
|
| 1196 |
|
|
| "10111100"|"10111101"|"10111110"|"10111111"
|
| 1197 |
|
|
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|
| 1198 |
|
|
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|
| 1199 |
|
|
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|
| 1200 |
|
|
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|
| 1201 |
|
|
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|
| 1202 |
|
|
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|
| 1203 |
|
|
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|
| 1204 |
|
|
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
|
| 1205 |
|
|
null; -- NOP, undocumented
|
| 1206 |
|
|
when "01111110"|"01111111" =>
|
| 1207 |
|
|
-- NOP, undocumented
|
| 1208 |
|
|
null;
|
| 1209 |
|
|
-- 8 BIT LOAD GROUP
|
| 1210 |
|
|
when "01010111" =>
|
| 1211 |
|
|
-- LD A,I
|
| 1212 |
|
|
Special_LD <= "100";
|
| 1213 |
|
|
TStates <= "101";
|
| 1214 |
|
|
when "01011111" =>
|
| 1215 |
|
|
-- LD A,R
|
| 1216 |
|
|
Special_LD <= "101";
|
| 1217 |
|
|
TStates <= "101";
|
| 1218 |
|
|
when "01000111" =>
|
| 1219 |
|
|
-- LD I,A
|
| 1220 |
|
|
Special_LD <= "110";
|
| 1221 |
|
|
TStates <= "101";
|
| 1222 |
|
|
when "01001111" =>
|
| 1223 |
|
|
-- LD R,A
|
| 1224 |
|
|
Special_LD <= "111";
|
| 1225 |
|
|
TStates <= "101";
|
| 1226 |
|
|
-- 16 BIT LOAD GROUP
|
| 1227 |
|
|
when "01001011"|"01011011"|"01101011"|"01111011" =>
|
| 1228 |
|
|
-- LD dd,(nn)
|
| 1229 |
|
|
MCycles <= "101";
|
| 1230 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1231 |
|
|
when 2 =>
|
| 1232 |
|
|
Inc_PC <= '1';
|
| 1233 |
|
|
LDZ <= '1';
|
| 1234 |
|
|
when 3 =>
|
| 1235 |
|
|
Set_Addr_To <= aZI;
|
| 1236 |
|
|
Inc_PC <= '1';
|
| 1237 |
|
|
LDW <= '1';
|
| 1238 |
|
|
when 4 =>
|
| 1239 |
|
|
Read_To_Reg <= '1';
|
| 1240 |
|
|
if IR(5 downto 4) = "11" then
|
| 1241 |
|
|
Set_BusA_To <= "1000";
|
| 1242 |
|
|
else
|
| 1243 |
|
|
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
|
| 1244 |
|
|
Set_BusA_To(0) <= '1';
|
| 1245 |
|
|
end if;
|
| 1246 |
|
|
Inc_WZ <= '1';
|
| 1247 |
|
|
Set_Addr_To <= aZI;
|
| 1248 |
|
|
when 5 =>
|
| 1249 |
|
|
Read_To_Reg <= '1';
|
| 1250 |
|
|
if IR(5 downto 4) = "11" then
|
| 1251 |
|
|
Set_BusA_To <= "1001";
|
| 1252 |
|
|
else
|
| 1253 |
|
|
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
|
| 1254 |
|
|
Set_BusA_To(0) <= '0';
|
| 1255 |
|
|
end if;
|
| 1256 |
|
|
when others => null;
|
| 1257 |
|
|
end case;
|
| 1258 |
|
|
when "01000011"|"01010011"|"01100011"|"01110011" =>
|
| 1259 |
|
|
-- LD (nn),dd
|
| 1260 |
|
|
MCycles <= "101";
|
| 1261 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1262 |
|
|
when 2 =>
|
| 1263 |
|
|
Inc_PC <= '1';
|
| 1264 |
|
|
LDZ <= '1';
|
| 1265 |
|
|
when 3 =>
|
| 1266 |
|
|
Set_Addr_To <= aZI;
|
| 1267 |
|
|
Inc_PC <= '1';
|
| 1268 |
|
|
LDW <= '1';
|
| 1269 |
|
|
if IR(5 downto 4) = "11" then
|
| 1270 |
|
|
Set_BusB_To <= "1000";
|
| 1271 |
|
|
else
|
| 1272 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1273 |
|
|
Set_BusB_To(0) <= '1';
|
| 1274 |
|
|
Set_BusB_To(3) <= '0';
|
| 1275 |
|
|
end if;
|
| 1276 |
|
|
when 4 =>
|
| 1277 |
|
|
Inc_WZ <= '1';
|
| 1278 |
|
|
Set_Addr_To <= aZI;
|
| 1279 |
|
|
Write <= '1';
|
| 1280 |
|
|
if IR(5 downto 4) = "11" then
|
| 1281 |
|
|
Set_BusB_To <= "1001";
|
| 1282 |
|
|
else
|
| 1283 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1284 |
|
|
Set_BusB_To(0) <= '0';
|
| 1285 |
|
|
Set_BusB_To(3) <= '0';
|
| 1286 |
|
|
end if;
|
| 1287 |
|
|
when 5 =>
|
| 1288 |
|
|
Write <= '1';
|
| 1289 |
|
|
when others => null;
|
| 1290 |
|
|
end case;
|
| 1291 |
|
|
when "10100000" | "10101000" | "10110000" | "10111000" =>
|
| 1292 |
|
|
-- LDI, LDD, LDIR, LDDR
|
| 1293 |
|
|
MCycles <= "011";
|
| 1294 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1295 |
|
|
when 1 =>
|
| 1296 |
|
|
Set_Addr_To <= aXY;
|
| 1297 |
|
|
IncDec_16 <= "1100"; -- BC
|
| 1298 |
|
|
when 2 =>
|
| 1299 |
|
|
Set_BusB_To <= "0110";
|
| 1300 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 1301 |
|
|
ALU_Op <= "1000";
|
| 1302 |
|
|
Set_Addr_To <= aDE;
|
| 1303 |
|
|
if IR(3) = '0' then
|
| 1304 |
|
|
IncDec_16 <= "0110"; -- IX
|
| 1305 |
|
|
else
|
| 1306 |
|
|
IncDec_16 <= "1110";
|
| 1307 |
|
|
end if;
|
| 1308 |
|
|
when 3 =>
|
| 1309 |
|
|
I_BT <= '1';
|
| 1310 |
|
|
TStates <= "101";
|
| 1311 |
|
|
Write <= '1';
|
| 1312 |
|
|
if IR(3) = '0' then
|
| 1313 |
|
|
IncDec_16 <= "0101"; -- DE
|
| 1314 |
|
|
else
|
| 1315 |
|
|
IncDec_16 <= "1101";
|
| 1316 |
|
|
end if;
|
| 1317 |
|
|
if IR(4) = '1' and F(2) = '1' then
|
| 1318 |
|
|
MCycles <= "100";
|
| 1319 |
|
|
end if;
|
| 1320 |
|
|
when 4 =>
|
| 1321 |
|
|
I_BTR <= '1';
|
| 1322 |
|
|
TStates <= "101";
|
| 1323 |
|
|
MCycles <= "100";
|
| 1324 |
|
|
when others => null;
|
| 1325 |
|
|
end case;
|
| 1326 |
|
|
when "10100001" | "10101001" | "10110001" | "10111001" =>
|
| 1327 |
|
|
-- CPI, CPD, CPIR, CPDR
|
| 1328 |
|
|
MCycles <= "011";
|
| 1329 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1330 |
|
|
when 1 =>
|
| 1331 |
|
|
Set_Addr_To <= aXY;
|
| 1332 |
|
|
IncDec_16 <= "1100"; -- BC
|
| 1333 |
|
|
when 2 =>
|
| 1334 |
|
|
Set_BusB_To <= "0110";
|
| 1335 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 1336 |
|
|
ALU_Op <= "1111";
|
| 1337 |
|
|
Save_ALU <= '1';
|
| 1338 |
|
|
PreserveC <= '1';
|
| 1339 |
|
|
if IR(3) = '0' then
|
| 1340 |
|
|
IncDec_16 <= "0110";
|
| 1341 |
|
|
else
|
| 1342 |
|
|
IncDec_16 <= "1110";
|
| 1343 |
|
|
end if;
|
| 1344 |
|
|
when 3 =>
|
| 1345 |
|
|
I_BC <= '1';
|
| 1346 |
|
|
TStates <= "101";
|
| 1347 |
|
|
if IR(4) = '1' and F(2) = '1' and F(6) = '0' then
|
| 1348 |
|
|
MCycles <= "100";
|
| 1349 |
|
|
end if;
|
| 1350 |
|
|
when 4 =>
|
| 1351 |
|
|
I_BTR <= '1';
|
| 1352 |
|
|
TStates <= "101";
|
| 1353 |
|
|
MCycles <= "100";
|
| 1354 |
|
|
when others => null;
|
| 1355 |
|
|
end case;
|
| 1356 |
|
|
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
|
| 1357 |
|
|
-- NEG
|
| 1358 |
|
|
Alu_OP <= "1010";
|
| 1359 |
|
|
Set_BusB_To <= "0111";
|
| 1360 |
|
|
Set_BusA_To <= "1010";
|
| 1361 |
|
|
Read_To_Acc <= '1';
|
| 1362 |
|
|
Save_ALU <= '1';
|
| 1363 |
|
|
when "01000110"|"01001110"|"01100110"|"01101110" =>
|
| 1364 |
|
|
-- IM 0
|
| 1365 |
|
|
IMode <= "00";
|
| 1366 |
|
|
when "01010110"|"01110110" =>
|
| 1367 |
|
|
-- IM 1
|
| 1368 |
|
|
IMode <= "01";
|
| 1369 |
|
|
when "01011110"|"01110111" =>
|
| 1370 |
|
|
-- IM 2
|
| 1371 |
|
|
IMode <= "10";
|
| 1372 |
|
|
-- 16 bit arithmetic
|
| 1373 |
|
|
when "01001010"|"01011010"|"01101010"|"01111010" =>
|
| 1374 |
|
|
-- ADC HL,ss
|
| 1375 |
|
|
MCycles <= "011";
|
| 1376 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1377 |
|
|
when 2 =>
|
| 1378 |
|
|
ALU_Op <= "1001";
|
| 1379 |
|
|
Read_To_Reg <= '1';
|
| 1380 |
|
|
Save_ALU <= '1';
|
| 1381 |
|
|
Set_BusA_To(2 downto 0) <= "101";
|
| 1382 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 1383 |
|
|
when 0|1|2 =>
|
| 1384 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1385 |
|
|
Set_BusB_To(0) <= '1';
|
| 1386 |
|
|
when others =>
|
| 1387 |
|
|
Set_BusB_To <= "1000";
|
| 1388 |
|
|
end case;
|
| 1389 |
|
|
when 3 =>
|
| 1390 |
|
|
Read_To_Reg <= '1';
|
| 1391 |
|
|
Save_ALU <= '1';
|
| 1392 |
|
|
ALU_Op <= "1001";
|
| 1393 |
|
|
Set_BusA_To(2 downto 0) <= "100";
|
| 1394 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 1395 |
|
|
when 0|1|2 =>
|
| 1396 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1397 |
|
|
Set_BusB_To(0) <= '0';
|
| 1398 |
|
|
when others =>
|
| 1399 |
|
|
Set_BusB_To <= "1001";
|
| 1400 |
|
|
end case;
|
| 1401 |
|
|
TStates <= "011";
|
| 1402 |
|
|
when others =>
|
| 1403 |
|
|
end case;
|
| 1404 |
|
|
when "01000010"|"01010010"|"01100010"|"01110010" =>
|
| 1405 |
|
|
-- SBC HL,ss
|
| 1406 |
|
|
MCycles <= "011";
|
| 1407 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1408 |
|
|
when 2 =>
|
| 1409 |
|
|
ALU_Op <= "1011";
|
| 1410 |
|
|
Read_To_Reg <= '1';
|
| 1411 |
|
|
Save_ALU <= '1';
|
| 1412 |
|
|
Set_BusA_To(2 downto 0) <= "101";
|
| 1413 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 1414 |
|
|
when 0|1|2 =>
|
| 1415 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1416 |
|
|
Set_BusB_To(0) <= '1';
|
| 1417 |
|
|
when others =>
|
| 1418 |
|
|
Set_BusB_To <= "1000";
|
| 1419 |
|
|
end case;
|
| 1420 |
|
|
when 3 =>
|
| 1421 |
|
|
ALU_Op <= "1011";
|
| 1422 |
|
|
Read_To_Reg <= '1';
|
| 1423 |
|
|
Save_ALU <= '1';
|
| 1424 |
|
|
Set_BusA_To(2 downto 0) <= "100";
|
| 1425 |
|
|
case to_integer(unsigned(IR(5 downto 4))) is
|
| 1426 |
|
|
when 0|1|2 =>
|
| 1427 |
|
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
| 1428 |
|
|
when others =>
|
| 1429 |
|
|
Set_BusB_To <= "1001";
|
| 1430 |
|
|
end case;
|
| 1431 |
|
|
TStates <= "011";
|
| 1432 |
|
|
when others =>
|
| 1433 |
|
|
end case;
|
| 1434 |
|
|
when "01101111" =>
|
| 1435 |
|
|
-- RLD
|
| 1436 |
|
|
MCycles <= "100";
|
| 1437 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1438 |
|
|
when 2 =>
|
| 1439 |
|
|
Set_Addr_To <= aXY;
|
| 1440 |
|
|
when 3 =>
|
| 1441 |
|
|
Read_To_Reg <= '1';
|
| 1442 |
|
|
Set_BusB_To(2 downto 0) <= "110";
|
| 1443 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 1444 |
|
|
ALU_Op <= "1101";
|
| 1445 |
|
|
TStates <= "100";
|
| 1446 |
|
|
Set_Addr_To <= aXY;
|
| 1447 |
|
|
Save_ALU <= '1';
|
| 1448 |
|
|
when 4 =>
|
| 1449 |
|
|
I_RLD <= '1';
|
| 1450 |
|
|
Write <= '1';
|
| 1451 |
|
|
when others =>
|
| 1452 |
|
|
end case;
|
| 1453 |
|
|
when "01100111" =>
|
| 1454 |
|
|
-- RRD
|
| 1455 |
|
|
MCycles <= "100";
|
| 1456 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1457 |
|
|
when 2 =>
|
| 1458 |
|
|
Set_Addr_To <= aXY;
|
| 1459 |
|
|
when 3 =>
|
| 1460 |
|
|
Read_To_Reg <= '1';
|
| 1461 |
|
|
Set_BusB_To(2 downto 0) <= "110";
|
| 1462 |
|
|
Set_BusA_To(2 downto 0) <= "111";
|
| 1463 |
|
|
ALU_Op <= "1110";
|
| 1464 |
|
|
TStates <= "100";
|
| 1465 |
|
|
Set_Addr_To <= aXY;
|
| 1466 |
|
|
Save_ALU <= '1';
|
| 1467 |
|
|
when 4 =>
|
| 1468 |
|
|
I_RRD <= '1';
|
| 1469 |
|
|
Write <= '1';
|
| 1470 |
|
|
when others =>
|
| 1471 |
|
|
end case;
|
| 1472 |
|
|
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
|
| 1473 |
|
|
-- RETI, RETN
|
| 1474 |
|
|
MCycles <= "011";
|
| 1475 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1476 |
|
|
when 1 =>
|
| 1477 |
|
|
Set_Addr_TO <= aSP;
|
| 1478 |
|
|
when 2 =>
|
| 1479 |
|
|
IncDec_16 <= "0111";
|
| 1480 |
|
|
Set_Addr_To <= aSP;
|
| 1481 |
|
|
LDZ <= '1';
|
| 1482 |
|
|
when 3 =>
|
| 1483 |
|
|
Jump <= '1';
|
| 1484 |
|
|
IncDec_16 <= "0111";
|
| 1485 |
|
|
I_RETN <= '1';
|
| 1486 |
|
|
when others => null;
|
| 1487 |
|
|
end case;
|
| 1488 |
|
|
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
|
| 1489 |
|
|
-- IN r,(C)
|
| 1490 |
|
|
MCycles <= "010";
|
| 1491 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1492 |
|
|
when 1 =>
|
| 1493 |
|
|
Set_Addr_To <= aBC;
|
| 1494 |
|
|
when 2 =>
|
| 1495 |
|
|
IORQ <= '1';
|
| 1496 |
|
|
if IR(5 downto 3) /= "110" then
|
| 1497 |
|
|
Read_To_Reg <= '1';
|
| 1498 |
|
|
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
|
| 1499 |
|
|
end if;
|
| 1500 |
|
|
I_INRC <= '1';
|
| 1501 |
|
|
when others =>
|
| 1502 |
|
|
end case;
|
| 1503 |
|
|
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
|
| 1504 |
|
|
-- OUT (C),r
|
| 1505 |
|
|
-- OUT (C),0
|
| 1506 |
|
|
MCycles <= "010";
|
| 1507 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1508 |
|
|
when 1 =>
|
| 1509 |
|
|
Set_Addr_To <= aBC;
|
| 1510 |
|
|
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
|
| 1511 |
|
|
if IR(5 downto 3) = "110" then
|
| 1512 |
|
|
Set_BusB_To(3) <= '1';
|
| 1513 |
|
|
end if;
|
| 1514 |
|
|
when 2 =>
|
| 1515 |
|
|
Write <= '1';
|
| 1516 |
|
|
IORQ <= '1';
|
| 1517 |
|
|
when others =>
|
| 1518 |
|
|
end case;
|
| 1519 |
|
|
when "10100010" | "10101010" | "10110010" | "10111010" =>
|
| 1520 |
|
|
-- INI, IND, INIR, INDR
|
| 1521 |
|
|
MCycles <= "011";
|
| 1522 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1523 |
|
|
when 1 =>
|
| 1524 |
|
|
TStates <= "101";
|
| 1525 |
|
|
Set_Addr_To <= aBC;
|
| 1526 |
|
|
Set_BusB_To <= "1010";
|
| 1527 |
|
|
Set_BusA_To <= "0000";
|
| 1528 |
|
|
Read_To_Reg <= '1';
|
| 1529 |
|
|
Save_ALU <= '1';
|
| 1530 |
|
|
ALU_Op <= "1010";
|
| 1531 |
|
|
when 2 =>
|
| 1532 |
|
|
IORQ <= '1';
|
| 1533 |
|
|
Set_BusB_To <= "0110";
|
| 1534 |
|
|
Set_Addr_To <= aXY;
|
| 1535 |
|
|
when 3 =>
|
| 1536 |
|
|
if IR(3) = '0' then
|
| 1537 |
|
|
IncDec_16 <= "0010";
|
| 1538 |
|
|
else
|
| 1539 |
|
|
IncDec_16 <= "1010";
|
| 1540 |
|
|
end if;
|
| 1541 |
|
|
TStates <= "100";
|
| 1542 |
|
|
Write <= '1';
|
| 1543 |
|
|
if IR(4) = '1' and F(6) = '0' then
|
| 1544 |
|
|
MCycles <= "100";
|
| 1545 |
|
|
end if;
|
| 1546 |
|
|
when 4 =>
|
| 1547 |
|
|
I_BTR <= '1';
|
| 1548 |
|
|
TStates <= "101";
|
| 1549 |
|
|
MCycles <= "100";
|
| 1550 |
|
|
when others => null;
|
| 1551 |
|
|
end case;
|
| 1552 |
|
|
when "10100011" | "10101011" | "10110011" | "10111011" =>
|
| 1553 |
|
|
-- OUTI, OUTD, OTIR, OTDR
|
| 1554 |
|
|
MCycles <= "011";
|
| 1555 |
|
|
case to_integer(unsigned(MCycle)) is
|
| 1556 |
|
|
when 1 =>
|
| 1557 |
|
|
TStates <= "101";
|
| 1558 |
|
|
Set_Addr_To <= aXY;
|
| 1559 |
|
|
Set_BusB_To <= "1010";
|
| 1560 |
|
|
Set_BusA_To <= "0000";
|
| 1561 |
|
|
Read_To_Reg <= '1';
|
| 1562 |
|
|
Save_ALU <= '1';
|
| 1563 |
|
|
ALU_Op <= "1010";
|
| 1564 |
|
|
when 2 =>
|
| 1565 |
|
|
Set_BusB_To <= "0110";
|
| 1566 |
|
|
Set_Addr_To <= aBC;
|
| 1567 |
|
|
when 3 =>
|
| 1568 |
|
|
if IR(3) = '0' then
|
| 1569 |
|
|
IncDec_16 <= "0010";
|
| 1570 |
|
|
else
|
| 1571 |
|
|
IncDec_16 <= "1010";
|
| 1572 |
|
|
end if;
|
| 1573 |
|
|
IORQ <= '1';
|
| 1574 |
|
|
TStates <= "100";
|
| 1575 |
|
|
Write <= '1';
|
| 1576 |
|
|
if IR(4) = '1' and F(6) = '0' then
|
| 1577 |
|
|
MCycles <= "100";
|
| 1578 |
|
|
end if;
|
| 1579 |
|
|
when 4 =>
|
| 1580 |
|
|
I_BTR <= '1';
|
| 1581 |
|
|
TStates <= "101";
|
| 1582 |
|
|
MCycles <= "100";
|
| 1583 |
|
|
when others => null;
|
| 1584 |
|
|
end case;
|
| 1585 |
|
|
end case;
|
| 1586 |
|
|
|
| 1587 |
|
|
end case;
|
| 1588 |
|
|
|
| 1589 |
|
|
if Mode = 1 then
|
| 1590 |
|
|
if MCycle = "001" then
|
| 1591 |
|
|
-- TStates <= "100";
|
| 1592 |
|
|
else
|
| 1593 |
|
|
TStates <= "011";
|
| 1594 |
|
|
end if;
|
| 1595 |
|
|
end if;
|
| 1596 |
|
|
|
| 1597 |
|
|
end process;
|
| 1598 |
|
|
|
| 1599 |
|
|
end;
|
