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[/] [t80/] [trunk/] [sw/] [xrom.cpp] - Blame information for rev 3

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//
// Xilinx VHDL ROM generator
//
// Version : 0220
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//      http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//      Requires stl to compile
//
// File history :
//
// 0220 : Initial release
//
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
        // VC fix
        #define max __max
#endif
 
class File
{
public:
        explicit File(const char *fileName, const char *mode)
        {
                m_file = fopen(fileName, mode);
                if (m_file != NULL)
                {
                        return;
                }
                string errorStr = "Error opening ";
                errorStr += fileName;
                errorStr += "\n";
                throw errorStr;
        }
 
        ~File()
        {
                fclose(m_file);
        }
 
        FILE *Handle() { return m_file; };
private:
        FILE                            *m_file;
};
 
int main (int argc, char *argv[])
{
        cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0220\n";
 
        try
        {
                unsigned long aWidth;
                unsigned long dWidth;
                unsigned long select = 0;
                char z = 0;
 
                if (argc < 4)
                {
                        cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
                        cerr << "\nThe options can be:\n";
                        cerr << "  -[deciamal number] = SelectRAM usage in 1/16 parts\n";
                        cerr << "  -z = use tri-state buses\n";
                        cerr << "\nExample:\n";
                        cerr << "  xrom Test_ROM 13 8 -6\n\n";
                        return -1;
                }
 
                int result;
 
                result = sscanf(argv[2], "%lu", &aWidth);
                if (result < 1)
                {
                        throw "Error in address bits argument!\n";
                }
 
                result = sscanf(argv[3], "%lu", &dWidth);
                if (result < 1)
                {
                        throw "Error in data bits argument!\n";
                }
 
                if (argc > 4)
                {
                        result = sscanf(argv[4], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[4], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                if (argc > 5)
                {
                        result = sscanf(argv[5], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[5], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                string  outFileName = argv[1];
                outFileName = outFileName + ".vhd";
 
                File    outFile(outFileName.c_str(), "wt");
 
                unsigned long selectIter = 0;
                unsigned long blockIter = 0;
                unsigned long bytes = (dWidth + 7) / 8;
 
                if (!select)
                {
                        blockIter = ((1UL << aWidth) + 511) / 512;
                }
                else if (select == 16)
                {
                        selectIter = ((1UL << aWidth) + 15) / 16;
                }
                else
                {
                        blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
                        selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
                }
 
                fprintf(outFile.Handle(), "-- This file was generated with xrom written by Daniel Wallner\n");
                fprintf(outFile.Handle(), "\nlibrary IEEE;");
                fprintf(outFile.Handle(), "\nuse IEEE.std_logic_1164.all;");
                fprintf(outFile.Handle(), "\nuse IEEE.numeric_std.all;");
                fprintf(outFile.Handle(), "\nlibrary UNISIM;");
                fprintf(outFile.Handle(), "\nuse UNISIM.vcomponents.all;");
                fprintf(outFile.Handle(), "\n\nentity %s is", argv[1]);
                fprintf(outFile.Handle(), "\n\tport(");
                fprintf(outFile.Handle(), "\n\t\tClk\t: in std_logic;");
                fprintf(outFile.Handle(), "\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
                fprintf(outFile.Handle(), "\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
                fprintf(outFile.Handle(), "\n\t);");
                fprintf(outFile.Handle(), "\nend %s;", outFileName.c_str());
                fprintf(outFile.Handle(), "\n\narchitecture rtl of %s is", argv[1]);
 
                fprintf(outFile.Handle(), "\n\tsignal zero : std_logic := '0';");
                fprintf(outFile.Handle(), "\n\tsignal DI : std_logic_vector(7 downto 0) := \"-------\";");
                if (selectIter > 0)
                {
                        fprintf(outFile.Handle(), "\n\tsignal A_r: unsigned(A'range);");
                }
                if (selectIter > 1)
                {
                        fprintf(outFile.Handle(), "\n\tsignal sEN : unsigned(%d downto 0);", selectIter - 1);
                        fprintf(outFile.Handle(), "\n\ttype sRAMOut is array (0 to %d) of UNSIGNED(D'range);", selectIter - 1);
                        fprintf(outFile.Handle(), "\n\tsignal sRAMOut : sRAMOut_a;");
                        fprintf(outFile.Handle(), "\n\tsignal siA, siA2 : integer;");
                }
                if (blockIter > 1)
                {
                        fprintf(outFile.Handle(), "\n\tsignal bEN : unsigned(%d downto 0);", blockIter - 1);
                        fprintf(outFile.Handle(), "\n\ttype bRAMOut_a is array (0 to %d) of UNSIGNED(D'range);", blockIter - 1);
                        fprintf(outFile.Handle(), "\n\tsignal bRAMOut : bRAMOut_a;");
                        fprintf(outFile.Handle(), "\n\tsignal biA, biA_r : integer;");
                        if (!selectIter)
                        {
                                fprintf(outFile.Handle(), "\n\tsignal A_r: UNSIGNED(A'left downto 9);");
                        }
                }
 
                fprintf(outFile.Handle(), "\nbegin");
 
                if (selectIter > 0 || blockIter > 1)
                {
                        fprintf(outFile.Handle(), "\n\tprocess (Clk)");
                        fprintf(outFile.Handle(), "\n\tbegin");
                        fprintf(outFile.Handle(), "\n\t\tif Clk'event and Clk = '1' then");
                        if (!selectIter)
                        {
                                fprintf(outFile.Handle(), "\n\t\t\tA_r <= A(A'left downto 9);");
                        }
                        else
                        {
                                fprintf(outFile.Handle(), "\n\t\t\tA_r <= A;");
                        }
                        fprintf(outFile.Handle(), "\n\t\tend if;");
                        fprintf(outFile.Handle(), "\n\tend process;");
                }
 
                if (selectIter == 1)
                {
                        fprintf(outFile.Handle(), "\n\tU_ROM: RAMB4_S8\n\t\tport map (Zero, Zero, Clk, A(0), A(1), A(2), A(3), D(0));");
                }
                if (selectIter > 1)
                {
                        fprintf(outFile.Handle(), "\n\n\tsiA <= to_integer(A(A'left downto 4));");
                        fprintf(outFile.Handle(), "\n\tsiA_r <= TO_INTEGER(A_r(A'left downto 4));");
                        fprintf(outFile.Handle(), "\n\n\tprocess (siA)\n\t\tvariable S:UNSIGNED(%d downto 0);", selectIter - 1);
                        fprintf(outFile.Handle(), "\n\tbegin\n\t\tS := TO_UNSIGNED(1,%d);", selectIter);
                        fprintf(outFile.Handle(), "\n\t\tfor I in 0 to %d loop", selectIter - 1);
                        fprintf(outFile.Handle(), "\n\t\t\tif I < iA then\n\t\t\t\tS := SHL(S,\"1\");\n\t\t\tend if;\n\t\tend loop;");
                        fprintf(outFile.Handle(), "\n\t\tbEN <= to_unsigned(S,%d);\n\tend process;", selectIter);
                        fprintf(outFile.Handle(), "\n\n\tsG1_1: for I in 0 to %d generate", selectIter - 1);
                        fprintf(outFile.Handle(), "\n\t\tU_ROM: RAMB4_S8\n\t\t\tport map (DI, sEN(I), Zero, Zero, Clk, A(3 downto 0), bRAMOut(I));");
                        if (z)
                        {
                                fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(I) when iA2=I else (others=>'Z');");
                        }
                        fprintf(outFile.Handle(), "\n\tend generate;");
                        if (!z)
                        {
                                fprintf(outFile.Handle(), "\n\n\tprocess (biA_r,RAMOut)\n\tbegin");
                                fprintf(outFile.Handle(), "\n\t\tD <= sRAMOut(0);");
                                fprintf(outFile.Handle(), "\n\t\tfor I in 1 to %d loop", selectIter - 1);
                                fprintf(outFile.Handle(), "\n\t\t\tif siA_r=I then\n\t\t\t\tD <= sRAMOut(I);\n\t\t\tend if;");
                                fprintf(outFile.Handle(), "\n\t\tend loop;\n\tend process;");
                        }
                }
                if (blockIter == 1)
                {
                        fprintf(outFile.Handle(), "\n\tU_ROM: RAMB4_S8\n\t\tport map (DI, One, Zero, Zero, Clk, A, D);");
                }
                if (blockIter > 1)
                {
                        fprintf(outFile.Handle(), "\n\n\tbiA <= to_integer(A(A'left downto 9));");
                        fprintf(outFile.Handle(), "\n\tbiA_r <= TO_INTEGER(A_r(A'left downto 9));");
                        fprintf(outFile.Handle(), "\n\n\tprocess (biA)\n\t\tvariable S:UNSIGNED(%d downto 0);", blockIter - 1);
                        fprintf(outFile.Handle(), "\n\tbegin\n\t\tS := TO_UNSIGNED(1,%d);", blockIter);
                        fprintf(outFile.Handle(), "\n\t\tfor I in 0 to %d loop", blockIter - 1);
                        fprintf(outFile.Handle(), "\n\t\t\tif I < iA then\n\t\t\t\tS := SHL(S,\"1\");\n\t\t\tend if;\n\t\tend loop;");
                        fprintf(outFile.Handle(), "\n\t\tbEN <= to_unsigned(S,%d);\n\tend process;", blockIter);
                        fprintf(outFile.Handle(), "\n\n\tbG1_1: for I in 0 to %d generate", blockIter - 1);
                        fprintf(outFile.Handle(), "\n\t\tU_ROM: RAMB4_S8\n\t\t\tport map (DI, bEN(I), Zero, Zero, Clk, A(8 downto 0), bRAMOut(I));");
                        if (z)
                        {
                                fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(I) when iA2=I else (others=>'Z');");
                        }
                        fprintf(outFile.Handle(), "\n\tend generate;");
                        if (!z)
                        {
                                fprintf(outFile.Handle(), "\n\n\tprocess (biA_r,RAMOut)\n\tbegin");
                                fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(0);");
                                fprintf(outFile.Handle(), "\n\t\tfor I in 1 to %d loop", blockIter - 1);
                                fprintf(outFile.Handle(), "\n\t\t\tif biA_r=I then\n\t\t\t\tD <= bRAMOut(I);\n\t\t\tend if;");
                                fprintf(outFile.Handle(), "\n\t\tend loop;\n\tend process;");
                        }
                }
 
                fprintf(outFile.Handle(), "\nend;\n");
 
                return 0;
        }
        catch (string error)
        {
                cerr << "Fatal: " << error;
        }
        catch (const char *error)
        {
                cerr << "Fatal: " << error;
        }
        return -1;
}

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Subversion Repositories t80

[/] [t80/] [trunk/] [sw/] [xrom.cpp] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	jesus	`//`
2			`// Xilinx VHDL ROM generator`
3			`//`
4			`// Version : 0220`
5			`//`
6			`// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)`
7			`//`
8			`// All rights reserved`
9			`//`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12			`//`
13			`// Redistributions of source code must retain the above copyright notice,`
14			`// this list of conditions and the following disclaimer.`
15			`//`
16			`// Redistributions in binary form must reproduce the above copyright`
17			`// notice, this list of conditions and the following disclaimer in the`
18			`// documentation and/or other materials provided with the distribution.`
19			`//`
20			`// Neither the name of the author nor the names of other contributors may`
21			`// be used to endorse or promote products derived from this software without`
22			`// specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
26			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
27			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE`
28			`// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
29			`// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF`
30			`// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS`
31			`// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN`
32			`// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
33			`// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
34			`// POSSIBILITY OF SUCH DAMAGE.`
35			`//`
36			`// Please report bugs to the author, but before you do so, please`
37			`// make sure that this is not a derivative work and that`
38			`// you have the latest version of this file.`
39			`//`
40			`// The latest version of this file can be found at:`
41			`// http://www.opencores.org/cvsweb.shtml/t51/`
42			`//`
43			`// Limitations :`
44			`// Requires stl to compile`
45			`//`
46			`// File history :`
47			`//`
48			`// 0220 : Initial release`
49			`//`
50
51			`#include <stdio.h>`
52			`#include <string>`
53			`#include <vector>`
54			`#include <iostream>`
55
56			`using namespace std;`
57
58			`#if !(defined(max)) && _MSC_VER`
59			`// VC fix`
60			`#define max __max`
61			`#endif`
62
63			`class File`
64			`{`
65			`public:`
66			`explicit File(const char fileName, const char mode)`
67			`{`
68			`m_file = fopen(fileName, mode);`
69			`if (m_file != NULL)`
70			`{`
71			`return;`
72			`}`
73			`string errorStr = "Error opening ";`
74			`errorStr += fileName;`
75			`errorStr += "\n";`
76			`throw errorStr;`
77			`}`
78
79			`~File()`
80			`{`
81			`fclose(m_file);`
82			`}`
83
84			`FILE *Handle() { return m_file; };`
85			`private:`
86			`FILE *m_file;`
87			`};`
88
89			`int main (int argc, char *argv[])`
90			`{`
91			`cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0220\n";`
92
93			`try`
94			`{`
95			`unsigned long aWidth;`
96			`unsigned long dWidth;`
97			`unsigned long select = 0;`
98			`char z = 0;`
99
100			`if (argc < 4)`
101			`{`
102			`cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";`
103			`cerr << "\nThe options can be:\n";`
104			`cerr << " -[deciamal number] = SelectRAM usage in 1/16 parts\n";`
105			`cerr << " -z = use tri-state buses\n";`
106			`cerr << "\nExample:\n";`
107			`cerr << " xrom Test_ROM 13 8 -6\n\n";`
108			`return -1;`
109			`}`
110
111			`int result;`
112
113			`result = sscanf(argv[2], "%lu", &aWidth);`
114			`if (result < 1)`
115			`{`
116			`throw "Error in address bits argument!\n";`
117			`}`
118
119			`result = sscanf(argv[3], "%lu", &dWidth);`
120			`if (result < 1)`
121			`{`
122			`throw "Error in data bits argument!\n";`
123			`}`
124
125			`if (argc > 4)`
126			`{`
127			`result = sscanf(argv[4], "%c%lu", &z, &select);`
128			`if (result < 1 \|\| z != '-')`
129			`{`
130			`throw "Error in options!\n";`
131			`}`
132			`if (result < 2)`
133			`{`
134			`sscanf(argv[4], "%c%c", &z, &z);`
135			`if (z != 'z')`
136			`{`
137			`throw "Error in options!\n";`
138			`}`
139			`}`
140			`}`
141
142			`if (argc > 5)`
143			`{`
144			`result = sscanf(argv[5], "%c%lu", &z, &select);`
145			`if (result < 1 \|\| z != '-')`
146			`{`
147			`throw "Error in options!\n";`
148			`}`
149			`if (result < 2)`
150			`{`
151			`sscanf(argv[5], "%c%c", &z, &z);`
152			`if (z != 'z')`
153			`{`
154			`throw "Error in options!\n";`
155			`}`
156			`}`
157			`}`
158
159			`string outFileName = argv[1];`
160			`outFileName = outFileName + ".vhd";`
161
162			`File outFile(outFileName.c_str(), "wt");`
163
164			`unsigned long selectIter = 0;`
165			`unsigned long blockIter = 0;`
166			`unsigned long bytes = (dWidth + 7) / 8;`
167
168			`if (!select)`
169			`{`
170			`blockIter = ((1UL << aWidth) + 511) / 512;`
171			`}`
172			`else if (select == 16)`
173			`{`
174			`selectIter = ((1UL << aWidth) + 15) / 16;`
175			`}`
176			`else`
177			`{`
178			`blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;`
179			`selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;`
180			`}`
181
182			`fprintf(outFile.Handle(), "-- This file was generated with xrom written by Daniel Wallner\n");`
183			`fprintf(outFile.Handle(), "\nlibrary IEEE;");`
184			`fprintf(outFile.Handle(), "\nuse IEEE.std_logic_1164.all;");`
185			`fprintf(outFile.Handle(), "\nuse IEEE.numeric_std.all;");`
186			`fprintf(outFile.Handle(), "\nlibrary UNISIM;");`
187			`fprintf(outFile.Handle(), "\nuse UNISIM.vcomponents.all;");`
188			`fprintf(outFile.Handle(), "\n\nentity %s is", argv[1]);`
189			`fprintf(outFile.Handle(), "\n\tport(");`
190			`fprintf(outFile.Handle(), "\n\t\tClk\t: in std_logic;");`
191			`fprintf(outFile.Handle(), "\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);`
192			`fprintf(outFile.Handle(), "\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);`
193			`fprintf(outFile.Handle(), "\n\t);");`
194			`fprintf(outFile.Handle(), "\nend %s;", outFileName.c_str());`
195			`fprintf(outFile.Handle(), "\n\narchitecture rtl of %s is", argv[1]);`
196
197			`fprintf(outFile.Handle(), "\n\tsignal zero : std_logic := '0';");`
198			`fprintf(outFile.Handle(), "\n\tsignal DI : std_logic_vector(7 downto 0) := \"-------\";");`
199			`if (selectIter > 0)`
200			`{`
201			`fprintf(outFile.Handle(), "\n\tsignal A_r: unsigned(A'range);");`
202			`}`
203			`if (selectIter > 1)`
204			`{`
205			`fprintf(outFile.Handle(), "\n\tsignal sEN : unsigned(%d downto 0);", selectIter - 1);`
206			`fprintf(outFile.Handle(), "\n\ttype sRAMOut is array (0 to %d) of UNSIGNED(D'range);", selectIter - 1);`
207			`fprintf(outFile.Handle(), "\n\tsignal sRAMOut : sRAMOut_a;");`
208			`fprintf(outFile.Handle(), "\n\tsignal siA, siA2 : integer;");`
209			`}`
210			`if (blockIter > 1)`
211			`{`
212			`fprintf(outFile.Handle(), "\n\tsignal bEN : unsigned(%d downto 0);", blockIter - 1);`
213			`fprintf(outFile.Handle(), "\n\ttype bRAMOut_a is array (0 to %d) of UNSIGNED(D'range);", blockIter - 1);`
214			`fprintf(outFile.Handle(), "\n\tsignal bRAMOut : bRAMOut_a;");`
215			`fprintf(outFile.Handle(), "\n\tsignal biA, biA_r : integer;");`
216			`if (!selectIter)`
217			`{`
218			`fprintf(outFile.Handle(), "\n\tsignal A_r: UNSIGNED(A'left downto 9);");`
219			`}`
220			`}`
221
222			`fprintf(outFile.Handle(), "\nbegin");`
223
224			`if (selectIter > 0 \|\| blockIter > 1)`
225			`{`
226			`fprintf(outFile.Handle(), "\n\tprocess (Clk)");`
227			`fprintf(outFile.Handle(), "\n\tbegin");`
228			`fprintf(outFile.Handle(), "\n\t\tif Clk'event and Clk = '1' then");`
229			`if (!selectIter)`
230			`{`
231			`fprintf(outFile.Handle(), "\n\t\t\tA_r <= A(A'left downto 9);");`
232			`}`
233			`else`
234			`{`
235			`fprintf(outFile.Handle(), "\n\t\t\tA_r <= A;");`
236			`}`
237			`fprintf(outFile.Handle(), "\n\t\tend if;");`
238			`fprintf(outFile.Handle(), "\n\tend process;");`
239			`}`
240
241			`if (selectIter == 1)`
242			`{`
243			`fprintf(outFile.Handle(), "\n\tU_ROM: RAMB4_S8\n\t\tport map (Zero, Zero, Clk, A(0), A(1), A(2), A(3), D(0));");`
244			`}`
245			`if (selectIter > 1)`
246			`{`
247			`fprintf(outFile.Handle(), "\n\n\tsiA <= to_integer(A(A'left downto 4));");`
248			`fprintf(outFile.Handle(), "\n\tsiA_r <= TO_INTEGER(A_r(A'left downto 4));");`
249			`fprintf(outFile.Handle(), "\n\n\tprocess (siA)\n\t\tvariable S:UNSIGNED(%d downto 0);", selectIter - 1);`
250			`fprintf(outFile.Handle(), "\n\tbegin\n\t\tS := TO_UNSIGNED(1,%d);", selectIter);`
251			`fprintf(outFile.Handle(), "\n\t\tfor I in 0 to %d loop", selectIter - 1);`
252			`fprintf(outFile.Handle(), "\n\t\t\tif I < iA then\n\t\t\t\tS := SHL(S,\"1\");\n\t\t\tend if;\n\t\tend loop;");`
253			`fprintf(outFile.Handle(), "\n\t\tbEN <= to_unsigned(S,%d);\n\tend process;", selectIter);`
254			`fprintf(outFile.Handle(), "\n\n\tsG1_1: for I in 0 to %d generate", selectIter - 1);`
255			`fprintf(outFile.Handle(), "\n\t\tU_ROM: RAMB4_S8\n\t\t\tport map (DI, sEN(I), Zero, Zero, Clk, A(3 downto 0), bRAMOut(I));");`
256			`if (z)`
257			`{`
258			`fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(I) when iA2=I else (others=>'Z');");`
259			`}`
260			`fprintf(outFile.Handle(), "\n\tend generate;");`
261			`if (!z)`
262			`{`
263			`fprintf(outFile.Handle(), "\n\n\tprocess (biA_r,RAMOut)\n\tbegin");`
264			`fprintf(outFile.Handle(), "\n\t\tD <= sRAMOut(0);");`
265			`fprintf(outFile.Handle(), "\n\t\tfor I in 1 to %d loop", selectIter - 1);`
266			`fprintf(outFile.Handle(), "\n\t\t\tif siA_r=I then\n\t\t\t\tD <= sRAMOut(I);\n\t\t\tend if;");`
267			`fprintf(outFile.Handle(), "\n\t\tend loop;\n\tend process;");`
268			`}`
269			`}`
270			`if (blockIter == 1)`
271			`{`
272			`fprintf(outFile.Handle(), "\n\tU_ROM: RAMB4_S8\n\t\tport map (DI, One, Zero, Zero, Clk, A, D);");`
273			`}`
274			`if (blockIter > 1)`
275			`{`
276			`fprintf(outFile.Handle(), "\n\n\tbiA <= to_integer(A(A'left downto 9));");`
277			`fprintf(outFile.Handle(), "\n\tbiA_r <= TO_INTEGER(A_r(A'left downto 9));");`
278			`fprintf(outFile.Handle(), "\n\n\tprocess (biA)\n\t\tvariable S:UNSIGNED(%d downto 0);", blockIter - 1);`
279			`fprintf(outFile.Handle(), "\n\tbegin\n\t\tS := TO_UNSIGNED(1,%d);", blockIter);`
280			`fprintf(outFile.Handle(), "\n\t\tfor I in 0 to %d loop", blockIter - 1);`
281			`fprintf(outFile.Handle(), "\n\t\t\tif I < iA then\n\t\t\t\tS := SHL(S,\"1\");\n\t\t\tend if;\n\t\tend loop;");`
282			`fprintf(outFile.Handle(), "\n\t\tbEN <= to_unsigned(S,%d);\n\tend process;", blockIter);`
283			`fprintf(outFile.Handle(), "\n\n\tbG1_1: for I in 0 to %d generate", blockIter - 1);`
284			`fprintf(outFile.Handle(), "\n\t\tU_ROM: RAMB4_S8\n\t\t\tport map (DI, bEN(I), Zero, Zero, Clk, A(8 downto 0), bRAMOut(I));");`
285			`if (z)`
286			`{`
287			`fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(I) when iA2=I else (others=>'Z');");`
288			`}`
289			`fprintf(outFile.Handle(), "\n\tend generate;");`
290			`if (!z)`
291			`{`
292			`fprintf(outFile.Handle(), "\n\n\tprocess (biA_r,RAMOut)\n\tbegin");`
293			`fprintf(outFile.Handle(), "\n\t\tD <= bRAMOut(0);");`
294			`fprintf(outFile.Handle(), "\n\t\tfor I in 1 to %d loop", blockIter - 1);`
295			`fprintf(outFile.Handle(), "\n\t\t\tif biA_r=I then\n\t\t\t\tD <= bRAMOut(I);\n\t\t\tend if;");`
296			`fprintf(outFile.Handle(), "\n\t\tend loop;\n\tend process;");`
297			`}`
298			`}`
299
300			`fprintf(outFile.Handle(), "\nend;\n");`
301
302			`return 0;`
303			`}`
304			`catch (string error)`
305			`{`
306			`cerr << "Fatal: " << error;`
307			`}`
308			`catch (const char *error)`
309			`{`
310			`cerr << "Fatal: " << error;`
311			`}`
312			`return -1;`
313			`}`