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[/] [t80/] [trunk/] [sw/] [xrom.cpp] - Blame information for rev 4

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//
// Xilinx VHDL ROM generator
//
// Version : 0220
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//      http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//      Not all address/data widths produce working code
//      Requires stl to compile
//
// File history :
//
// 0220 : Initial release
//
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
        // VC fix
        #define max __max
#endif
 
int main (int argc, char *argv[])
{
        cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0220\n";
 
        try
        {
                unsigned long aWidth;
                unsigned long dWidth;
                unsigned long select = 0;
                char z = 0;
 
                if (argc < 4)
                {
                        cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
                        cerr << "\nThe options can be:\n";
                        cerr << "  -[deciamal number] = SelectRAM usage in 1/16 parts\n";
                        cerr << "  -z = use tri-state buses\n";
                        cerr << "\nExample:\n";
                        cerr << "  xrom Test_ROM 13 8 -6\n\n";
                        return -1;
                }
 
                int result;
 
                result = sscanf(argv[2], "%lu", &aWidth);
                if (result < 1)
                {
                        throw "Error in address bits argument!\n";
                }
 
                result = sscanf(argv[3], "%lu", &dWidth);
                if (result < 1)
                {
                        throw "Error in data bits argument!\n";
                }
 
                if (argc > 4)
                {
                        result = sscanf(argv[4], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[4], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                if (argc > 5)
                {
                        result = sscanf(argv[5], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[5], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                unsigned long selectIter = 0;
                unsigned long blockIter = 0;
                unsigned long bytes = (dWidth + 7) / 8;
 
                if (!select)
                {
                        blockIter = ((1UL << aWidth) + 511) / 512;
                }
                else if (select == 16)
                {
                        selectIter = ((1UL << aWidth) + 15) / 16;
                }
                else
                {
                        blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
                        selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
                }
 
                unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
 
                printf("-- This file was generated with xrom written by Daniel Wallner\n");
                printf("\nlibrary IEEE;");
                printf("\nuse IEEE.std_logic_1164.all;");
                printf("\nuse IEEE.numeric_std.all;");
                printf("\nlibrary UNISIM;");
                printf("\nuse UNISIM.vcomponents.all;");
                printf("\n\nentity %s is", argv[1]);
                printf("\n\tport(");
                printf("\n\t\tClk\t: in std_logic;");
                printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
                printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
                printf("\n\t);");
                printf("\nend %s;", argv[1]);
                printf("\n\narchitecture rtl of %s is", argv[1]);
 
                if (selectIter > 0)
                {
                        printf("\n\tsignal A_r: unsigned(A'range);");
                }
                if (selectIter > 1)
                {
                        printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);
                        printf("\n\tsignal sRAMOut : sRAMOut_a;");
                        printf("\n\tsignal siA_r : integer;");
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal sD : std_logic_vector(D'range);");
                }
                if (blockIter > 1)
                {
                        printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(D'range);", blockTotal - blockIter, blockTotal - 1);
                        printf("\n\tsignal bRAMOut : bRAMOut_a;");
                        printf("\n\tsignal biA_r : integer;");
                        if (!selectIter)
                        {
                                printf("\n\tsignal A_r : unsigned(A'left downto 9);");
                        }
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal bD : std_logic_vector(D'range);");
                }
 
                printf("\nbegin");
 
                if (selectIter > 0 || blockIter > 1)
                {
                        printf("\n\tprocess (Clk)");
                        printf("\n\tbegin");
                        printf("\n\t\tif Clk'event and Clk = '1' then");
                        if (!selectIter)
                        {
                                printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");
                        }
                        else
                        {
                                printf("\n\t\t\tA_r <= unsigned(A);");
                        }
                        printf("\n\t\tend if;");
                        printf("\n\tend process;");
                }
 
                if (selectIter == 1)
                {
                        printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
                        printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);
                        if (blockIter)
                        {
                                printf("s");
                        }
                        printf("D(I), A_r(0), A_r(1), A_r(2), A_r(3));");
                        printf("\n\tend generate;");
                }
                if (selectIter > 1)
                {
                        printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
                        printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
                        printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
                        printf("\n\t\t\tS%s : LUT4\n\t\t\t\tport map (sRAMOut(I)(J), A_r(0), A_r(1), A_r(2), A_r(3));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(0);");
                                printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);
                                printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (blockIter == 1)
                {
                        printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\tB%s : RAMB4_S8\n\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), ", argv[1]);
                        if (selectIter)
                        {
                                printf("b");
                        }
                        printf("D(7 + 8 * J downto 8 * J));");
                        printf("\n\tend generate;");
                }
                if (blockIter > 1)
                {
                        printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
                        printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
                        printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(%d)(%d downto 0);", blockTotal - blockIter, dWidth - 1);
                                printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);
                                printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (selectIter && blockIter)
                {
                        printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);
                }
 
                printf("\nend;\n");
 
                return 0;
        }
        catch (string error)
        {
                cerr << "Fatal: " << error;
        }
        catch (const char *error)
        {
                cerr << "Fatal: " << error;
        }
        return -1;
}

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[/] [t80/] [trunk/] [sw/] [xrom.cpp] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	jesus	`//`
2			`// Xilinx VHDL ROM generator`
3			`//`
4			`// Version : 0220`
5			`//`
6			`// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)`
7			`//`
8			`// All rights reserved`
9			`//`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12			`//`
13			`// Redistributions of source code must retain the above copyright notice,`
14			`// this list of conditions and the following disclaimer.`
15			`//`
16			`// Redistributions in binary form must reproduce the above copyright`
17			`// notice, this list of conditions and the following disclaimer in the`
18			`// documentation and/or other materials provided with the distribution.`
19			`//`
20			`// Neither the name of the author nor the names of other contributors may`
21			`// be used to endorse or promote products derived from this software without`
22			`// specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
26			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
27			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE`
28			`// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
29			`// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF`
30			`// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS`
31			`// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN`
32			`// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
33			`// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
34			`// POSSIBILITY OF SUCH DAMAGE.`
35			`//`
36			`// Please report bugs to the author, but before you do so, please`
37			`// make sure that this is not a derivative work and that`
38			`// you have the latest version of this file.`
39			`//`
40			`// The latest version of this file can be found at:`
41			`// http://www.opencores.org/cvsweb.shtml/t51/`
42			`//`
43			`// Limitations :`
44			`// Not all address/data widths produce working code`
45			`// Requires stl to compile`
46			`//`
47			`// File history :`
48			`//`
49			`// 0220 : Initial release`
50			`//`
51
52			`#include <stdio.h>`
53			`#include <string>`
54			`#include <vector>`
55			`#include <iostream>`
56
57			`using namespace std;`
58
59			`#if !(defined(max)) && _MSC_VER`
60			`// VC fix`
61			`#define max __max`
62			`#endif`
63
64			`int main (int argc, char *argv[])`
65			`{`
66			`cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0220\n";`
67
68			`try`
69			`{`
70			`unsigned long aWidth;`
71			`unsigned long dWidth;`
72			`unsigned long select = 0;`
73			`char z = 0;`
74
75			`if (argc < 4)`
76			`{`
77			`cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";`
78			`cerr << "\nThe options can be:\n";`
79			`cerr << " -[deciamal number] = SelectRAM usage in 1/16 parts\n";`
80			`cerr << " -z = use tri-state buses\n";`
81			`cerr << "\nExample:\n";`
82			`cerr << " xrom Test_ROM 13 8 -6\n\n";`
83			`return -1;`
84			`}`
85
86			`int result;`
87
88			`result = sscanf(argv[2], "%lu", &aWidth);`
89			`if (result < 1)`
90			`{`
91			`throw "Error in address bits argument!\n";`
92			`}`
93
94			`result = sscanf(argv[3], "%lu", &dWidth);`
95			`if (result < 1)`
96			`{`
97			`throw "Error in data bits argument!\n";`
98			`}`
99
100			`if (argc > 4)`
101			`{`
102			`result = sscanf(argv[4], "%c%lu", &z, &select);`
103			`if (result < 1 \|\| z != '-')`
104			`{`
105			`throw "Error in options!\n";`
106			`}`
107			`if (result < 2)`
108			`{`
109			`sscanf(argv[4], "%c%c", &z, &z);`
110			`if (z != 'z')`
111			`{`
112			`throw "Error in options!\n";`
113			`}`
114			`}`
115			`}`
116
117			`if (argc > 5)`
118			`{`
119			`result = sscanf(argv[5], "%c%lu", &z, &select);`
120			`if (result < 1 \|\| z != '-')`
121			`{`
122			`throw "Error in options!\n";`
123			`}`
124			`if (result < 2)`
125			`{`
126			`sscanf(argv[5], "%c%c", &z, &z);`
127			`if (z != 'z')`
128			`{`
129			`throw "Error in options!\n";`
130			`}`
131			`}`
132			`}`
133
134			`unsigned long selectIter = 0;`
135			`unsigned long blockIter = 0;`
136			`unsigned long bytes = (dWidth + 7) / 8;`
137
138			`if (!select)`
139			`{`
140			`blockIter = ((1UL << aWidth) + 511) / 512;`
141			`}`
142			`else if (select == 16)`
143			`{`
144			`selectIter = ((1UL << aWidth) + 15) / 16;`
145			`}`
146			`else`
147			`{`
148			`blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;`
149			`selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;`
150			`}`
151
152			`unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;`
153
154			`printf("-- This file was generated with xrom written by Daniel Wallner\n");`
155			`printf("\nlibrary IEEE;");`
156			`printf("\nuse IEEE.std_logic_1164.all;");`
157			`printf("\nuse IEEE.numeric_std.all;");`
158			`printf("\nlibrary UNISIM;");`
159			`printf("\nuse UNISIM.vcomponents.all;");`
160			`printf("\n\nentity %s is", argv[1]);`
161			`printf("\n\tport(");`
162			`printf("\n\t\tClk\t: in std_logic;");`
163			`printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);`
164			`printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);`
165			`printf("\n\t);");`
166			`printf("\nend %s;", argv[1]);`
167			`printf("\n\narchitecture rtl of %s is", argv[1]);`
168
169			`if (selectIter > 0)`
170			`{`
171			`printf("\n\tsignal A_r: unsigned(A'range);");`
172			`}`
173			`if (selectIter > 1)`
174			`{`
175			`printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);`
176			`printf("\n\tsignal sRAMOut : sRAMOut_a;");`
177			`printf("\n\tsignal siA_r : integer;");`
178			`}`
179			`if (selectIter && blockIter)`
180			`{`
181			`printf("\n\tsignal sD : std_logic_vector(D'range);");`
182			`}`
183			`if (blockIter > 1)`
184			`{`
185			`printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(D'range);", blockTotal - blockIter, blockTotal - 1);`
186			`printf("\n\tsignal bRAMOut : bRAMOut_a;");`
187			`printf("\n\tsignal biA_r : integer;");`
188			`if (!selectIter)`
189			`{`
190			`printf("\n\tsignal A_r : unsigned(A'left downto 9);");`
191			`}`
192			`}`
193			`if (selectIter && blockIter)`
194			`{`
195			`printf("\n\tsignal bD : std_logic_vector(D'range);");`
196			`}`
197
198			`printf("\nbegin");`
199
200			`if (selectIter > 0 \|\| blockIter > 1)`
201			`{`
202			`printf("\n\tprocess (Clk)");`
203			`printf("\n\tbegin");`
204			`printf("\n\t\tif Clk'event and Clk = '1' then");`
205			`if (!selectIter)`
206			`{`
207			`printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");`
208			`}`
209			`else`
210			`{`
211			`printf("\n\t\t\tA_r <= unsigned(A);");`
212			`}`
213			`printf("\n\t\tend if;");`
214			`printf("\n\tend process;");`
215			`}`
216
217			`if (selectIter == 1)`
218			`{`
219			`printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);`
220			`printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);`
221			`if (blockIter)`
222			`{`
223			`printf("s");`
224			`}`
225			`printf("D(I), A_r(0), A_r(1), A_r(2), A_r(3));");`
226			`printf("\n\tend generate;");`
227			`}`
228			`if (selectIter > 1)`
229			`{`
230			`printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");`
231			`printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);`
232			`printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);`
233			`printf("\n\t\t\tS%s : LUT4\n\t\t\t\tport map (sRAMOut(I)(J), A_r(0), A_r(1), A_r(2), A_r(3));", argv[1]);`
234			`printf("\n\t\tend generate;");`
235			`if (z == 'z')`
236			`{`
237			`printf("\n\t\t");`
238			`if (blockIter)`
239			`{`
240			`printf("s");`
241			`}`
242			`printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");`
243			`}`
244			`printf("\n\tend generate;");`
245			`if (z != 'z')`
246			`{`
247			`printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");`
248			`if (blockIter)`
249			`{`
250			`printf("s");`
251			`}`
252			`printf("D <= sRAMOut(0);");`
253			`printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);`
254			`printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");`
255			`if (blockIter)`
256			`{`
257			`printf("s");`
258			`}`
259			`printf("D <= sRAMOut(I);\n\t\t\tend if;");`
260			`printf("\n\t\tend loop;\n\tend process;");`
261			`}`
262			`}`
263
264			`if (blockIter == 1)`
265			`{`
266			`printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);`
267			`printf("\n\t\tB%s : RAMB4_S8\n\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), ", argv[1]);`
268			`if (selectIter)`
269			`{`
270			`printf("b");`
271			`}`
272			`printf("D(7 + 8 * J downto 8 * J));");`
273			`printf("\n\tend generate;");`
274			`}`
275			`if (blockIter > 1)`
276			`{`
277			`printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");`
278			`printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);`
279			`printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);`
280			`printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);`
281			`printf("\n\t\tend generate;");`
282			`if (z == 'z')`
283			`{`
284			`printf("\n\t\t");`
285			`if (selectIter)`
286			`{`
287			`printf("b");`
288			`}`
289			`printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");`
290			`}`
291			`printf("\n\tend generate;");`
292			`if (z != 'z')`
293			`{`
294			`printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");`
295			`if (selectIter)`
296			`{`
297			`printf("b");`
298			`}`
299			`printf("D <= bRAMOut(%d)(%d downto 0);", blockTotal - blockIter, dWidth - 1);`
300			`printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);`
301			`printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");`
302			`if (selectIter)`
303			`{`
304			`printf("b");`
305			`}`
306			`printf("D <= bRAMOut(I);\n\t\t\tend if;");`
307			`printf("\n\t\tend loop;\n\tend process;");`
308			`}`
309			`}`
310
311			`if (selectIter && blockIter)`
312			`{`
313			`printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);`
314			`}`
315
316			`printf("\nend;\n");`
317
318			`return 0;`
319			`}`
320			`catch (string error)`
321			`{`
322			`cerr << "Fatal: " << error;`
323			`}`
324			`catch (const char *error)`
325			`{`
326			`cerr << "Fatal: " << error;`
327			`}`
328			`return -1;`
329			`}`