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//
// Xilinx VHDL ROM generator
//
// Version : 0221
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//      http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//      Not all address/data widths produce working code
//      Requires stl to compile
//
// File history :
//
// 0220 : Initial release
//
// 0221 : Fixed block ROMs with partial bytes
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
        // VC fix
        #define max __max
#endif
 
int main (int argc, char *argv[])
{
        cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0221\n";
 
        try
        {
                unsigned long aWidth;
                unsigned long dWidth;
                unsigned long select = 0;
                char z = 0;
 
                if (argc < 4)
                {
                        cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
                        cerr << "\nThe options can be:\n";
                        cerr << "  -[deciamal number] = SelectRAM usage in 1/16 parts\n";
                        cerr << "  -z = use tri-state buses\n";
                        cerr << "\nExample:\n";
                        cerr << "  xrom Test_ROM 13 8 -6\n\n";
                        return -1;
                }
 
                int result;
 
                result = sscanf(argv[2], "%lu", &aWidth);
                if (result < 1)
                {
                        throw "Error in address bits argument!\n";
                }
 
                result = sscanf(argv[3], "%lu", &dWidth);
                if (result < 1)
                {
                        throw "Error in data bits argument!\n";
                }
 
                if (argc > 4)
                {
                        result = sscanf(argv[4], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[4], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                if (argc > 5)
                {
                        result = sscanf(argv[5], "%c%lu", &z, &select);
                        if (result < 1 || z != '-')
                        {
                                throw "Error in options!\n";
                        }
                        if (result < 2)
                        {
                                sscanf(argv[5], "%c%c", &z, &z);
                                if (z != 'z')
                                {
                                        throw "Error in options!\n";
                                }
                        }
                }
 
                unsigned long selectIter = 0;
                unsigned long blockIter = 0;
                unsigned long bytes = (dWidth + 7) / 8;
 
                if (!select)
                {
                        blockIter = ((1UL << aWidth) + 511) / 512;
                }
                else if (select == 16)
                {
                        selectIter = ((1UL << aWidth) + 15) / 16;
                }
                else
                {
                        blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
                        selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
                }
 
                unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
 
                printf("-- This file was generated with xrom written by Daniel Wallner\n");
                printf("\nlibrary IEEE;");
                printf("\nuse IEEE.std_logic_1164.all;");
                printf("\nuse IEEE.numeric_std.all;");
                printf("\nlibrary UNISIM;");
                printf("\nuse UNISIM.vcomponents.all;");
                printf("\n\nentity %s is", argv[1]);
                printf("\n\tport(");
                printf("\n\t\tClk\t: in std_logic;");
                printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
                printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
                printf("\n\t);");
                printf("\nend %s;", argv[1]);
                printf("\n\narchitecture rtl of %s is", argv[1]);
 
                if (selectIter > 0)
                {
                        printf("\n\tsignal A_r: unsigned(A'range);");
                }
                if (selectIter > 1)
                {
                        printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);
                        printf("\n\tsignal sRAMOut : sRAMOut_a;");
                        printf("\n\tsignal siA_r : integer;");
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal sD : std_logic_vector(D'range);");
                }
                if (blockIter == 1)
                {
                        printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);
                }
                if (blockIter > 1)
                {
                        printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);
                        printf("\n\tsignal bRAMOut : bRAMOut_a;");
                        printf("\n\tsignal biA_r : integer;");
                        if (!selectIter)
                        {
                                printf("\n\tsignal A_r : unsigned(A'left downto 9);");
                        }
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal bD : std_logic_vector(D'range);");
                }
 
                printf("\nbegin");
 
                if (selectIter > 0 || blockIter > 1)
                {
                        printf("\n\tprocess (Clk)");
                        printf("\n\tbegin");
                        printf("\n\t\tif Clk'event and Clk = '1' then");
                        if (!selectIter)
                        {
                                printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");
                        }
                        else
                        {
                                printf("\n\t\t\tA_r <= unsigned(A);");
                        }
                        printf("\n\t\tend if;");
                        printf("\n\tend process;");
                }
 
                if (selectIter == 1)
                {
                        printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
                        printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);
                        if (blockIter)
                        {
                                printf("s");
                        }
                        printf("D(I), A_r(0), A_r(1), A_r(2), A_r(3));");
                        printf("\n\tend generate;");
                }
                if (selectIter > 1)
                {
                        printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
                        printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
                        printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
                        printf("\n\t\t\tS%s : LUT4\n\t\t\t\tport map (sRAMOut(I)(J), A_r(0), A_r(1), A_r(2), A_r(3));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(0);");
                                printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);
                                printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (blockIter == 1)
                {
                        printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\tB%s : RAMB4_S8", argv[1]);
                        printf("\n\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
                        printf("\n\tend generate;");
                        printf("\n\n\t");
                        if (selectIter)
                        {
                                printf("b");
                        }
                        printf("D <= bRAMOut(D'range);");
                }
                if (blockIter > 1)
                {
                        printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
                        printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
                        printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);
                                printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);
                                printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (selectIter && blockIter)
                {
                        printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);
                }
 
                printf("\nend;\n");
 
                return 0;
        }
        catch (string error)
        {
                cerr << "Fatal: " << error;
        }
        catch (const char *error)
        {
                cerr << "Fatal: " << error;
        }
        return -1;
}

Line No.	Rev	Author	Line
1	4	jesus	`//`
2			`// Xilinx VHDL ROM generator`
3			`//`
4	5	jesus	`// Version : 0221`
5	4	jesus	`//`
6			`// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)`
7			`//`
8			`// All rights reserved`
9			`//`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12			`//`
13			`// Redistributions of source code must retain the above copyright notice,`
14			`// this list of conditions and the following disclaimer.`
15			`//`
16			`// Redistributions in binary form must reproduce the above copyright`
17			`// notice, this list of conditions and the following disclaimer in the`
18			`// documentation and/or other materials provided with the distribution.`
19			`//`
20			`// Neither the name of the author nor the names of other contributors may`
21			`// be used to endorse or promote products derived from this software without`
22			`// specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
26			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
27			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE`
28			`// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
29			`// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF`
30			`// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS`
31			`// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN`
32			`// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
33			`// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
34			`// POSSIBILITY OF SUCH DAMAGE.`
35			`//`
36			`// Please report bugs to the author, but before you do so, please`
37			`// make sure that this is not a derivative work and that`
38			`// you have the latest version of this file.`
39			`//`
40			`// The latest version of this file can be found at:`
41			`// http://www.opencores.org/cvsweb.shtml/t51/`
42			`//`
43			`// Limitations :`
44			`// Not all address/data widths produce working code`
45			`// Requires stl to compile`
46			`//`
47			`// File history :`
48			`//`
49			`// 0220 : Initial release`
50			`//`
51	5	jesus	`// 0221 : Fixed block ROMs with partial bytes`
52	4	jesus
53			`#include <stdio.h>`
54			`#include <string>`
55			`#include <vector>`
56			`#include <iostream>`
57
58			`using namespace std;`
59
60			`#if !(defined(max)) && _MSC_VER`
61			`// VC fix`
62			`#define max __max`
63			`#endif`
64
65			`int main (int argc, char *argv[])`
66			`{`
67	5	jesus	`cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0221\n";`
68	4	jesus
69			`try`
70			`{`
71			`unsigned long aWidth;`
72			`unsigned long dWidth;`
73			`unsigned long select = 0;`
74			`char z = 0;`
75
76			`if (argc < 4)`
77			`{`
78			`cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";`
79			`cerr << "\nThe options can be:\n";`
80			`cerr << " -[deciamal number] = SelectRAM usage in 1/16 parts\n";`
81			`cerr << " -z = use tri-state buses\n";`
82			`cerr << "\nExample:\n";`
83			`cerr << " xrom Test_ROM 13 8 -6\n\n";`
84			`return -1;`
85			`}`
86
87			`int result;`
88
89			`result = sscanf(argv[2], "%lu", &aWidth);`
90			`if (result < 1)`
91			`{`
92			`throw "Error in address bits argument!\n";`
93			`}`
94
95			`result = sscanf(argv[3], "%lu", &dWidth);`
96			`if (result < 1)`
97			`{`
98			`throw "Error in data bits argument!\n";`
99			`}`
100
101			`if (argc > 4)`
102			`{`
103			`result = sscanf(argv[4], "%c%lu", &z, &select);`
104			`if (result < 1 \|\| z != '-')`
105			`{`
106			`throw "Error in options!\n";`
107			`}`
108			`if (result < 2)`
109			`{`
110			`sscanf(argv[4], "%c%c", &z, &z);`
111			`if (z != 'z')`
112			`{`
113			`throw "Error in options!\n";`
114			`}`
115			`}`
116			`}`
117
118			`if (argc > 5)`
119			`{`
120			`result = sscanf(argv[5], "%c%lu", &z, &select);`
121			`if (result < 1 \|\| z != '-')`
122			`{`
123			`throw "Error in options!\n";`
124			`}`
125			`if (result < 2)`
126			`{`
127			`sscanf(argv[5], "%c%c", &z, &z);`
128			`if (z != 'z')`
129			`{`
130			`throw "Error in options!\n";`
131			`}`
132			`}`
133			`}`
134
135			`unsigned long selectIter = 0;`
136			`unsigned long blockIter = 0;`
137			`unsigned long bytes = (dWidth + 7) / 8;`
138
139			`if (!select)`
140			`{`
141			`blockIter = ((1UL << aWidth) + 511) / 512;`
142			`}`
143			`else if (select == 16)`
144			`{`
145			`selectIter = ((1UL << aWidth) + 15) / 16;`
146			`}`
147			`else`
148			`{`
149			`blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;`
150			`selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;`
151			`}`
152
153			`unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;`
154
155			`printf("-- This file was generated with xrom written by Daniel Wallner\n");`
156			`printf("\nlibrary IEEE;");`
157			`printf("\nuse IEEE.std_logic_1164.all;");`
158			`printf("\nuse IEEE.numeric_std.all;");`
159			`printf("\nlibrary UNISIM;");`
160			`printf("\nuse UNISIM.vcomponents.all;");`
161			`printf("\n\nentity %s is", argv[1]);`
162			`printf("\n\tport(");`
163			`printf("\n\t\tClk\t: in std_logic;");`
164			`printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);`
165			`printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);`
166			`printf("\n\t);");`
167			`printf("\nend %s;", argv[1]);`
168			`printf("\n\narchitecture rtl of %s is", argv[1]);`
169
170			`if (selectIter > 0)`
171			`{`
172			`printf("\n\tsignal A_r: unsigned(A'range);");`
173			`}`
174			`if (selectIter > 1)`
175			`{`
176			`printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);`
177			`printf("\n\tsignal sRAMOut : sRAMOut_a;");`
178			`printf("\n\tsignal siA_r : integer;");`
179			`}`
180			`if (selectIter && blockIter)`
181			`{`
182			`printf("\n\tsignal sD : std_logic_vector(D'range);");`
183			`}`
184	5	jesus	`if (blockIter == 1)`
185			`{`
186			`printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);`
187			`}`
188	4	jesus	`if (blockIter > 1)`
189			`{`
190	5	jesus	`printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);`
191	4	jesus	`printf("\n\tsignal bRAMOut : bRAMOut_a;");`
192			`printf("\n\tsignal biA_r : integer;");`
193			`if (!selectIter)`
194			`{`
195			`printf("\n\tsignal A_r : unsigned(A'left downto 9);");`
196			`}`
197			`}`
198			`if (selectIter && blockIter)`
199			`{`
200			`printf("\n\tsignal bD : std_logic_vector(D'range);");`
201			`}`
202
203			`printf("\nbegin");`
204
205			`if (selectIter > 0 \|\| blockIter > 1)`
206			`{`
207			`printf("\n\tprocess (Clk)");`
208			`printf("\n\tbegin");`
209			`printf("\n\t\tif Clk'event and Clk = '1' then");`
210			`if (!selectIter)`
211			`{`
212			`printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");`
213			`}`
214			`else`
215			`{`
216			`printf("\n\t\t\tA_r <= unsigned(A);");`
217			`}`
218			`printf("\n\t\tend if;");`
219			`printf("\n\tend process;");`
220			`}`
221
222			`if (selectIter == 1)`
223			`{`
224			`printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);`
225			`printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);`
226			`if (blockIter)`
227			`{`
228			`printf("s");`
229			`}`
230			`printf("D(I), A_r(0), A_r(1), A_r(2), A_r(3));");`
231			`printf("\n\tend generate;");`
232			`}`
233			`if (selectIter > 1)`
234			`{`
235			`printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");`
236			`printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);`
237			`printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);`
238			`printf("\n\t\t\tS%s : LUT4\n\t\t\t\tport map (sRAMOut(I)(J), A_r(0), A_r(1), A_r(2), A_r(3));", argv[1]);`
239			`printf("\n\t\tend generate;");`
240			`if (z == 'z')`
241			`{`
242			`printf("\n\t\t");`
243			`if (blockIter)`
244			`{`
245			`printf("s");`
246			`}`
247			`printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");`
248			`}`
249			`printf("\n\tend generate;");`
250			`if (z != 'z')`
251			`{`
252			`printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");`
253			`if (blockIter)`
254			`{`
255			`printf("s");`
256			`}`
257			`printf("D <= sRAMOut(0);");`
258			`printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);`
259			`printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");`
260			`if (blockIter)`
261			`{`
262			`printf("s");`
263			`}`
264			`printf("D <= sRAMOut(I);\n\t\t\tend if;");`
265			`printf("\n\t\tend loop;\n\tend process;");`
266			`}`
267			`}`
268
269			`if (blockIter == 1)`
270			`{`
271			`printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);`
272	5	jesus	`printf("\n\t\tB%s : RAMB4_S8", argv[1]);`
273			`printf("\n\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);`
274			`printf("\n\tend generate;");`
275			`printf("\n\n\t");`
276	4	jesus	`if (selectIter)`
277			`{`
278			`printf("b");`
279			`}`
280	5	jesus	`printf("D <= bRAMOut(D'range);");`
281	4	jesus	`}`
282			`if (blockIter > 1)`
283			`{`
284			`printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");`
285			`printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);`
286			`printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);`
287			`printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);`
288			`printf("\n\t\tend generate;");`
289			`if (z == 'z')`
290			`{`
291			`printf("\n\t\t");`
292			`if (selectIter)`
293			`{`
294			`printf("b");`
295			`}`
296			`printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");`
297			`}`
298			`printf("\n\tend generate;");`
299			`if (z != 'z')`
300			`{`
301			`printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");`
302			`if (selectIter)`
303			`{`
304			`printf("b");`
305			`}`
306	5	jesus	`printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);`
307	4	jesus	`printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);`
308			`printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");`
309			`if (selectIter)`
310			`{`
311			`printf("b");`
312			`}`
313	5	jesus	`printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");`
314	4	jesus	`printf("\n\t\tend loop;\n\tend process;");`
315			`}`
316			`}`
317
318			`if (selectIter && blockIter)`
319			`{`
320			`printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);`
321			`}`
322
323			`printf("\nend;\n");`
324
325			`return 0;`
326			`}`
327			`catch (string error)`
328			`{`
329			`cerr << "Fatal: " << error;`
330			`}`
331			`catch (const char *error)`
332			`{`
333			`cerr << "Fatal: " << error;`
334			`}`
335			`return -1;`
336			`}`

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