Subversion Repositories mjpeg-decoder

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component jpeg_dequant_multiplier

        port (

        a: IN std_logic_VECTOR(11 downto 0);

        b: IN std_logic_VECTOR(7 downto 0);

        o: OUT std_logic_VECTOR(19 downto 0));

end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : jpeg_dequant_multiplier

                port map (

                        a => a,

                        b => b,

                        o => o);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file jpeg_dequant_multiplier.vhd when simulating

-- the core, jpeg_dequant_multiplier. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".