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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:16:23 10/19/2014
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-- Design Name:
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-- Module Name: clk_mod - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity clk_mod is
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Port ( CLK_100MHz_IN : in STD_LOGIC;
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CLK_100Mhz_OUT : out STD_LOGIC);
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end clk_mod;
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architecture Behavioral of clk_mod is
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signal clk_1x, clk_1x_bufg : std_logic:='0';
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signal clk0_2xout_tmp, clk0_2xout_bufg : std_logic:='0';
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signal clk0_1xout_tmp, clk0_1xout_bufg : std_logic:='0';
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begin
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CLK_100Mhz_OUT <= clk0_1xout_bufg;
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U01_BUFG : BUFG
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port map (I => clk0_1xout_tmp, O => clk0_1xout_bufg);
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U0_BUFG : BUFG
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port map (I => clk0_2xout_tmp, O => clk0_2xout_bufg);
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DCM_SP_inst : DCM_SP
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generic map (
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CLKDV_DIVIDE => 4.0, -- CLKDV divide value (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
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CLKFX_DIVIDE => 2, -- Divide value on CLKFX outputs - D - (1-32)
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CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32)
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CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
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CLKIN_PERIOD => 10.0, -- Input clock period specified in nS
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CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
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CLK_FEEDBACK => "2X", -- Feedback source (NONE, 1X, 2X)
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
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DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
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DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
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DSS_MODE => "NONE", -- Unsupported - Do not change value
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DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
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FACTORY_JF => X"c080", -- Unsupported - Do not change value
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PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
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STARTUP_WAIT => FALSE -- Delay configock frequency clock output
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)
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port map (
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CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
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CLK90 => open, -- 1-bit output: 90 degree clock output
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CLKDV => open, -- 1-bit output: Divided clock output
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CLKFX => clk0_1xout_tmp, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
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CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
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LOCKED => open, -- 1-bit output: DCM_SP Lock Output
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PSDONE => open, -- 1-bit output: Phase shift done output
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STATUS => open, -- 8-bit output: DCM_SP status output
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CLKFB => clk0_2xout_bufg, -- 1-bit input: Cl DONE until DCM_SP LOCKED (TRUE/FALSE)
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CLK0 => open, -- 1-bit output: 0 degree clock output
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CLK180 => open, -- 1-bit output: 180 degree clock output
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CLK270 => open, -- 1-bit output: 270 degree clock output
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CLK2X => clk0_2xout_tmp, -- 1-bit output: 2X clock feedback input
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CLKIN => CLK_100MHz_IN, -- 1-bit input: Clock input
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DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
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PSCLK => '0', -- 1-bit input: Phase shift clock input
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PSEN => '0', -- 1-bit input: Phase shift enable
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PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
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RST => '0' -- 1-bit input: Active high reset input
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);
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end Behavioral;
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