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https://opencores.org/ocsvn/tcp_ip_core_w_dhcp/tcp_ip_core_w_dhcp/trunk
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craighaywo |
-- Hi Emacs, this is -*- mode: vhdl -*-
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----------------------------------------------------------------------------------------------------
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--
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-- Registro de desplazamiento a la izquierda, entrada paralelo, salida serie
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--
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-- Copyright (c) 2007 Javier Valcarce García, javier.valcarce@gmail.com
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-- $Id$
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--
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----------------------------------------------------------------------------------------------------
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity losr is
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generic (
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N : integer := 4);
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port (
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reset : in std_logic;
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clk : in std_logic;
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load : in std_logic;
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ce : in std_logic;
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do : out std_logic;
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di : in std_logic_vector(N-1 downto 0));
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end losr;
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architecture arch of losr is
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begin
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process(reset, clk)
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variable data : std_logic_vector(N-1 downto 0);
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begin
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if reset = '1' then
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data := (others => '0');
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elsif rising_edge(clk) then
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if load = '1' then
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data := di;
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elsif ce = '1' then
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data := data(N-2 downto 0) & "0";
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end if;
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end if;
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do <= data(N-1);
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end process;
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end arch;
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