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craighaywo |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:40:35 12/04/2014
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-- Design Name:
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-- Module Name: spi_mod - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity spi_mod is
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Port ( CLK_IN : in STD_LOGIC;
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RST_IN : in STD_LOGIC;
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WR_CONTINUOUS_IN : in STD_LOGIC;
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WE_IN : in STD_LOGIC;
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WR_ADDR_IN : in STD_LOGIC_VECTOR (7 downto 0);
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WR_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
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WR_DATA_CMPLT_OUT : out STD_LOGIC;
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RD_CONTINUOUS_IN : in STD_LOGIC;
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RD_IN : in STD_LOGIC;
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RD_WIDTH_IN : in STD_LOGIC;
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RD_ADDR_IN : in STD_LOGIC_VECTOR (7 downto 0);
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RD_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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RD_DATA_CMPLT_OUT : out STD_LOGIC;
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SLOW_CS_EN_IN : in STD_LOGIC;
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OPER_CMPLT_POST_CS_OUT : out STD_LOGIC;
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SDI_OUT : out STD_LOGIC;
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SDO_IN : in STD_LOGIC;
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SCLK_OUT : out STD_LOGIC;
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CS_OUT : out STD_LOGIC);
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end spi_mod;
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architecture Behavioral of spi_mod is
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constant C_clk_div : unsigned(7 downto 0) := X"02";
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constant C_spi_clk_polarity : std_logic := '0';
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constant C_wr_len : unsigned(3 downto 0) := X"F";
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constant C_rd_8len : unsigned(7 downto 0) := X"0F"; -- 8 bit addr, 8 bit data
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constant C_rd_16len : unsigned(7 downto 0) := X"17"; -- 8 bit addr, 16 bit data
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constant C_wr_cont_len : unsigned(3 downto 0) := X"7";
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constant C_rd_cont_len : unsigned(7 downto 0) := X"07";
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constant C_oper_cmplt_init : unsigned(7 downto 0) := X"00";
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signal clk_counter : unsigned(7 downto 0) := C_clk_div;
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signal clk_div, spi_clk, spi_clk_o : std_logic := '0';
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signal cs, cs_p, cs_pp, cs_ppp : std_logic := '1';
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signal wr_data_cmplt, rd_data_cmplt : std_logic := '0';
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signal wr_bit_counter : unsigned(3 downto 0);
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signal rd_bit_counter : unsigned(7 downto 0);
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signal we_ini, we_ini_p, rd_ini, rd_ini_p, doing_wr, doing_rd : std_logic := '0';
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signal operation_cmplt : std_logic := '0';
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signal operation_cmplt_reg : std_logic_vector(31 downto 0);
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signal wr_data_buf, wr_data_buf2 : std_logic_vector(7 downto 0);
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signal rd_addr_buf, rd_data_buf : std_logic_vector(7 downto 0) := (others => '0');
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signal doing_wr_p, doing_rd_p, load_countinous_wr : std_logic := '0';
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signal sdi_p : std_logic := '0';
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signal operation_cmplt_cntr : unsigned(7 downto 0) := C_oper_cmplt_init;
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signal oper_cmplt_post_cs : std_logic := '0';
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begin
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CS_OUT <= cs;
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SCLK_OUT <= spi_clk_o;
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SDI_OUT <= rd_addr_buf(7) when doing_rd = '1' else wr_data_buf(7);
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WR_DATA_CMPLT_OUT <= wr_data_cmplt;
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RD_DATA_CMPLT_OUT <= rd_data_cmplt;
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OPER_CMPLT_POST_CS_OUT <= oper_cmplt_post_cs;
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spi_clk_o <= spi_clk when (cs = '0' and (doing_wr = '1' or doing_rd = '1')) else C_spi_clk_polarity;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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clk_counter <= clk_counter - 1;
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if clk_counter = X"00" then
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clk_counter <= C_clk_div;
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end if;
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if clk_counter = X"00" then
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clk_div <= '1';
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else
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clk_div <= '0';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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if clk_div = '1' then
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spi_clk <= not(spi_clk);
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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we_ini_p <= we_ini;
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rd_ini_p <= rd_ini;
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if operation_cmplt = '1' then
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we_ini <= '0';
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rd_ini <= '0';
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elsif we_ini = '0' and rd_ini = '0' then
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if WE_IN = '1' then
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we_ini <= '1';
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elsif WE_IN = '0' and RD_IN = '1' then
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rd_ini <= '1';
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end if;
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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doing_wr_p <= doing_wr;
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doing_rd_p <= doing_rd;
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if we_ini = '1' and clk_div = '1' and spi_clk = '1' then -- start on next falling edge of spi clk
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doing_wr <= '1';
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elsif operation_cmplt = '1' then
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doing_wr <= '0';
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end if;
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if rd_ini = '1' and clk_div = '1' and spi_clk = '1' then -- start on next falling edge of spi clk
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doing_rd <= '1';
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elsif operation_cmplt = '1' then
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doing_rd <= '0';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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if we_ini_p = '0' and we_ini = '1' then
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wr_data_buf <= WR_ADDR_IN;
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wr_data_buf2 <= WR_DATA_IN;
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elsif load_countinous_wr = '1' then
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wr_data_buf <= WR_DATA_IN;
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elsif doing_wr = '1' and clk_div = '1' and spi_clk_o = '1' then -- shift on falling edge
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wr_data_buf(7 downto 1) <= wr_data_buf(6 downto 0);
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wr_data_buf(0) <= wr_data_buf2(7);
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wr_data_buf2(7 downto 1) <= wr_data_buf2(6 downto 0);
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wr_data_buf2(0) <= '0';
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end if;
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if doing_wr = '1' and clk_div = '1' and spi_clk_o = '1' then
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if wr_bit_counter = X"0" then
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if WR_CONTINUOUS_IN = '1' then
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wr_bit_counter <= C_wr_cont_len;
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end if;
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else
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wr_bit_counter <= wr_bit_counter - 1;
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end if;
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elsif doing_wr = '0' then
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wr_bit_counter <= C_wr_len;
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end if;
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if doing_wr = '1' and clk_div = '1' and spi_clk_o = '1' then
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if wr_bit_counter = X"0" then
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if WR_CONTINUOUS_IN = '1' then
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load_countinous_wr <= '1';
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end if;
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end if;
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else
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load_countinous_wr <= '0';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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if doing_wr = '1' and clk_div = '1' and spi_clk_o = '0' and wr_bit_counter = X"0" then -- final rising edge of spi clk
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wr_data_cmplt <= '1';
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else
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wr_data_cmplt <= '0';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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operation_cmplt_reg(0) <= operation_cmplt;
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operation_cmplt_reg(31 downto 1) <= operation_cmplt_reg(30 downto 0);
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if doing_wr = '1' and clk_div = '1' and spi_clk_o = '1' and wr_bit_counter = X"0" and WR_CONTINUOUS_IN = '0' then
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operation_cmplt <= '1';
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elsif doing_rd = '1' and clk_div = '1' and spi_clk_o = '1' and rd_bit_counter = X"00" and RD_CONTINUOUS_IN = '0' then
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operation_cmplt <= '1';
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else
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operation_cmplt <= '0';
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end if;
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if operation_cmplt = '1' or doing_wr = '1' or doing_rd = '1' then
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operation_cmplt_cntr <= C_oper_cmplt_init;
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else
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operation_cmplt_cntr <= operation_cmplt_cntr - 1;
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end if;
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if WE_IN = '1' then
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cs <= '0';
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elsif RD_IN = '1' then
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cs <= '0';
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elsif operation_cmplt_reg(3) = '1' and SLOW_CS_EN_IN = '0' then
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cs <= '1';
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elsif operation_cmplt_reg(19) = '1' and SLOW_CS_EN_IN = '1' then
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cs <= '1';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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cs_p <= cs;
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cs_pp <= cs_p;
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cs_ppp <= cs_pp;
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if cs_ppp = '0' and cs_pp = '1' then
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oper_cmplt_post_cs <= '1';
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else
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oper_cmplt_post_cs <= '0';
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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if rd_ini_p = '0' and rd_ini = '1' then
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rd_addr_buf <= RD_ADDR_IN;
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elsif doing_rd = '1' and clk_div = '1' and spi_clk_o = '1' then -- shift on falling edge
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rd_addr_buf(7 downto 1) <= rd_addr_buf(6 downto 0);
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rd_addr_buf(0) <= '0';
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end if;
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if doing_rd = '1' and clk_div = '1' and spi_clk_o = '1' then
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if rd_bit_counter = X"00" then
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if RD_CONTINUOUS_IN = '1' then
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rd_bit_counter <= C_rd_cont_len;
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end if;
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else
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rd_bit_counter <= rd_bit_counter - 1;
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end if;
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elsif doing_rd = '0' then
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if RD_WIDTH_IN = '0' then
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rd_bit_counter <= C_rd_8len;
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else
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rd_bit_counter <= C_rd_16len;
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end if;
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end if;
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if doing_rd = '1' and clk_div = '1' and spi_clk_o = '0' then
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if rd_bit_counter < C_rd_8len then
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rd_data_buf(7 downto 1) <= rd_data_buf(6 downto 0);
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rd_data_buf(0) <= SDO_IN;
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end if;
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end if;
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end if;
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end process;
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process(CLK_IN)
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begin
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if rising_edge(CLK_IN) then
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if doing_rd = '1' and clk_div = '1' and spi_clk_o = '1' and rd_bit_counter = X"00" then -- final falling edge of spi clk
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rd_data_cmplt <= '1';
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else
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rd_data_cmplt <= '0';
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end if;
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if doing_rd = '1' and clk_div = '1' and spi_clk_o = '1' and rd_bit_counter = X"00" then -- final falling edge of spi clk
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RD_DATA_OUT <= rd_data_buf;
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end if;
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end if;
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end process;
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end Behavioral;
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