1 |
2 |
craighaywo |
----------------------------------------------------------------------------------
|
2 |
|
|
-- Company:
|
3 |
|
|
-- Engineer: CW
|
4 |
|
|
--
|
5 |
|
|
-- Create Date: 21:25:31 10/06/2014
|
6 |
|
|
-- Design Name:
|
7 |
|
|
-- Module Name: hw_client - Behavioral
|
8 |
|
|
-- Project Name:
|
9 |
|
|
-- Target Devices:
|
10 |
|
|
-- Tool versions:
|
11 |
|
|
-- Description:
|
12 |
|
|
--
|
13 |
|
|
-- Dependencies:
|
14 |
|
|
--
|
15 |
|
|
-- Revision:
|
16 |
|
|
-- Revision 0.01 - File Created
|
17 |
|
|
-- Additional Comments:
|
18 |
|
|
--
|
19 |
|
|
----------------------------------------------------------------------------------
|
20 |
|
|
|
21 |
|
|
library IEEE;
|
22 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
23 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
24 |
|
|
use work.CommonPckg.all;
|
25 |
|
|
use work.SdCardPckg.all;
|
26 |
|
|
|
27 |
|
|
library UNISIM;
|
28 |
|
|
use UNISIM.VComponents.all;
|
29 |
|
|
|
30 |
|
|
entity vault is
|
31 |
|
|
Port ( CLK_IN : in STD_LOGIC;
|
32 |
|
|
|
33 |
|
|
LED_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
34 |
|
|
SSEG_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
35 |
|
|
SSEG_EN_OUT : out STD_LOGIC_VECTOR (3 downto 0);
|
36 |
|
|
SW_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
37 |
|
|
BUTTON_IN : in STD_LOGIC_VECTOR (5 downto 0);
|
38 |
|
|
|
39 |
|
|
SDI : in STD_LOGIC;
|
40 |
|
|
SDO : out STD_LOGIC;
|
41 |
|
|
SCLK : out STD_LOGIC;
|
42 |
|
|
CS : out STD_LOGIC;
|
43 |
|
|
RESET : out STD_LOGIC;
|
44 |
|
|
|
45 |
|
|
SD_MISO_IN : in STD_LOGIC;
|
46 |
|
|
SD_MOSI_OUT : out STD_LOGIC;
|
47 |
|
|
SD_CLK_OUT : out STD_LOGIC;
|
48 |
|
|
SD_CS_OUT : out STD_LOGIC;
|
49 |
|
|
|
50 |
|
|
TEST_RF_OUT : out STD_LOGIC);
|
51 |
|
|
end vault;
|
52 |
|
|
|
53 |
|
|
architecture Behavioral of vault is
|
54 |
|
|
|
55 |
|
|
COMPONENT clk_mod
|
56 |
|
|
Port ( CLK_100MHz_IN : in STD_LOGIC;
|
57 |
|
|
CLK_100Mhz_OUT : out STD_LOGIC);
|
58 |
|
|
END COMPONENT;
|
59 |
|
|
|
60 |
|
|
COMPONENT sseg
|
61 |
|
|
PORT (
|
62 |
|
|
CLK : in STD_LOGIC;
|
63 |
|
|
VAL_IN : in STD_LOGIC_VECTOR (15 downto 0);
|
64 |
|
|
SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0);
|
65 |
|
|
AN_OUT : out STD_LOGIC_VECTOR(3 downto 0));
|
66 |
|
|
END COMPONENT;
|
67 |
|
|
|
68 |
|
|
COMPONENT led_mod is
|
69 |
|
|
Port ( CLK_IN : in STD_LOGIC;
|
70 |
|
|
LED_STATE_IN : in STD_LOGIC_VECTOR (2 downto 0);
|
71 |
|
|
ERROR_CODE_IN : in STD_LOGIC_VECTOR (4 downto 0);
|
72 |
|
|
ERROR_CODE_EN_IN : in STD_LOGIC;
|
73 |
|
|
LEDS_OUT : out STD_LOGIC_VECTOR (1 downto 0);
|
74 |
|
|
CLK_1HZ_OUT : out STD_LOGIC);
|
75 |
|
|
END COMPONENT;
|
76 |
|
|
|
77 |
|
|
COMPONENT eth_mod is
|
78 |
|
|
Generic ( G_FUNCTION : string :="client" ); -- client/server (defaults to client)
|
79 |
|
|
Port ( CLK_IN : in STD_LOGIC;
|
80 |
|
|
|
81 |
|
|
-- Command interface
|
82 |
|
|
INIT_ENC28J60 : in STD_LOGIC;
|
83 |
|
|
DHCP_CONNECT : in STD_LOGIC;
|
84 |
|
|
-- TCP_CONNECT : in STD_LOGIC;
|
85 |
|
|
ERROR_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
86 |
|
|
|
87 |
|
|
-- Data Interface
|
88 |
|
|
-- ADDR_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
89 |
|
|
-- DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
90 |
|
|
|
91 |
|
|
DEBUG_IN : in STD_LOGIC_VECTOR (2 downto 0);
|
92 |
|
|
DEBUG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
|
93 |
|
|
|
94 |
|
|
-- TCP Connection Interface
|
95 |
|
|
TCP_CONNECTION_ACTIVE_OUT : out STD_LOGIC;
|
96 |
|
|
TCP_RD_DATA_AVAIL_OUT : out STD_LOGIC;
|
97 |
|
|
TCP_RD_DATA_EN_IN : in STD_LOGIC;
|
98 |
|
|
TCP_RD_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
|
99 |
|
|
TCP_WR_DATA_POSSIBLE_OUT : out STD_LOGIC;
|
100 |
|
|
TCP_WR_DATA_EN_IN : in STD_LOGIC;
|
101 |
|
|
TCP_WR_DATA_FLUSH_IN : in STD_LOGIC;
|
102 |
|
|
TCP_WR_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
|
103 |
|
|
|
104 |
|
|
CLK_1HZ_IN : in STD_LOGIC;
|
105 |
|
|
|
106 |
|
|
-- Eth SPI interface
|
107 |
|
|
SDI_OUT : out STD_LOGIC;
|
108 |
|
|
SDO_IN : in STD_LOGIC;
|
109 |
|
|
SCLK_OUT : out STD_LOGIC;
|
110 |
|
|
CS_OUT : out STD_LOGIC);
|
111 |
|
|
END COMPONENT;
|
112 |
|
|
|
113 |
|
|
COMPONENT SdCardCtrl
|
114 |
|
|
generic (
|
115 |
|
|
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
|
116 |
|
|
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
|
117 |
|
|
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
|
118 |
|
|
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
|
119 |
|
|
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
|
120 |
|
|
);
|
121 |
|
|
port (
|
122 |
|
|
-- Host-side interface signals.
|
123 |
|
|
clk_i : in std_logic; -- Master clock.
|
124 |
|
|
reset_i : in std_logic := NO; -- active-high, synchronous reset.
|
125 |
|
|
rd_i : in std_logic := NO; -- active-high read block request.
|
126 |
|
|
wr_i : in std_logic := NO; -- active-high write block request.
|
127 |
|
|
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
|
128 |
|
|
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
|
129 |
|
|
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
|
130 |
|
|
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
|
131 |
|
|
busy_o : out std_logic; -- High when controller is busy performing some operation.
|
132 |
|
|
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
|
133 |
|
|
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
|
134 |
|
|
error_o : out std_logic_vector(15 downto 0) := (others => NO);
|
135 |
|
|
-- I/O signals to the external SD card.
|
136 |
|
|
cs_bo : out std_logic := HI; -- Active-low chip-select.
|
137 |
|
|
sclk_o : out std_logic := LO; -- Serial clock to SD card.
|
138 |
|
|
mosi_o : out std_logic := HI; -- Serial data output to SD card.
|
139 |
|
|
miso_i : in std_logic := ZERO; -- Serial data input from SD card.
|
140 |
|
|
state_debug_o : out std_logic_vector(4 downto 0)
|
141 |
|
|
);
|
142 |
|
|
END COMPONENT;
|
143 |
|
|
|
144 |
|
|
Constant C_TEST_W_SD_CARD :boolean :=false;
|
145 |
|
|
Constant C_TEST_W_FPGA :boolean :=true;
|
146 |
|
|
|
147 |
|
|
subtype slv is std_logic_vector;
|
148 |
|
|
|
149 |
|
|
signal clk_100MHz, clk_1hz : std_logic;
|
150 |
|
|
|
151 |
|
|
signal char_addr, font_addr : std_logic_vector(11 downto 0);
|
152 |
|
|
signal char_data, font_data : std_logic_vector(7 downto 0);
|
153 |
|
|
signal debug_addr : std_logic_vector(11 downto 0);
|
154 |
|
|
signal debug_data : std_logic_vector(7 downto 0);
|
155 |
|
|
signal debug_i : std_logic_vector(2 downto 0);
|
156 |
|
|
signal debug_o : std_logic_vector(15 downto 0);
|
157 |
|
|
signal r, g, b : std_logic := '0';
|
158 |
|
|
signal octl : std_logic_vector(7 downto 0);
|
159 |
|
|
signal ocrx, ocry : std_logic_vector(7 downto 0) := (others => '0');
|
160 |
|
|
|
161 |
|
|
signal frame_addr : std_logic_vector(23 downto 1) := (others => '0');
|
162 |
|
|
signal frame_data : std_logic_vector(15 downto 0) := (others => '0');
|
163 |
|
|
signal frame_rd, frame_rd_cmplt : std_logic := '0';
|
164 |
|
|
|
165 |
|
|
signal sseg_data : std_logic_vector(15 downto 0) := (others => '0');
|
166 |
|
|
signal debug_we : std_logic := '0';
|
167 |
|
|
signal debug_wr_addr : unsigned(11 downto 0) := (others => '0');
|
168 |
|
|
signal debug_wr_data : std_logic_vector(7 downto 0) := (others => '0');
|
169 |
|
|
signal buttons, buttons_prev, buttons_edge : std_logic_vector(5 downto 0) := (others => '0');
|
170 |
|
|
signal debounce_count : unsigned(15 downto 0) := (others => '0');
|
171 |
|
|
|
172 |
|
|
signal data_bus, addr_bus : std_logic_vector(7 downto 0) := (others => '0');
|
173 |
|
|
signal eth_command : std_logic_vector(3 downto 0);
|
174 |
|
|
signal eth_command_err : std_logic_vector(7 downto 0);
|
175 |
|
|
signal eth_command_en, eth_command_cmplt : std_logic;
|
176 |
|
|
|
177 |
|
|
signal sdi_buf, sdo_buf, sclk_buf, sclk_buf_n, sclk_oddr, cs_buf : std_logic;
|
178 |
|
|
|
179 |
|
|
signal clk_div_counter : unsigned(7 downto 0) := (others => '0');
|
180 |
|
|
signal test_rf_counter : unsigned(15 downto 0) := (others => '0');
|
181 |
|
|
signal tcp_rd_en, tcp_rd_en_p, tcp_rd_data_avail : std_logic;
|
182 |
|
|
signal tcp_connection_active : std_logic;
|
183 |
|
|
signal tcp_wr_en, tcp_wr_possible, wr_en : std_logic := '0';
|
184 |
|
|
signal check_rd_data : std_logic;
|
185 |
|
|
signal tcp_data_rd : std_logic_vector(7 downto 0);
|
186 |
|
|
signal tcp_data_wr : unsigned(7 downto 0) := X"00";
|
187 |
|
|
signal tcp_data_rd_p, tcp_data_rd_pp : unsigned(7 downto 0);
|
188 |
|
|
signal err_count : unsigned(15 downto 0) := (others => '0');
|
189 |
|
|
signal sd_cs, sd_clk, sd_mosi, sd_miso : std_logic;
|
190 |
|
|
signal busy_o, hndshk_i, hndshk_o, wr_i : std_logic;
|
191 |
|
|
signal wr_counter : unsigned(11 downto 0) := (others => '0');
|
192 |
|
|
signal data_i : unsigned(7 downto 0) := (others => '0');
|
193 |
|
|
signal addr_i : unsigned(31 downto 0) := (others => '0');
|
194 |
|
|
signal test_rf : std_logic;
|
195 |
|
|
|
196 |
|
|
type SD_ST is ( IDLE,
|
197 |
|
|
INIT_WR,
|
198 |
|
|
WAIT_FOR_DATA_AVAIL,
|
199 |
|
|
WAIT_FOR_BYTE,
|
200 |
|
|
WR_BYTE0,
|
201 |
|
|
WR_BYTE1,
|
202 |
|
|
WR_BYTE2,
|
203 |
|
|
WR_BYTE3,
|
204 |
|
|
WAIT_FOR_NOT_BUSY);
|
205 |
|
|
|
206 |
|
|
signal sd_state, sd_next_state : SD_ST := IDLE;
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
begin
|
210 |
|
|
|
211 |
|
|
clk_mod_Inst : clk_mod
|
212 |
|
|
PORT MAP ( CLK_100MHz_IN => CLK_IN,
|
213 |
|
|
CLK_100Mhz_OUT => clk_100MHz);
|
214 |
|
|
|
215 |
|
|
--------------------------- DEBUG LOGIC ------------------------------
|
216 |
|
|
|
217 |
|
|
LED_OUT(3 downto 3) <= (others => '0');
|
218 |
|
|
LED_OUT(2) <= tcp_connection_active;
|
219 |
|
|
|
220 |
|
|
SD_CS_OUT <= sd_cs;
|
221 |
|
|
SD_CLK_OUT <= sd_clk;
|
222 |
|
|
SD_MOSI_OUT <= sd_mosi;
|
223 |
|
|
sd_miso <= SD_MISO_IN;
|
224 |
|
|
|
225 |
|
|
sseg_inst : sseg
|
226 |
|
|
PORT MAP (
|
227 |
|
|
CLK => clk_100MHz,
|
228 |
|
|
VAL_IN => sseg_data,
|
229 |
|
|
SSEG_OUT => SSEG_OUT,
|
230 |
|
|
AN_OUT => SSEG_EN_OUT);
|
231 |
|
|
|
232 |
|
|
process(clk_100MHz)
|
233 |
|
|
begin
|
234 |
|
|
if rising_edge(clk_100MHz) then
|
235 |
|
|
debounce_count <= debounce_count + 1;
|
236 |
|
|
buttons_prev <= buttons;
|
237 |
|
|
if debounce_count = X"0000" then
|
238 |
|
|
buttons <= BUTTON_IN;
|
239 |
|
|
end if;
|
240 |
|
|
for i in 0 to 5 loop
|
241 |
|
|
if buttons_prev(i) = '1' and buttons(i) = '0' then
|
242 |
|
|
buttons_edge(i) <= '1';
|
243 |
|
|
else
|
244 |
|
|
buttons_edge(i) <= '0';
|
245 |
|
|
end if;
|
246 |
|
|
end loop;
|
247 |
|
|
end if;
|
248 |
|
|
end process;
|
249 |
|
|
|
250 |
|
|
--------------------------- UI I/O ------------------------------
|
251 |
|
|
|
252 |
|
|
led_mod_inst : led_mod
|
253 |
|
|
Port Map ( CLK_IN => clk_100MHz,
|
254 |
|
|
LED_STATE_IN => "001",
|
255 |
|
|
ERROR_CODE_IN => SW_IN(4 downto 0),
|
256 |
|
|
ERROR_CODE_EN_IN => '0',
|
257 |
|
|
LEDS_OUT => LED_OUT(1 downto 0),
|
258 |
|
|
CLK_1HZ_OUT => clk_1hz);
|
259 |
|
|
|
260 |
|
|
------------------------- Ethernet I/O --------------------------------
|
261 |
|
|
|
262 |
|
|
RESET <= '1';
|
263 |
|
|
debug_i <= buttons_edge(2)&buttons_edge(1)&buttons_edge(0);
|
264 |
|
|
|
265 |
|
|
OBUF_inst_0: OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map (I => sdi_buf, O => SDO);
|
266 |
|
|
IBUF_inst_0: IBUF port map (I => SDI, O => sdo_buf);
|
267 |
|
|
OBUF_inst_1: OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map (I => sclk_oddr, O => SCLK);
|
268 |
|
|
OBUF_inst_2: OBUF generic map ( DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map (I => cs_buf, O => CS);
|
269 |
|
|
|
270 |
|
|
sclk_buf_n <= not(sclk_buf);
|
271 |
|
|
|
272 |
|
|
ODDR2_CLK: ODDR2
|
273 |
|
|
port map (
|
274 |
|
|
Q => sclk_oddr, -- 1-bit output data
|
275 |
|
|
C0 => sclk_buf, -- 1-bit clock input
|
276 |
|
|
C1 => sclk_buf_n, -- 1-bit clock input
|
277 |
|
|
CE => '1', -- 1-bit clock enable input
|
278 |
|
|
D0 => '1', -- 1-bit data input (associated with C0)
|
279 |
|
|
D1 => '0', -- 1-bit data input (associated with C1)
|
280 |
|
|
R => '0', -- 1-bit reset input
|
281 |
|
|
S => '0' -- 1-bit set input
|
282 |
|
|
);
|
283 |
|
|
|
284 |
|
|
eth_mod_inst : eth_mod
|
285 |
|
|
Generic Map ( G_FUNCTION => "client" )
|
286 |
|
|
Port Map ( CLK_IN => clk_100MHz,
|
287 |
|
|
|
288 |
|
|
-- Command interface
|
289 |
|
|
INIT_ENC28J60 => buttons_edge(3),
|
290 |
|
|
DHCP_CONNECT => buttons_edge(4),
|
291 |
|
|
-- TCP_CONNECT => buttons_edge(5),
|
292 |
|
|
ERROR_OUT => eth_command_err,
|
293 |
|
|
|
294 |
|
|
-- Data Interface
|
295 |
|
|
-- ADDR_IN => addr_bus,
|
296 |
|
|
-- DATA_OUT => data_bus,
|
297 |
|
|
|
298 |
|
|
DEBUG_IN => debug_i,
|
299 |
|
|
DEBUG_OUT => debug_o,
|
300 |
|
|
|
301 |
|
|
-- TCP Connection Interface
|
302 |
|
|
TCP_CONNECTION_ACTIVE_OUT => tcp_connection_active,
|
303 |
|
|
TCP_RD_DATA_AVAIL_OUT => tcp_rd_data_avail,
|
304 |
|
|
TCP_RD_DATA_EN_IN => tcp_rd_en,
|
305 |
|
|
TCP_RD_DATA_OUT => tcp_data_rd,
|
306 |
|
|
TCP_WR_DATA_POSSIBLE_OUT => tcp_wr_possible,
|
307 |
|
|
TCP_WR_DATA_EN_IN => tcp_wr_en,
|
308 |
|
|
TCP_WR_DATA_FLUSH_IN => buttons_edge(1),
|
309 |
|
|
TCP_WR_DATA_IN => slv(tcp_data_wr),
|
310 |
|
|
|
311 |
|
|
CLK_1HZ_IN => clk_1hz,
|
312 |
|
|
|
313 |
|
|
-- Eth SPI interface
|
314 |
|
|
SDI_OUT => sdi_buf,
|
315 |
|
|
SDO_IN => sdo_buf,
|
316 |
|
|
SCLK_OUT => sclk_buf,
|
317 |
|
|
CS_OUT => cs_buf);
|
318 |
|
|
|
319 |
|
|
------------------------- TCP Testing --------------------------------
|
320 |
|
|
|
321 |
|
|
-- Test with FPGA
|
322 |
|
|
FPGA_TEST: if C_TEST_W_FPGA = true generate
|
323 |
|
|
|
324 |
|
|
LED_OUT(7 downto 4) <= sseg_data(15 downto 12);
|
325 |
|
|
--sseg_data(15 downto 0) <= slv(err_count);
|
326 |
|
|
sseg_data(15 downto 0) <= slv(debug_o);
|
327 |
|
|
|
328 |
|
|
process(clk_100MHz)
|
329 |
|
|
begin
|
330 |
|
|
if rising_edge(clk_100MHz) then
|
331 |
|
|
if tcp_wr_en = '1' then
|
332 |
|
|
tcp_data_wr <= tcp_data_wr + 1;
|
333 |
|
|
end if;
|
334 |
|
|
end if;
|
335 |
|
|
end process;
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
TEST_RF_OUT <= test_rf;
|
339 |
|
|
|
340 |
|
|
process(clk_100MHz)
|
341 |
|
|
begin
|
342 |
|
|
if rising_edge(clk_100MHz) then
|
343 |
|
|
test_rf_counter <= test_rf_counter - 1;
|
344 |
|
|
if buttons(2) = '0' then
|
345 |
|
|
if test_rf_counter = X"0000" then
|
346 |
|
|
test_rf <= not(test_rf);
|
347 |
|
|
end if;
|
348 |
|
|
else
|
349 |
|
|
test_rf <= '1';
|
350 |
|
|
end if;
|
351 |
|
|
end if;
|
352 |
|
|
end process;
|
353 |
|
|
|
354 |
|
|
process(clk_100MHz)
|
355 |
|
|
begin
|
356 |
|
|
if rising_edge(clk_100MHz) then
|
357 |
|
|
if clk_div_counter = X"00" then
|
358 |
|
|
clk_div_counter <= unsigned(SW_IN);
|
359 |
|
|
else
|
360 |
|
|
clk_div_counter <= clk_div_counter - 1;
|
361 |
|
|
end if;
|
362 |
|
|
if clk_div_counter = X"00" and tcp_wr_possible = '1' and buttons(0) = '0' then
|
363 |
|
|
-- if clk_div_counter = X"00" and tcp_rd_data_avail = '1' and buttons(0) = '0' then
|
364 |
|
|
-- tcp_rd_en <= '1';
|
365 |
|
|
tcp_wr_en <= '1';
|
366 |
|
|
else
|
367 |
|
|
-- tcp_rd_en <= '0';
|
368 |
|
|
tcp_wr_en <= '0';
|
369 |
|
|
end if;
|
370 |
|
|
if tcp_rd_en = '1' then
|
371 |
|
|
tcp_data_rd_p <= unsigned(tcp_data_rd);
|
372 |
|
|
tcp_data_rd_pp <= unsigned(tcp_data_rd_p);
|
373 |
|
|
end if;
|
374 |
|
|
tcp_rd_en_p <= tcp_rd_en;
|
375 |
|
|
if tcp_rd_en_p = '1' then
|
376 |
|
|
if tcp_data_rd_p /= X"00" and tcp_data_rd_pp /= X"00" then
|
377 |
|
|
check_rd_data <= '1';
|
378 |
|
|
end if;
|
379 |
|
|
else
|
380 |
|
|
check_rd_data <= '0';
|
381 |
|
|
end if;
|
382 |
|
|
if check_rd_data = '1' then
|
383 |
|
|
if tcp_data_rd_p /= (tcp_data_rd_pp + 1) then
|
384 |
|
|
err_count <= err_count + 1;
|
385 |
|
|
end if;
|
386 |
|
|
end if;
|
387 |
|
|
end if;
|
388 |
|
|
end process;
|
389 |
|
|
|
390 |
|
|
end generate;
|
391 |
|
|
|
392 |
|
|
-- Test by logging to SD Card
|
393 |
|
|
SD_CARD_TEST: if C_TEST_W_SD_CARD = true generate
|
394 |
|
|
|
395 |
|
|
LED_OUT(7) <= '1' when sd_state = IDLE else '0';
|
396 |
|
|
LED_OUT(6) <= hndshk_i;
|
397 |
|
|
LED_OUT(5) <= busy_o;
|
398 |
|
|
LED_OUT(4) <= '0';
|
399 |
|
|
|
400 |
|
|
sseg_data(15 downto 0) <= debug_o;
|
401 |
|
|
|
402 |
|
|
wr_i <= '1' when sd_state = INIT_WR else '0';
|
403 |
|
|
tcp_rd_en <= '1' when sd_state = WAIT_FOR_BYTE else '0';
|
404 |
|
|
hndshk_i <= '1' when sd_state = WR_BYTE1 else '0';
|
405 |
|
|
|
406 |
|
|
SD_ST_DECODE: process (buttons_edge(3), tcp_rd_en)
|
407 |
|
|
begin
|
408 |
|
|
sd_next_state <= sd_state; --default is to stay in current state
|
409 |
|
|
case (sd_state) is
|
410 |
|
|
when IDLE =>
|
411 |
|
|
if buttons_edge(4) = '1' and busy_o = '0' then
|
412 |
|
|
sd_next_state <= INIT_WR;
|
413 |
|
|
end if;
|
414 |
|
|
when INIT_WR =>
|
415 |
|
|
if busy_o = '1' then
|
416 |
|
|
sd_next_state <= WAIT_FOR_DATA_AVAIL;
|
417 |
|
|
end if;
|
418 |
|
|
when WAIT_FOR_DATA_AVAIL =>
|
419 |
|
|
if tcp_rd_data_avail = '1' then
|
420 |
|
|
sd_next_state <= WAIT_FOR_BYTE;
|
421 |
|
|
end if;
|
422 |
|
|
when WAIT_FOR_BYTE =>
|
423 |
|
|
sd_next_state <= WR_BYTE0;
|
424 |
|
|
when WR_BYTE0 =>
|
425 |
|
|
if hndshk_o = '1' then
|
426 |
|
|
sd_next_state <= WR_BYTE1;
|
427 |
|
|
end if;
|
428 |
|
|
when WR_BYTE1 =>
|
429 |
|
|
if hndshk_o = '0' then
|
430 |
|
|
sd_next_state <= WR_BYTE2;
|
431 |
|
|
end if;
|
432 |
|
|
when WR_BYTE2 =>
|
433 |
|
|
sd_next_state <= WR_BYTE3;
|
434 |
|
|
when WR_BYTE3 =>
|
435 |
|
|
if wr_counter = X"200" then
|
436 |
|
|
sd_next_state <= WAIT_FOR_NOT_BUSY;
|
437 |
|
|
else
|
438 |
|
|
sd_next_state <= WAIT_FOR_DATA_AVAIL;
|
439 |
|
|
end if;
|
440 |
|
|
when WAIT_FOR_NOT_BUSY =>
|
441 |
|
|
if busy_o = '0' then
|
442 |
|
|
sd_next_state <= INIT_WR;
|
443 |
|
|
end if;
|
444 |
|
|
end case;
|
445 |
|
|
end process;
|
446 |
|
|
|
447 |
|
|
process(clk_100MHz)
|
448 |
|
|
begin
|
449 |
|
|
if rising_edge(clk_100MHz) then
|
450 |
|
|
sd_state <= sd_next_state;
|
451 |
|
|
if sd_state = INIT_WR then
|
452 |
|
|
wr_counter <= (others => '0');
|
453 |
|
|
elsif sd_state = WR_BYTE2 then
|
454 |
|
|
wr_counter <= wr_counter + 1;
|
455 |
|
|
end if;
|
456 |
|
|
if sd_state = WR_BYTE3 and sd_next_state = WAIT_FOR_NOT_BUSY then
|
457 |
|
|
addr_i <= addr_i + 1;
|
458 |
|
|
end if;
|
459 |
|
|
end if;
|
460 |
|
|
end process;
|
461 |
|
|
|
462 |
|
|
SdCardCtrl_Inst : SdCardCtrl
|
463 |
|
|
generic map (
|
464 |
|
|
FREQ_G => 100.0, -- Master clock frequency (MHz).
|
465 |
|
|
INIT_SPI_FREQ_G => 0.4, -- Slow SPI clock freq. during initialization (MHz).
|
466 |
|
|
SPI_FREQ_G => 25.0, -- Operational SPI freq. to the SD card (MHz).
|
467 |
|
|
BLOCK_SIZE_G => 512, -- Number of bytes in an SD card block or sector.
|
468 |
|
|
CARD_TYPE_G => SD_CARD_E -- Type of SD card connected to this controller.
|
469 |
|
|
)
|
470 |
|
|
port map (
|
471 |
|
|
|
472 |
|
|
-- Host-side interface signals.
|
473 |
|
|
clk_i => clk_100MHz,
|
474 |
|
|
reset_i => buttons_edge(3),
|
475 |
|
|
rd_i => '0',
|
476 |
|
|
wr_i => wr_i,
|
477 |
|
|
continue_i => '0',
|
478 |
|
|
addr_i => slv(addr_i),
|
479 |
|
|
data_i => tcp_data_rd,
|
480 |
|
|
data_o => open,
|
481 |
|
|
busy_o => busy_o,
|
482 |
|
|
hndShk_i => hndshk_i,
|
483 |
|
|
hndShk_o => hndshk_o,
|
484 |
|
|
error_o => open,
|
485 |
|
|
|
486 |
|
|
-- I/O signals to the external SD card.
|
487 |
|
|
cs_bo => sd_cs,
|
488 |
|
|
sclk_o => sd_clk,
|
489 |
|
|
mosi_o => sd_mosi,
|
490 |
|
|
miso_i => sd_miso,
|
491 |
|
|
state_debug_o => open); --leds(4 downto 0));
|
492 |
|
|
|
493 |
|
|
end generate;
|
494 |
|
|
|
495 |
|
|
end Behavioral;
|
496 |
|
|
|