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[/] [tcp_socket/] [trunk/] [source/] [serial_out.vhd] - Blame information for rev 3

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--------------------------------------------------------------------------------
---
---  SERIAL OUTPUT
---
---  :Author: Jonathan P Dawson
---  :Date: 17/10/2013
---  :email: chips@jondawson.org.uk
---  :license: MIT
---  :Copyright: Copyright (C) Jonathan P Dawson 2013
---
---  A Serial Output Component
---
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity serial_output is
 
  generic(
    CLOCK_FREQUENCY : integer;
    BAUD_RATE       : integer
  );
  port(
    CLK     : in std_logic;
    RST     : in  std_logic;
    TX      : out std_logic := '1';
 
    IN1     : in std_logic_vector(7 downto 0);
    IN1_STB : in std_logic;
    IN1_ACK : out std_logic := '1'
  );
 
end entity serial_output;
 
architecture RTL of serial_output is
 
  constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
  signal BAUD_COUNT      : Unsigned(11 downto 0) := (others => '0');
  signal DATA            : std_logic_vector(7 downto 0) := (others => '0');
  signal X16CLK_EN       : std_logic := '0';
  signal S_IN1_ACK       : std_logic := '0';
 
  type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
  signal STATE : STATE_TYPE := IDLE;
 
begin
 
  process
  begin
    wait until rising_edge(CLK);
    if BAUD_COUNT = CLOCK_DIVIDER - 1 then
      BAUD_COUNT <= (others => '0');
      X16CLK_EN  <= '1';
    else
      BAUD_COUNT <= BAUD_COUNT + 1;
      X16CLK_EN  <= '0';
    end if;
    if RST = '1' then
      BAUD_COUNT <= (others => '0');
      X16CLK_EN  <= '0';
    end if;
  end process;
 
  process
  begin
    wait until rising_edge(CLK);
    case STATE is
      when IDLE =>
        TX <= '1';
        S_IN1_ACK <= '1';
        if S_IN1_ACK = '1' and IN1_STB = '1' then
          S_IN1_ACK <= '0';
          DATA  <= IN1;
          STATE <= WAIT_EN;
        end if;
      when WAIT_EN =>
        if X16CLK_EN = '1' then
          STATE <= START;
        end if;
      when START =>
        if X16CLK_EN = '1' then
          STATE <= TX0;
        end if;
        TX <= '0';
      when TX0 =>
        if X16CLK_EN = '1' then
          STATE <= TX1;
        end if;
        TX <= DATA(0);
      when TX1 =>
        if X16CLK_EN = '1' then
          STATE <= TX2;
        end if;
        TX <= DATA(1);
      when TX2 =>
        if X16CLK_EN = '1' then
          STATE <= TX3;
        end if;
        TX <= DATA(2);
      when TX3 =>
        if X16CLK_EN = '1' then
          STATE <= TX4;
        end if;
        TX <= DATA(3);
      when TX4 =>
        if X16CLK_EN = '1' then
          STATE <= TX5;
        end if;
        TX <= DATA(4);
      when TX5 =>
        if X16CLK_EN = '1' then
          STATE <= TX6;
        end if;
        TX <= DATA(5);
      when TX6 =>
        if X16CLK_EN = '1' then
          STATE <= TX7;
        end if;
        TX <= DATA(6);
      when TX7 =>
        if X16CLK_EN = '1' then
          STATE <= STOP;
        end if;
        TX <= DATA(7);
      when STOP =>
        if X16CLK_EN = '1' then
          STATE <= IDLE;
        end if;
        TX <= '1';
      when others =>
        STATE <= IDLE;
    end case;
    if RST = '1' then
      STATE <= IDLE;
      TX <= '1';
      S_IN1_ACK <= '0';
    end if;
  end process;
 
  IN1_ACK <= S_IN1_ACK;
 
end architecture RTL;

Line No.	Rev	Author	Line
1	2	jondawson	`--------------------------------------------------------------------------------`
2			`---`
3			`--- SERIAL OUTPUT`
4			`---`
5			`--- :Author: Jonathan P Dawson`
6			`--- :Date: 17/10/2013`
7			`--- :email: chips@jondawson.org.uk`
8			`--- :license: MIT`
9			`--- :Copyright: Copyright (C) Jonathan P Dawson 2013`
10			`---`
11			`--- A Serial Output Component`
12			`---`
13			`--------------------------------------------------------------------------------`
14
15			`library ieee;`
16			`use ieee.std_logic_1164.all;`
17			`use ieee.numeric_std.all;`
18
19			`entity serial_output is`
20
21			`generic(`
22			`CLOCK_FREQUENCY : integer;`
23			`BAUD_RATE : integer`
24			`);`
25			`port(`
26			`CLK : in std_logic;`
27			`RST : in std_logic;`
28			`TX : out std_logic := '1';`
29
30			`IN1 : in std_logic_vector(7 downto 0);`
31			`IN1_STB : in std_logic;`
32			`IN1_ACK : out std_logic := '1'`
33			`);`
34
35			`end entity serial_output;`
36
37			`architecture RTL of serial_output is`
38
39			`constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);`
40			`signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');`
41			`signal DATA : std_logic_vector(7 downto 0) := (others => '0');`
42			`signal X16CLK_EN : std_logic := '0';`
43			`signal S_IN1_ACK : std_logic := '0';`
44
45			`type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);`
46			`signal STATE : STATE_TYPE := IDLE;`
47
48			`begin`
49
50			`process`
51			`begin`
52			`wait until rising_edge(CLK);`
53			`if BAUD_COUNT = CLOCK_DIVIDER - 1 then`
54			`BAUD_COUNT <= (others => '0');`
55			`X16CLK_EN <= '1';`
56			`else`
57			`BAUD_COUNT <= BAUD_COUNT + 1;`
58			`X16CLK_EN <= '0';`
59			`end if;`
60			`if RST = '1' then`
61			`BAUD_COUNT <= (others => '0');`
62			`X16CLK_EN <= '0';`
63			`end if;`
64			`end process;`
65
66			`process`
67			`begin`
68			`wait until rising_edge(CLK);`
69			`case STATE is`
70			`when IDLE =>`
71			`TX <= '1';`
72			`S_IN1_ACK <= '1';`
73			`if S_IN1_ACK = '1' and IN1_STB = '1' then`
74			`S_IN1_ACK <= '0';`
75			`DATA <= IN1;`
76			`STATE <= WAIT_EN;`
77			`end if;`
78			`when WAIT_EN =>`
79			`if X16CLK_EN = '1' then`
80			`STATE <= START;`
81			`end if;`
82			`when START =>`
83			`if X16CLK_EN = '1' then`
84			`STATE <= TX0;`
85			`end if;`
86			`TX <= '0';`
87			`when TX0 =>`
88			`if X16CLK_EN = '1' then`
89			`STATE <= TX1;`
90			`end if;`
91			`TX <= DATA(0);`
92			`when TX1 =>`
93			`if X16CLK_EN = '1' then`
94			`STATE <= TX2;`
95			`end if;`
96			`TX <= DATA(1);`
97			`when TX2 =>`
98			`if X16CLK_EN = '1' then`
99			`STATE <= TX3;`
100			`end if;`
101			`TX <= DATA(2);`
102			`when TX3 =>`
103			`if X16CLK_EN = '1' then`
104			`STATE <= TX4;`
105			`end if;`
106			`TX <= DATA(3);`
107			`when TX4 =>`
108			`if X16CLK_EN = '1' then`
109			`STATE <= TX5;`
110			`end if;`
111			`TX <= DATA(4);`
112			`when TX5 =>`
113			`if X16CLK_EN = '1' then`
114			`STATE <= TX6;`
115			`end if;`
116			`TX <= DATA(5);`
117			`when TX6 =>`
118			`if X16CLK_EN = '1' then`
119			`STATE <= TX7;`
120			`end if;`
121			`TX <= DATA(6);`
122			`when TX7 =>`
123			`if X16CLK_EN = '1' then`
124			`STATE <= STOP;`
125			`end if;`
126			`TX <= DATA(7);`
127			`when STOP =>`
128			`if X16CLK_EN = '1' then`
129			`STATE <= IDLE;`
130			`end if;`
131			`TX <= '1';`
132			`when others =>`
133			`STATE <= IDLE;`
134			`end case;`
135			`if RST = '1' then`
136			`STATE <= IDLE;`
137			`TX <= '1';`
138			`S_IN1_ACK <= '0';`
139			`end if;`
140			`end process;`
141
142			`IN1_ACK <= S_IN1_ACK;`
143
144			`end architecture RTL;`

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[/] [tcp_socket/] [trunk/] [source/] [serial_out.vhd] - Blame information for rev 3