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[/] [tdm/] [trunk/] [code/] [ISDN_cont/] [tb/] [ISDN_cont_tb.vhd] - Blame information for rev 6

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1 2 khatib
-------------------------------------------------------------------------------
2
-- Title      : ISDN tdm controller
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-- Project    : TDM controller
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-------------------------------------------------------------------------------
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-- File       : ISDN_cont_tb.vhd
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-- Author     : Jamil Khatib  <khatib@ieee.org>
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-- Organization:  OpenCores.org
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-- Created    : 2001/04/30
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-- Last update:2001/04/30
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-- Platform   : 
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-- Simulators  : NC-sim/linux, Modelsim XE/windows98
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-- Synthesizers: Leonardo
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-- Target      : 
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-- Dependency  : ieee.std_logic_1164, ieee.std_logic_unsigned.
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--               HDLC.hdlc_components_pkg
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-------------------------------------------------------------------------------
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-- Description:  ISDN tdm controller that extracts 2B+D channels from 3 time
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-- slots of the incoming streem
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-------------------------------------------------------------------------------
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-- Copyright (c) 2001  Jamil Khatib
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-- 
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :  2001/04/30
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-- Modifier        :  Jamil Khatib  <khatib@ieee.org>
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-- Desccription    :  Created
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-- ToOptimize      :
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-- Known Bugs      :
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-------------------------------------------------------------------------------
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1  2001/05/06 17:55:23  jamil
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-- Initial Release
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--
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------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library HDLC;
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use HDLC.hdlc_components_pkg.all;
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-------------------------------------------------------------------------------
51
 
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entity isdn_cont_tb is
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end isdn_cont_tb;
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-------------------------------------------------------------------------------
57
 
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architecture isdn_cont_tb of isdn_cont_tb is
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  component isdn_cont_ent
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    port (
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      rst_n     : in  std_logic;
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      C2        : in  std_logic;
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      DSTi      : in  std_logic;
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      DSTo      : out std_logic;
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      F0_n      : in  std_logic;
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      F0od_n    : out std_logic;
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      HDLCen1   : out std_logic;
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      HDLCen2   : out std_logic;
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      HDLCen3   : out std_logic;
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      HDLCTxen1 : out std_logic;
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      HDLCTxen2 : out std_logic;
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      HDLCTxen3 : out std_logic;
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      Dout      : out std_logic;
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      Din1      : in  std_logic;
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      Din2      : in  std_logic;
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      Din3      : in  std_logic);
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  end component;
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80
  signal rst_n     : std_logic := '0';
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  signal C2        : std_logic := '0';
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  signal DSTi      : std_logic;
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  signal DSTo      : std_logic;
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  signal F0_n      : std_logic;
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  signal F0od_n    : std_logic;
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  signal HDLCen1   : std_logic;
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  signal HDLCen2   : std_logic;
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  signal HDLCen3   : std_logic;
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  signal HDLCTxen1 : std_logic;
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  signal HDLCTxen2 : std_logic;
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  signal HDLCTxen3 : std_logic;
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  signal Dout      : std_logic;
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  signal Din1      : std_logic;
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  signal Din2      : std_logic;
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  signal Din3      : std_logic;
96
 
97
  --Rx HDLC
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  signal RxData_o      : std_logic_vector(7 downto 0);
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  signal ValidFrame    : std_logic;
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  signal FrameError_i  : std_logic;
101
  signal AbortSignal_i : std_logic;
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  signal Rx_Readbyte   : std_logic;
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  signal Rx_rdy        : std_logic;
104
 
105
  --Tx HDLC
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  signal Tx_ValidFrame   : std_logic;
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  signal Tx_AbortFrame   : std_logic;
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  signal Tx_AbortedTrans : std_logic;
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  signal Tx_WriteByte    : std_logic;
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  signal Tx_rdy          : std_logic;
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  signal TxData          : std_logic_vector(7 downto 0);
112
 
113
  type SERIAL_typ is array (0 to 511) of std_logic;  -- Serial Data array
114
 
115
  signal RxData : SERIAL_typ;           -- Rx Serial Data
116
 
117
begin  -- isdn_cont_tb
118
 
119
  C2    <= not C2 after 244 ns;
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  rst_n <= '0',
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           '1'    after 730 ns;
122
 
123
 
124
-------------------------------------------------------------------------------
125
  -- purpose: Initialization
126
  -- type   : combinational
127
  -- inputs : rst_n
128
  -- outputs: 
129
  INIT               : process (rst_n)
130
    variable counter : std_logic_vector(7 downto 0) := "00000000";  -- Internal Counter
131
  begin  -- PROCESS INIT
132
 
133
    if (rst_n = '0') then
134
 
135
      RxData(0) <= '1';
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      RxData(1) <= '1';
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      RxData(2) <= '1';
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      RxData(3) <= '1';
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      RxData(4) <= '1';
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      RxData(5) <= '1';
141
      RxData(6) <= '1';
142
      RxData(7) <= '1';
143
 
144
      RxData(8)  <= '1';
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      RxData(9)  <= '1';
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      RxData(10) <= '1';
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      RxData(11) <= '1';
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      RxData(12) <= '1';
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      RxData(13) <= '1';
150
      RxData(14) <= '1';
151
      RxData(15) <= '1';
152
 
153
      RxData(16) <= '1';
154
      RxData(17) <= '1';
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      RxData(18) <= '1';
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      RxData(19) <= '1';
157
      RxData(20) <= '1';
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      RxData(21) <= '1';
159
      RxData(22) <= '1';
160
      RxData(23) <= '1';
161
 
162
      -- Idle
163
      RxData(24) <= '0';
164
      RxData(25) <= '1';
165
      RxData(26) <= '1';
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      RxData(27) <= '1';
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      RxData(28) <= '1';
168
      RxData(29) <= '1';
169
      RxData(30) <= '1';
170
      RxData(31) <= '0';
171
      -- Opening Flag
172
 
173
      -- Data pattern
174
      for i in 0 to 5 loop
175
        RxData(32+8*i+0) <= Counter(0);
176
        RxData(32+8*i+1) <= Counter(1);
177
        RxData(32+8*i+2) <= Counter(2);
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        RxData(32+8*i+3) <= Counter(3);
179
        RxData(32+8*i+4) <= Counter(4);
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        RxData(32+8*i+5) <= Counter(5);
181
        RxData(32+8*i+6) <= Counter(6);
182
        RxData(32+8*i+7) <= Counter(7);
183
 
184
        Counter := Counter +1;
185
      end loop;  -- i
186
 
187
 
188
 
189
 
190
 
191
 
192
      -- Data pattern
193
--      FOR i IN 0 TO 31 LOOP
194
--        RxData(8*i+0) <= Counter(0);
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--        RxData(8*i+1) <= Counter(1);
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--        RxData(8*i+2) <= Counter(2);
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--        RxData(8*i+3) <= Counter(3);
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--        RxData(8*i+4) <= Counter(4);
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--        RxData(8*i+5) <= Counter(5);
200
--        RxData(8*i+6) <= Counter(6);
201
--        RxData(8*i+7) <= Counter(7);
202
 
203
--        Counter := Counter +1;
204
--      END LOOP;                       -- i
205
 
206
    end if;
207
  end process INIT;
208
-- purpose: Framing pulse genertor
209
-- type   : combinational
210
-- inputs : 
211
-- outputs: 
212
--  F0_gen : process
213
--  begin                               -- process F0_gen
214
 
215
  F0_n <= '1',
216
--    wait until rst_n = '1';
217
 
218
          '0' after 970 ns,
219
          '1' after 1464 ns,
220
          '0' after 12200 ns,
221
          '1' after 12688 ns,
222
          '0' after 25367 ns,
223
          '1' after 25864 ns;
224
 
225
--    wait until C2 = '0';
226
--    F0_n <= '0' after 15130 ns,
227
--            '1' after 15500 ns;
228
--  end process F0_gen;
229
-------------------------------------------------------------------------------
230
  -- purpose: Rx Data generator
231
  -- type   : combinational
232
  -- inputs : C2, rst_n
233
  -- outputs: 
234
  Rx_gen       : process
235
    variable i : integer := 0;
236
  begin  -- PROCESS Rx_gen
237
    DSTi                 <= '1';
238
 
239
    wait until rst_n = '1';
240
    while (true) loop
241
 
242
      wait until F0_n = '0';
243
 
244
      for counter in 0 to 31 loop
245
 
246
        DSTi <= RxData(i);              --(counter+i*8);
247
 
248
        wait until C2 = '1';
249
 
250
        i := i +1;
251
 
252
      end loop;  -- counter
253
 
254
    end loop;  -- while
255
 
256
  end process Rx_gen;
257
 
258
-------------------------------------------------------------------------------
259
  -- purpose: Tx generator for serial backend data
260
  -- type   : combinational
261
  -- inputs : 
262
  -- outputs: 
263
--  Tx_gen                 : PROCESS
264
--    VARIABLE count_index : INTEGER := 0;  --
265
 
266
--  BEGIN                               -- PROCESS Tx_gen
267
--    Din1 <= '0';
268
--    Din2 <= '0';
269
--    Din3 <= '0';
270
 
271
--    WAIT UNTIL rst_n = '1';
272
 
273
----    wait until C2 = '0';
274
--    WAIT UNTIL HDLCTxen1 = '1' AND C2 = '0';
275
 
276
--    WHILE HDLCTxen1 = '1' LOOP
277
--      Din1        <= RxData(count_index);
278
--      count_index := count_index + 1;
279
--      WAIT UNTIL C2 = '1';
280
--    END LOOP;
281
 
282
--    WHILE HDLCTxen2 = '1' LOOP
283
--      Din2        <= RxData(count_index);
284
--      count_index := count_index + 1;
285
--      WAIT UNTIL C2 = '1';
286
--    END LOOP;
287
 
288
--    WHILE HDLCTxen3 = '1' LOOP
289
--      Din3        <= RxData(count_index);
290
--      count_index := count_index + 1;
291
--      WAIT UNTIL C2 = '1';
292
--    END LOOP;
293
 
294
--  END PROCESS Tx_gen;
295
-------------------------------------------------------------------------------
296
  HDLC_read : process
297
 
298
  begin  -- PROCESS HDLC_read
299
    Rx_Readbyte <= '0';
300
 
301
    while (true) loop
302
      wait until Rx_rdy = '1';
303
      Rx_Readbyte <= '1';
304
      wait until Rx_rdy = '0';
305
      Rx_Readbyte <= '0';
306
 
307
    end loop;
308
 
309
  end process HDLC_read;
310
  DUT : isdn_cont_ent
311
    port map (
312
      rst_n     => rst_n,
313
      C2        => C2,
314
      DSTi      => DSTi,
315
      DSTo      => DSTo,
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      F0_n      => F0_n,
317
      F0od_n    => F0od_n,
318
      HDLCen1   => HDLCen1,
319
      HDLCen2   => HDLCen2,
320
      HDLCen3   => HDLCen3,
321
      HDLCTxen1 => HDLCTxen1,
322
      HDLCTxen2 => HDLCTxen2,
323
      HDLCTxen3 => HDLCTxen3,
324
      Dout      => Dout,
325
      Din1      => Din1,
326
      Din2      => Din2,
327
      Din3      => Din3);
328
 
329
 
330
  RxChannel : RxChannel_ent
331
    port map (
332
      Rxclk       => C2,
333
      rst         => rst_n,
334
      Rx          => Dout,
335
      RxData      => RxData_o,
336
      ValidFrame  => ValidFrame,
337
      FrameError  => FrameError_i,
338
      AbortSignal => AbortSignal_i,
339
      Readbyte    => Rx_Readbyte,
340
      rdy         => Rx_rdy,
341
      RxEn        => HDLCen1);
342
 
343
 
344
  TxChannel : TxChannel_ent
345
    port map (
346
      TxClk        => C2,
347
      rst_n        => rst_n,
348
      TXEN         => HDLCTxen1,
349
      Tx           => Din1,
350
      ValidFrame   => Tx_ValidFrame,
351
      AbortFrame   => Tx_AbortFrame,
352
      AbortedTrans => Tx_AbortedTrans,
353
      WriteByte    => Tx_WriteByte,
354
      rdy          => Tx_rdy,
355
      TxData       => TxData);
356
 
357
end isdn_cont_tb;
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-------------------------------------------------------------------------------

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