OpenCores
URL https://opencores.org/ocsvn/tdm/tdm/trunk

Subversion Repositories tdm

[/] [tdm/] [trunk/] [code/] [SPMEM.VHD] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 khatib 
-------------------------------------------------------------------------------
2 
-- Title      :  Single port RAM
3 
-- Project    :  Memory Cores
4 
-------------------------------------------------------------------------------
5 
-- File        : spmem.vhd
6 
-- Author      : Jamil Khatib  (khatib@ieee.org)
7 
-- Organization: OpenIPCore Project
8 
-- Created     : 1999/5/14
9 
-- Last update : 2000/12/19
10 
-- Platform    :
11 
-- Simulators  : Modelsim 5.3XE/Windows98
12 
-- Synthesizers: Leonardo/WindowsNT
13 
-- Target      :
14 
-- Dependency  : ieee.std_logic_1164,ieee.std_logic_unsigned
15 
-------------------------------------------------------------------------------
16 
-- Description:  Single Port memory
17 
-------------------------------------------------------------------------------
18 
-- Copyright (c) 2000 Jamil Khatib
19 
--
20 
-- This VHDL design file is an open design; you can redistribute it and/or
21 
-- modify it and/or implement it after contacting the author
22 
-- You can check the draft license at
23 
-- http://www.opencores.org/OIPC/license.shtml
24 
 
25 
-------------------------------------------------------------------------------
26 
-- Revisions  :
27 
-- Revision Number :   1
28 
-- Version         :   0.1
29 
-- Date            :   12 May 1999
30 
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
31 
-- Desccription    :   Created
32 
-- Known bugs      :
33 
-- To Optimze      :
34 
-------------------------------------------------------------------------------
35 
-- Revisions  :
36 
-- Revision Number :   2
37 
-- Version         :   0.2
38 
-- Date            :   19 Dec 2000
39 
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
40 
-- Desccription    :   General review
41 
--                     Two versions are now available with reset and without
42 
--                     Default output can can be defined
43 
-- Known bugs      :
44 
-- To Optimze      :
45 
-------------------------------------------------------------------------------
46 
-- Revisions  :
47 
-- Revision Number :   3
48 
-- Version         :   0.3
49 
-- Date            :   5 Jan 2001
50 
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
51 
-- Desccription    :   Registered Read Address feature is added to make use of
52 
--                     Altera's FPGAs memory bits
53 
--                     This feature was added from Richard Herveille's
54 
--                     contribution and his memory core
55 
-- Known bugs      :
56 
-- To Optimze      :
57 
-------------------------------------------------------------------------------
58 
 
59 
 
60 
 
61 
library ieee;
62 
use ieee.std_logic_1164.all;
63 
use ieee.std_logic_unsigned.all;
64 
-------------------------------------------------------------------------------
65 
-- Single port Memory core with reset
66 
-- To make use of on FPGA memory bits do not use the RESET option
67 
-- For Altera's FPGA you have to use also OPTION := 1
68 
 
69 
entity Spmem_ent is
70 
  generic ( USE_RESET   : boolean   := false;  -- use system reset
71 
            USE_CS      : boolean   := false;  -- use chip select signal
72 
            DEFAULT_OUT : std_logic := '1';  -- Default output
73 
            OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
74 
                                        -- for Altera's FPGAs
75 
                                        -- 0: non registered read address
76 
            ADD_WIDTH   : integer   := 3;
77 
            WIDTH       : integer   := 8);
78 
 
79 
  port (
80 
    cs       :     std_logic;           -- chip select
81 
    clk      : in  std_logic;           -- write clock
82 
    reset    : in  std_logic;           -- System Reset
83 
    add      : in  std_logic_vector(add_width -1 downto 0);  --  Address
84 
    Data_In  : in  std_logic_vector(WIDTH -1 downto 0);  -- input data
85 
    Data_Out : out std_logic_vector(WIDTH -1 downto 0);  -- Output Data
86 
    WR       : in  std_logic);          -- Read Write Enable
87 
end Spmem_ent;
88 
 
89 
 
90 
 
91 
-------------------------------------------------------------------------------
92 
-- This Architecture was tested on the ModelSim 5.2EE
93 
-- The test vectors for model sim is included in vectors.do file
94 
 
95 
 
96 
architecture spmem_beh of Spmem_ent is
97 
 
98 
 
99 
 
100 
  type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
101 
                                                      -- Memory Type
102 
  signal data : data_array(0 to (2** add_width-1) );  -- Local data
103 
 
104 
 
105 
        -- FLEX/APEX devices require address to be registered with inclock for read operations
106 
  -- This signal is used only when OPTION = 1
107 
        signal regA : std_logic_vector( (add_width -1) downto 0);
108 
 
109 
  procedure init_mem(signal memory_cell : inout data_array ) is
110 
  begin
111 
 
112 
    for i in 0 to (2** add_width-1) loop
113 
      memory_cell(i) <= (others => '0');
114 
    end loop;
115 
 
116 
  end init_mem;
117 
 
118 
begin  -- spmem_beh
119 
-------------------------------------------------------------------------------
120 
-- Non Registered Read Address
121 
-------------------------------------------------------------------------------
122 
  NON_REG         : if OPTION = 0 generate
123 
-------------------------------------------------------------------------------
124 
-- Clocked Process with Reset
125 
-------------------------------------------------------------------------------
126 
    Reset_ENABLED : if USE_RESET = true generate
127 
-------------------------------------------------------------------------------
128 
      CS_ENABLED  : if USE_CS = true generate
129 
        process (clk, reset)
130 
 
131 
        begin  -- PROCESS
132 
          -- activities triggered by asynchronous reset (active low)
133 
 
134 
          if reset = '0' then
135 
            data_out <= (others => DEFAULT_OUT);
136 
            init_mem ( data);
137 
 
138 
            -- activities triggered by rising edge of clock
139 
          elsif clk'event and clk = '1' then
140 
            if CS = '1' then
141 
              if WR = '0' then
142 
                data(conv_integer(add)) <= data_in;
143 
                data_out                <= (others => DEFAULT_OUT);
144 
              else
145 
                data_out                <= data(conv_integer(add));
146 
              end if;
147 
            else
148 
              data_out                  <= (others => DEFAULT_OUT);
149 
            end if;
150 
 
151 
          end if;
152 
 
153 
        end process;
154 
      end generate CS_ENABLED;
155 
-------------------------------------------------------------------------------
156 
-------------------------------------------------------------------------------
157 
      CS_DISABLED : if USE_CS = false generate
158 
        process (clk, reset)
159 
 
160 
 
161 
        begin  -- PROCESS
162 
          -- activities triggered by asynchronous reset (active low)
163 
 
164 
          if reset = '0' then
165 
            data_out <= (others => DEFAULT_OUT);
166 
            init_mem ( data);
167 
 
168 
            -- activities triggered by rising edge of clock
169 
          elsif clk'event and clk = '1' then
170 
            if WR = '0' then
171 
              data(conv_integer(add)) <= data_in;
172 
              data_out                <= (others => DEFAULT_OUT);
173 
            else
174 
              data_out                <= data(conv_integer(add));
175 
            end if;
176 
 
177 
          end if;
178 
 
179 
        end process;
180 
      end generate CS_DISABLED;
181 
 
182 
-------------------------------------------------------------------------------
183 
-------------------------------------------------------------------------------
184 
    end generate Reset_ENABLED;
185 
-------------------------------------------------------------------------------
186 
-------------------------------------------------------------------------------
187 
-------------------------------------------------------------------------------
188 
-- Clocked Process without Reset
189 
-------------------------------------------------------------------------------
190 
    Reset_DISABLED : if USE_RESET = false generate
191 
-------------------------------------------------------------------------------
192 
-------------------------------------------------------------------------------
193 
      CS_ENABLED   : if USE_CS = true generate
194 
        process (clk)
195 
        begin  -- PROCESS
196 
 
197 
          -- activities triggered by rising edge of clock
198 
          if clk'event and clk = '1' then
199 
            if cs = '1' then
200 
              if WR = '0' then
201 
                data(conv_integer(add)) <= data_in;
202 
                data_out                <= (others => DEFAULT_OUT);
203 
              else
204 
                data_out                <= data(conv_integer(add));
205 
              end if;
206 
            else
207 
              data_out                  <= (others => DEFAULT_OUT);
208 
            end if;
209 
 
210 
 
211 
          end if;
212 
 
213 
        end process;
214 
      end generate CS_ENABLED;
215 
-------------------------------------------------------------------------------
216 
-------------------------------------------------------------------------------
217 
      CS_DISABLED : if USE_CS = false generate
218 
        process (clk)
219 
        begin  -- PROCESS
220 
 
221 
          -- activities triggered by rising edge of clock
222 
          if clk'event and clk = '1' then
223 
            if WR = '0' then
224 
              data(conv_integer(add)) <= data_in;
225 
              data_out                <= (others => DEFAULT_OUT);
226 
            else
227 
              data_out                <= data(conv_integer(add));
228 
            end if;
229 
 
230 
          end if;
231 
 
232 
        end process;
233 
      end generate CS_DISABLED;
234 
-------------------------------------------------------------------------------
235 
-------------------------------------------------------------------------------
236 
    end generate Reset_DISABLED;
237 
-------------------------------------------------------------------------------
238 
-------------------------------------------------------------------------------
239 
-------------------------------------------------------------------------------
240 
  end generate NON_REG;
241 
-------------------------------------------------------------------------------
242 
-------------------------------------------------------------------------------
243 
-------------------------------------------------------------------------------
244 
-------------------------------------------------------------------------------
245 
REG: if OPTION = 1 generate
246 
-------------------------------------------------------------------------------
247 
-- Clocked Process with Reset
248 
-------------------------------------------------------------------------------
249 
    Reset_ENABLED : if USE_RESET = true generate
250 
-------------------------------------------------------------------------------
251 
      CS_ENABLED  : if USE_CS = true generate
252 
        process (clk, reset)
253 
 
254 
        begin  -- PROCESS
255 
          -- activities triggered by asynchronous reset (active low)
256 
 
257 
          if reset = '0' then
258 
            data_out <= (others => DEFAULT_OUT);
259 
            init_mem ( data);
260 
 
261 
            -- activities triggered by rising edge of clock
262 
          elsif clk'event and clk = '1' then
263 
 
264 
            regA <= add;
265 
 
266 
            if CS = '1' then
267 
              if WR = '0' then
268 
                data(conv_integer(add)) <= data_in;
269 
                data_out                <= (others => DEFAULT_OUT);
270 
              else
271 
                data_out                <= data(conv_integer(regA));
272 
              end if;
273 
            else
274 
              data_out                  <= (others => DEFAULT_OUT);
275 
            end if;
276 
 
277 
          end if;
278 
 
279 
        end process;
280 
      end generate CS_ENABLED;
281 
-------------------------------------------------------------------------------
282 
-------------------------------------------------------------------------------
283 
      CS_DISABLED : if USE_CS = false generate
284 
        process (clk, reset)
285 
 
286 
 
287 
        begin  -- PROCESS
288 
          -- activities triggered by asynchronous reset (active low)
289 
 
290 
          if reset = '0' then
291 
            data_out <= (others => DEFAULT_OUT);
292 
            init_mem ( data);
293 
 
294 
            -- activities triggered by rising edge of clock
295 
          elsif clk'event and clk = '1' then
296 
            regA <= add;
297 
 
298 
            if WR = '0' then
299 
              data(conv_integer(add)) <= data_in;
300 
              data_out                <= (others => DEFAULT_OUT);
301 
            else
302 
              data_out                <= data(conv_integer(regA));
303 
            end if;
304 
 
305 
          end if;
306 
 
307 
        end process;
308 
      end generate CS_DISABLED;
309 
 
310 
-------------------------------------------------------------------------------
311 
-------------------------------------------------------------------------------
312 
    end generate Reset_ENABLED;
313 
-------------------------------------------------------------------------------
314 
-------------------------------------------------------------------------------
315 
-------------------------------------------------------------------------------
316 
-- Clocked Process without Reset
317 
-------------------------------------------------------------------------------
318 
    Reset_DISABLED : if USE_RESET = false generate
319 
-------------------------------------------------------------------------------
320 
-------------------------------------------------------------------------------
321 
      CS_ENABLED   : if USE_CS = true generate
322 
        process (clk)
323 
        begin  -- PROCESS
324 
 
325 
          -- activities triggered by rising edge of clock
326 
          if clk'event and clk = '1' then
327 
 
328 
            regA <= add;
329 
 
330 
            if cs = '1' then
331 
              if WR = '0' then
332 
                data(conv_integer(add)) <= data_in;
333 
                data_out                <= (others => DEFAULT_OUT);
334 
              else
335 
                data_out                <= data(conv_integer(regA));
336 
              end if;
337 
            else
338 
              data_out                  <= (others => DEFAULT_OUT);
339 
            end if;
340 
 
341 
 
342 
          end if;
343 
 
344 
        end process;
345 
      end generate CS_ENABLED;
346 
-------------------------------------------------------------------------------
347 
-------------------------------------------------------------------------------
348 
      CS_DISABLED : if USE_CS = false generate
349 
        process (clk)
350 
        begin  -- PROCESS
351 
 
352 
          -- activities triggered by rising edge of clock
353 
          if clk'event and clk = '1' then
354 
 
355 
            regA <= add;
356 
 
357 
            if WR = '0' then
358 
              data(conv_integer(add)) <= data_in;
359 
              data_out                <= (others => DEFAULT_OUT);
360 
            else
361 
              data_out                <= data(conv_integer(regA));
362 
            end if;
363 
 
364 
          end if;
365 
 
366 
        end process;
367 
      end generate CS_DISABLED;
368 
-------------------------------------------------------------------------------
369 
-------------------------------------------------------------------------------
370 
    end generate Reset_DISABLED;
371 
-------------------------------------------------------------------------------
372 
-------------------------------------------------------------------------------
373 
-------------------------------------------------------------------------------
374 
 
375 
end generate REG;
376 
 
377 
end spmem_beh;
378 
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.