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[/] [tdm/] [trunk/] [code/] [libs/] [components_pkg.vhd] - Blame information for rev 6

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1 2 khatib
-------------------------------------------------------------------------------
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-- Title      : ISDN tdm controller
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-- Project    : TDM controller
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-------------------------------------------------------------------------------
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-- File       : components_pkg.vhd
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-- Author     : Jamil Khatib  <khatib@ieee.org>
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-- Organization:  OpenCores.org
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-- Created    : 2001/05/06
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-- Last update:2001/05/22
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-- Platform   : 
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-- Simulators  : NC-sim/linux, Modelsim XE/windows98
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-- Synthesizers: Leonardo
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-- Target      : 
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-- Dependency  : ieee.std_logic_1164
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-------------------------------------------------------------------------------
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-- Description:  tdm components
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-------------------------------------------------------------------------------
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-- Copyright (c) 2001  Jamil Khatib
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-- 
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :  2001/05/06
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-- Modifier        :  Jamil Khatib  <khatib@ieee.org>
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-- Desccription    :  Created
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-- ToOptimize      :
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-- Known Bugs      : 
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-------------------------------------------------------------------------------
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3  2001/05/24 22:46:33  jamil
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-- TDM components added
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--
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-- Revision 1.2  2001/05/18 09:09:02  jamil
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-- TDM components added
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--
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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PACKAGE components_pkg IS
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  COMPONENT isdn_cont_ent
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    PORT (
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      rst_n     : IN  STD_LOGIC;
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      C2        : IN  STD_LOGIC;
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      DSTi      : IN  STD_LOGIC;
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      DSTo      : OUT STD_LOGIC;
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      F0_n      : IN  STD_LOGIC;
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      F0od_n    : OUT STD_LOGIC;
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      HDLCen1   : OUT STD_LOGIC;
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      HDLCen2   : OUT STD_LOGIC;
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      HDLCen3   : OUT STD_LOGIC;
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      HDLCTxen1 : OUT STD_LOGIC;
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      HDLCTxen2 : OUT STD_LOGIC;
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      HDLCTxen3 : OUT STD_LOGIC;
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      Dout      : OUT STD_LOGIC;
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      Din1      : IN  STD_LOGIC;
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      Din2      : IN  STD_LOGIC;
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      Din3      : IN  STD_LOGIC);
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  END COMPONENT;
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  COMPONENT tdm_cont_ent
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    PORT (
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      rst_n          : IN  STD_LOGIC;
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      C2             : IN  STD_LOGIC;
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      DSTi           : IN  STD_LOGIC;
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      DSTo           : OUT STD_LOGIC;
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      F0_n           : IN  STD_LOGIC;
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      F0od_n         : OUT STD_LOGIC;
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      CLK_I          : IN  STD_LOGIC;
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      NoChannels     : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
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      DropChannels   : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
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      RxD            : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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      RxValidData    : OUT STD_LOGIC;
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      FramErr        : OUT STD_LOGIC;
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      RxRead         : IN  STD_LOGIC;
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      RxRdy          : OUT STD_LOGIC;
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      TxErr          : OUT STD_LOGIC;
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      TxD            : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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      TxValidData    : IN  STD_LOGIC;
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      TxWrite        : IN  STD_LOGIC;
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      TxRdy          : OUT STD_LOGIC;
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      EnableSerialIF : IN  STD_LOGIC;
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      Tx_en0         : OUT STD_LOGIC;
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      Tx_en1         : OUT STD_LOGIC;
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      Tx_en2         : OUT STD_LOGIC;
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      Rx_en0         : OUT STD_LOGIC;
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      Rx_en1         : OUT STD_LOGIC;
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      Rx_en2         : OUT STD_LOGIC;
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      SerDo          : OUT STD_LOGIC;
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      SerDi          : IN  STD_LOGIC);
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  END COMPONENT;
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  COMPONENT TxTDMBuff
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    PORT (
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      CLK_I       : IN  STD_LOGIC;
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      rst_n       : IN  STD_LOGIC;
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      TxD         : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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      TxValidData : OUT STD_LOGIC;
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      TxWrite     : OUT STD_LOGIC;
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      TxRdy       : IN  STD_LOGIC;
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      WrBuff      : IN  STD_LOGIC;
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      TxData      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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      DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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      NoChannels  : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
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      TxDone      : OUT STD_LOGIC;
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      TxOverflow  : OUT STD_LOGIC);
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  END COMPONENT;
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  COMPONENT RxTDMBuff
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    PORT (
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      CLK_I           : IN  STD_LOGIC;
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      rst_n           : IN  STD_LOGIC;
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      RxD             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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      RxRead          : OUT STD_LOGIC;
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      RxRdy           : IN  STD_LOGIC;
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      RxValidData     : IN  STD_LOGIC;
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      BufferDataAvail : OUT STD_LOGIC;
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      ReadBuff        : IN  STD_LOGIC;
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      RxData          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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      RxError         : OUT STD_LOGIC);
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  END COMPONENT;
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  COMPONENT tdm_cont_top_ent
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    PORT (
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      CLK_I  : IN  STD_LOGIC;
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      RST_I  : IN  STD_LOGIC;
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      ACK_O  : OUT STD_LOGIC;
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      ADR_I  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
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      CYC_I  : IN  STD_LOGIC;
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      DAT_I  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
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      DAT_O  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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      RTY_O  : OUT STD_LOGIC;
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      STB_I  : IN  STD_LOGIC;
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      WE_I   : IN  STD_LOGIC;
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      TAG0_O : OUT STD_LOGIC;
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      TAG1_O : OUT STD_LOGIC;
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      C2     : IN  STD_LOGIC;
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      DSTi   : IN  STD_LOGIC;
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      DSTo   : OUT STD_LOGIC;
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      F0_n   : IN  STD_LOGIC;
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      F0od_n : OUT STD_LOGIC);
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  END COMPONENT;
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  COMPONENT tdm_wb_if_ent
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    PORT (
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      CLK_I          : IN  STD_LOGIC;
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      RST_I          : IN  STD_LOGIC;
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      ACK_O          : OUT STD_LOGIC;
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      ADR_I          : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
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      CYC_I          : IN  STD_LOGIC;
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      DAT_I          : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
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      DAT_O          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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      RTY_O          : OUT STD_LOGIC;
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      STB_I          : IN  STD_LOGIC;
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      WE_I           : IN  STD_LOGIC;
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      TAG0_O         : OUT STD_LOGIC;
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      TAG1_O         : OUT STD_LOGIC;
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      TxDone         : IN  STD_LOGIC;
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      WrBuff         : OUT STD_LOGIC;
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      TxData         : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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      TxOverflow     : IN  STD_LOGIC;
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      TxUnderflow    : IN  STD_LOGIC;
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      RxRdy          : IN  STD_LOGIC;
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      ReadBuff       : OUT STD_LOGIC;
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      RxData         : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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      RxOverflow     : IN  STD_LOGIC;
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      RxLineOverflow : IN  STD_LOGIC;
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      HDLCen         : OUT STD_LOGIC;
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      NoChannels     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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      DropChannels   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
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  END COMPONENT;
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END components_pkg;

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