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[/] [tdm/] [trunk/] [code/] [tdm_cont/] [core/] [tdm_cont.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
-- Title      : TDM controller
-- Project    : TDM controller
-------------------------------------------------------------------------------
-- File       : tdm_cont.vhd
-- Author     : Jamil Khatib  <khatib@ieee.org>
-- Organization:  OpenCores.org
-- Created    : 2001/05/09
-- Last update:2001/05/23
-- Platform   : 
-- Simulators  : NC-sim/linux, Modelsim XE/windows98
-- Synthesizers: Leonardo
-- Target      : 
-- Dependency  : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description:  tdm controller that reads and writes E1 bit rate through
-- ST-bis interface
-------------------------------------------------------------------------------
-- Copyright (c) 2001  Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :  2001/05/09
-- Modifier        :  Jamil Khatib  <khatib@ieee.org>
-- Desccription    :  Created
-- ToOptimize      :
-- Known Bugs      : 
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.3  2001/05/24 22:48:56  jamil
-- TDM Initial release
--
-- Revision 1.2  2001/05/18 08:49:23  jamil
-- Serial interface added
--
-- Revision 1.1  2001/05/13 21:13:35  jamil
-- Initial Release
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
ENTITY tdm_cont_ent IS
 
  PORT (
    rst_n  : IN  STD_LOGIC;             -- System asynchronous reset
    C2     : IN  STD_LOGIC;             -- ST-Bus clock
    DSTi   : IN  STD_LOGIC;             -- ST-Bus input Data
    DSTo   : OUT STD_LOGIC;             -- ST-Bus output Data
    F0_n   : IN  STD_LOGIC;             -- St-Bus Framing pulse
    F0od_n : OUT STD_LOGIC;             -- ST-Bus Delayed Framing pulse
 
    CLK_I : IN STD_LOGIC;               -- System clock
 
--Backend interface
    NoChannels   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);  -- no of Time slots
    DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0);  -- No of channels to be dropped
 
    RxD         : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Parellel Rx output
    RxValidData : OUT STD_LOGIC;                     -- Valid Data
    FramErr     : OUT STD_LOGIC;                     -- Frame Error due to
                                                     -- buffer overflow
    RxRead      : IN  STD_LOGIC;                     -- Read Byte
    RxRdy       : OUT STD_LOGIC;                     -- Byte ready
    TxErr       : OUT STD_LOGIC;
                                                     -- Tx Error in transmission due to buffer underflow
    TxD         : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Parellal Tx Input
    TxValidData : IN  STD_LOGIC;                     -- Tx Valid Data
    TxWrite     : IN  STD_LOGIC;                     -- Write byte
    TxRdy       : OUT STD_LOGIC;                     -- Byte Ready
 
    -- Serial Interfaces
    EnableSerialIF : IN STD_LOGIC;      -- Enable Serial Interface
 
    Tx_en0 : OUT STD_LOGIC;             -- Tx enable channel 0
    Tx_en1 : OUT STD_LOGIC;             -- Tx enable channel 1
    Tx_en2 : OUT STD_LOGIC;             -- Tx enable channel 2
 
    Rx_en0 : OUT STD_LOGIC;             -- Rx enable channel 0
    Rx_en1 : OUT STD_LOGIC;             -- Rx enable channel 1
    Rx_en2 : OUT STD_LOGIC;             -- Rx enable channel 2
 
    SerDo : OUT STD_LOGIC;              -- serial Data out
    SerDi : IN  STD_LOGIC               -- Serial Data in
 
    );
 
 
END tdm_cont_ent;
 
ARCHITECTURE tdm_cont_rtl OF tdm_cont_ent IS
  SIGNAL Tot_count  : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- total store counter
  SIGNAL drop_count : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- total droped counter
 
  TYPE States_type IS (IDLE_st, WRITE_st, READ_st);  --States type
 
  SIGNAL state : States_type;           -- FSM state
 
  SIGNAL DSTi_reg : STD_LOGIC;          -- DSTi register  
 
  SIGNAL Tx_reg   : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Tx Data register
  SIGNAL Tx_reg_i : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Tx Data register
  SIGNAL Tx_En    : STD_LOGIC;                     -- Tx Enable
  SIGNAL Rx_En    : STD_LOGIC;                     -- Rx Enable
  SIGNAL Rx_Reg   : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Rx Data register
 
  SIGNAL RxFrame : STD_LOGIC;           -- Rx Frame Valid
  SIGNAL RxFlag  : STD_LOGIC;           -- Rx Flag
 
  SIGNAL TxFlag    : STD_LOGIC;         -- Tx Flag
  SIGNAL TxDisable : STD_LOGIC;         -- disable Tx from Backend
 
  SIGNAL GetNew : STD_LOGIC;            -- Get New byte
 
  SIGNAL EnableRegister : STD_LOGIC_VECTOR(31 DOWNTO 0);
                                        -- Enable register
  SIGNAL EnShift        : STD_LOGIC;    -- Enable shift
 
BEGIN  -- tdm_cont_rtl
-------------------------------------------------------------------------------
-- Global constants
-------------------------------------------------------------------------------
  Tot_count  <= NoChannels & "111";
  drop_count <= DropChannels & "000";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Main machine
-------------------------------------------------------------------------------
-- purpose: FSM
-- type   : sequential
-- inputs : CLK_I, rst_n
-- outputs: 
  fsm : PROCESS (CLK_I, rst_n)
 
    VARIABLE counter     : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Bit counter
    VARIABLE Drop        : STD_LOGIC;   -- Drop bit
    VARIABLE ExtendFrame : STD_LOGIC;   -- Extend Delayed Frame pulse
  BEGIN  -- process fsm
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
      state       <= IDLE_st;
      counter     := (OTHERS => '0');
      Tx_En       <= '0';
      Rx_en       <= '0';
      DSTi_reg    <= '1';
      Drop        := '0';
      DSTo        <= 'Z';
      TxDisable   <= '1';
      F0od_n      <= '1';
      RxFrame     <= '0';
      GetNew      <= '0';
      ExtendFrame := '0';
      SerDo <= '1';
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      CASE State IS
        WHEN IDLE_st =>
          DSTo <= 'Z';
          Drop := '0';
 
          Tx_En <= '0';
          Rx_en <= '0';
 
          IF F0_n = '0' THEN
 
            State     <= WRITE_st;
            counter   := (OTHERS => '0');
            TxDisable <= NOT TxValidData;
            GetNew    <= '1';
 
          END IF;
 
          RxFrame <= '0';
 
          IF ExtendFrame = '1' AND C2 = '0' THEN
            F0od_n <= '1';
          END IF;
 
          IF C2 = '1' THEN
            ExtendFrame := '1';
          END IF;
 
 
        WHEN WRITE_st =>
          ExtendFrame := '0';
          GetNew      <= '0';
          RxFrame     <= '1';
 
          F0od_n <= '1';
          Rx_en  <= '0';
 
          IF C2 = '1' THEN
 
            IF counter >= drop_count THEN
              IF TxDisable = '1' THEN
                DSTo  <= '1';
                Tx_En <= '0';
              ELSE
 
                IF (EnableSerialIF = '1') THEN
                  DSTo <= SerDi;
                ELSE
                  DSTo <= Tx_reg(7);
                END IF;
 
                Tx_En <= '1';
              END IF;
 
              Drop := '0';
 
            ELSE
              DSTo  <= 'Z';
              Tx_En <= '0';
              Drop  := '1';
            END IF;
 
            State <= READ_st;
 
          ELSE
 
            Tx_En <= '0';
 
          END IF;
 
        WHEN READ_st =>
          ExtendFrame := '0';
          GetNew      <= '0';
          RxFrame     <= '1';
          Tx_En       <= '0';
 
          IF C2 = '0' THEN
 
            DSTi_reg <= DSTi;
            SerDo    <= DSTi;
 
            IF counter = Tot_count THEN
 
              State  <= IDLE_st;
              F0od_n <= '0';
 
            ELSE
              State  <= WRITE_st;
              F0od_n <= '1';
 
            END IF;
 
            counter := counter + 1;
 
            Rx_En <= NOT Drop;
          ELSE
            Rx_En <= '0';
          END IF;
 
      END CASE;
 
    END IF;
  END PROCESS fsm;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Rx Machines
-------------------------------------------------------------------------------
  -- purpose: Rx Serial To parellel
  -- type   : sequential
  RxS2P               : PROCESS (CLK_I, rst_n)
    VARIABLE Rx_count : STD_LOGIC_VECTOR(2 DOWNTO 0);  -- Rx Internal bit counter
 
  BEGIN  -- process RxS2P
    IF rst_n = '0' THEN                     -- asynchronous reset (active low)
      Rx_count := "000";
      RxFlag   <= '0';
      Rx_Reg   <= (OTHERS => '1');
      EnShift  <= '0';
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      IF Rx_En = '1' THEN
 
        Rx_Reg <= Rx_Reg(6 DOWNTO 0) & DSTi_reg;
 
        IF Rx_count = "111" THEN
          Rx_count := "000";
 
          RxFlag <= '1';
 
          EnShift  <= '1';
        ELSE
          Rx_count := Rx_count + 1;
          RxFlag   <= '0';
          EnShift  <= '0';
        END IF;
      ELSE
        RxFlag     <= '0';
        EnShift    <= '0';
      END IF;
 
    END IF;
  END PROCESS RxS2P;
-------------------------------------------------------------------------------
  -- purpose: Rx Backend
  -- type   : sequential
  -- inputs : CLK_I, rst_n
  -- outputs: 
  RxBackend        : PROCESS (CLK_I, rst_n)
    VARIABLE state : STD_LOGIC;         -- Internal State
  BEGIN  -- process RxBackend
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
      State       := '0';
      RxD         <= (OTHERS => '0');
      RxRdy       <= '0';
      FramErr     <= '0';
      RxValidData <= '0';
 
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      CASE State IS
 
        WHEN '0' =>
          RxRdy   <= '0';
          FramErr <= '0';
 
          IF RxFlag = '1' THEN
            RxD   <= Rx_Reg;
            State := '1';
          END IF;
 
        WHEN '1' =>
          RxRdy <= '1';
 RxValidData <= RxFrame;
          IF RxFlag = '1' THEN
            State       := '0';
            FramErr     <= '1';
--            RxValidData <= RxFrame;
          ELSIF RxRead = '1' THEN
 
--            RxValidData <= RxFrame;
 
            State   := '0';
            FramErr <= '0';
          END IF;
 
        WHEN OTHERS              =>
          RxRdy       <= '0';
          State       := '0';
          FramErr     <= '1';
          RxValidData <= RxFrame;
      END CASE;
    END IF;
  END PROCESS RxBackend;
-------------------------------------------------------------------------------
-- Tx Machines
-------------------------------------------------------------------------------
  -- purpose: Tx Parellel to serial
  -- type   : sequential
  -- inputs : CLK_I, rst_n
  -- outputs: 
  TxP2S               : PROCESS (CLK_I, rst_n)
    VARIABLE Tx_Count : STD_LOGIC_VECTOR(2 DOWNTO 0);  -- Tx Bit counter
  BEGIN  -- process TxP2S
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
      Tx_Count        := "000";
      Tx_reg          <= (OTHERS => '1');
      TxFlag          <= '0';
 
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      IF TxDisable = '0' AND GetNew = '1' THEN
        Tx_reg <= Tx_reg_i;
        TxFlag <= '1';
 
      ELSE
        IF Tx_En = '1' THEN
 
          IF Tx_count = "111" THEN
            Tx_count := "000";
 
            Tx_Reg   <= Tx_Reg_i;
            TxFlag   <= '1';
          ELSE
            Tx_count := Tx_count + 1;
            TxFlag   <= '0';
            Tx_Reg   <= Tx_Reg(6 DOWNTO 0) & '1';
 
          END IF;
 
        ELSE
          TxFlag <= '0';
        END IF;
      END IF;
    END IF;
  END PROCESS TxP2S;
-------------------------------------------------------------------------------
  -- purpose: Tx Backend machine
  -- type   : sequential
  -- inputs : CLK_I, rst_n
  -- outputs: 
  TxBackend        : PROCESS (CLK_I, rst_n)
    VARIABLE state : STD_LOGIC_VECTOR(1 DOWNTO 0);  -- Internal State
  BEGIN  -- process TxBackend
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
 
      State    := "11";                 -- Wait for NewValidFrame
      TxRdy    <= '0';
      TxErr    <= '0';
      Tx_Reg_i <= (OTHERS => '1');
 
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      CASE State IS
        WHEN"11" =>
          TxRdy <= '1';
 
        IF TxValidData = '1' THEN
          State := "01";                -- Get New byte
        END IF;
 
        WHEN "00" =>
        TxRdy <= '0';
 
        IF TxFlag = '1' THEN            -- and TxDisable = '0' then
 
          State := "01";                -- Get New Byte
        END IF;
 
        WHEN "01" =>
        TxRdy <= '1';
 
        IF TxFlag = '1' OR TxValidData = '0' THEN
          State    := "11";             -- Wait for New frame
          TxErr    <= '1';
          Tx_Reg_i <= (OTHERS => '1');
        ELSIF TxWrite = '1' THEN
          State    := "00";
          TxErr    <= '0';
          Tx_Reg_i <= TxD;
        END IF;
 
        WHEN OTHERS         =>
        TxRdy    <= '0';
        State    := "11";
        TxErr    <= '1';
        Tx_Reg_i <= (OTHERS => '1');
      END CASE;
    END IF;
  END PROCESS TxBackend;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Serial Interface logic
-------------------------------------------------------------------------------
  Tx_en0         <= EnableRegister(0) AND Tx_En;
  Tx_en1         <= EnableRegister(1) AND Tx_En;
  Tx_en2         <= EnableRegister(2) AND Tx_En;
  Rx_en0         <= EnableRegister(0) AND Rx_En;
  Rx_en1         <= EnableRegister(1) AND Rx_En;
  Rx_en2         <= EnableRegister(2) AND Rx_En;
-------------------------------------------------------------------------------
  -- purpose: Serial Enable shift register
  -- type   : sequential
  -- inputs : clock, rst_n
  -- outputs: 
  SerialEnShift : PROCESS (CLK_I, rst_n)
 
  BEGIN  -- PROCESS SerialEnShift
 
    IF rst_n = '0' THEN                     -- asynchronous reset (active low)
      EnableRegister <= "00000000000000000000000000000001";
    ELSIF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      IF (EnShift = '1') THEN
        EnableRegister <= EnableRegister(30 DOWNTO 0) & EnableRegister(31);
      END IF;
    END IF;
 
  END PROCESS SerialEnShift;
END tdm_cont_rtl;

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[/] [tdm/] [trunk/] [code/] [tdm_cont/] [core/] [tdm_cont.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	khatib	`-------------------------------------------------------------------------------`
2			`-- Title : TDM controller`
3			`-- Project : TDM controller`
4			`-------------------------------------------------------------------------------`
5			`-- File : tdm_cont.vhd`
6			`-- Author : Jamil Khatib <khatib@ieee.org>`
7			`-- Organization: OpenCores.org`
8			`-- Created : 2001/05/09`
9			`-- Last update:2001/05/23`
10			`-- Platform :`
11			`-- Simulators : NC-sim/linux, Modelsim XE/windows98`
12			`-- Synthesizers: Leonardo`
13			`-- Target :`
14			`-- Dependency : ieee.std_logic_1164`
15			`-------------------------------------------------------------------------------`
16			`-- Description: tdm controller that reads and writes E1 bit rate through`
17			`-- ST-bis interface`
18			`-------------------------------------------------------------------------------`
19			`-- Copyright (c) 2001 Jamil Khatib`
20			`--`
21			`-- This VHDL design file is an open design; you can redistribute it and/or`
22			`-- modify it and/or implement it after contacting the author`
23			`-- You can check the draft license at`
24			`-- http://www.opencores.org/OIPC/license.shtml`
25			`-------------------------------------------------------------------------------`
26			`-- Revisions :`
27			`-- Revision Number : 1`
28			`-- Version : 0.1`
29			`-- Date : 2001/05/09`
30			`-- Modifier : Jamil Khatib <khatib@ieee.org>`
31			`-- Desccription : Created`
32			`-- ToOptimize :`
33			`-- Known Bugs :`
34			`-------------------------------------------------------------------------------`
35			`-- $Log: not supported by cvs2svn $`
36			`-- Revision 1.3 2001/05/24 22:48:56 jamil`
37			`-- TDM Initial release`
38			`--`
39			`-- Revision 1.2 2001/05/18 08:49:23 jamil`
40			`-- Serial interface added`
41			`--`
42			`-- Revision 1.1 2001/05/13 21:13:35 jamil`
43			`-- Initial Release`
44			`--`
45			`-------------------------------------------------------------------------------`
46			`LIBRARY ieee;`
47			`USE ieee.std_logic_1164.ALL;`
48			`USE ieee.std_logic_unsigned.ALL;`
49
50			`ENTITY tdm_cont_ent IS`
51
52			`PORT (`
53			`rst_n : IN STD_LOGIC; -- System asynchronous reset`
54			`C2 : IN STD_LOGIC; -- ST-Bus clock`
55			`DSTi : IN STD_LOGIC; -- ST-Bus input Data`
56			`DSTo : OUT STD_LOGIC; -- ST-Bus output Data`
57			`F0_n : IN STD_LOGIC; -- St-Bus Framing pulse`
58			`F0od_n : OUT STD_LOGIC; -- ST-Bus Delayed Framing pulse`
59
60			`CLK_I : IN STD_LOGIC; -- System clock`
61
62			`--Backend interface`
63			`NoChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- no of Time slots`
64			`DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- No of channels to be dropped`
65
66			`RxD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Parellel Rx output`
67			`RxValidData : OUT STD_LOGIC; -- Valid Data`
68			`FramErr : OUT STD_LOGIC; -- Frame Error due to`
69			`-- buffer overflow`
70			`RxRead : IN STD_LOGIC; -- Read Byte`
71			`RxRdy : OUT STD_LOGIC; -- Byte ready`
72			`TxErr : OUT STD_LOGIC;`
73			`-- Tx Error in transmission due to buffer underflow`
74			`TxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Parellal Tx Input`
75			`TxValidData : IN STD_LOGIC; -- Tx Valid Data`
76			`TxWrite : IN STD_LOGIC; -- Write byte`
77			`TxRdy : OUT STD_LOGIC; -- Byte Ready`
78
79			`-- Serial Interfaces`
80			`EnableSerialIF : IN STD_LOGIC; -- Enable Serial Interface`
81
82			`Tx_en0 : OUT STD_LOGIC; -- Tx enable channel 0`
83			`Tx_en1 : OUT STD_LOGIC; -- Tx enable channel 1`
84			`Tx_en2 : OUT STD_LOGIC; -- Tx enable channel 2`
85
86			`Rx_en0 : OUT STD_LOGIC; -- Rx enable channel 0`
87			`Rx_en1 : OUT STD_LOGIC; -- Rx enable channel 1`
88			`Rx_en2 : OUT STD_LOGIC; -- Rx enable channel 2`
89
90			`SerDo : OUT STD_LOGIC; -- serial Data out`
91			`SerDi : IN STD_LOGIC -- Serial Data in`
92
93			`);`
94
95
96			`END tdm_cont_ent;`
97
98			`ARCHITECTURE tdm_cont_rtl OF tdm_cont_ent IS`
99			`SIGNAL Tot_count : STD_LOGIC_VECTOR(7 DOWNTO 0); -- total store counter`
100			`SIGNAL drop_count : STD_LOGIC_VECTOR(7 DOWNTO 0); -- total droped counter`
101
102			`TYPE States_type IS (IDLE_st, WRITE_st, READ_st); --States type`
103
104			`SIGNAL state : States_type; -- FSM state`
105
106			`SIGNAL DSTi_reg : STD_LOGIC; -- DSTi register`
107
108			`SIGNAL Tx_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data register`
109			`SIGNAL Tx_reg_i : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data register`
110			`SIGNAL Tx_En : STD_LOGIC; -- Tx Enable`
111			`SIGNAL Rx_En : STD_LOGIC; -- Rx Enable`
112			`SIGNAL Rx_Reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data register`
113
114			`SIGNAL RxFrame : STD_LOGIC; -- Rx Frame Valid`
115			`SIGNAL RxFlag : STD_LOGIC; -- Rx Flag`
116
117			`SIGNAL TxFlag : STD_LOGIC; -- Tx Flag`
118			`SIGNAL TxDisable : STD_LOGIC; -- disable Tx from Backend`
119
120			`SIGNAL GetNew : STD_LOGIC; -- Get New byte`
121
122			`SIGNAL EnableRegister : STD_LOGIC_VECTOR(31 DOWNTO 0);`
123			`-- Enable register`
124			`SIGNAL EnShift : STD_LOGIC; -- Enable shift`
125
126			`BEGIN -- tdm_cont_rtl`
127			`-------------------------------------------------------------------------------`
128			`-- Global constants`
129			`-------------------------------------------------------------------------------`
130			`Tot_count <= NoChannels & "111";`
131			`drop_count <= DropChannels & "000";`
132			`-------------------------------------------------------------------------------`
133			`-------------------------------------------------------------------------------`
134			`-- Main machine`
135			`-------------------------------------------------------------------------------`
136			`-- purpose: FSM`
137			`-- type : sequential`
138			`-- inputs : CLK_I, rst_n`
139			`-- outputs:`
140			`fsm : PROCESS (CLK_I, rst_n)`
141
142			`VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Bit counter`
143			`VARIABLE Drop : STD_LOGIC; -- Drop bit`
144			`VARIABLE ExtendFrame : STD_LOGIC; -- Extend Delayed Frame pulse`
145			`BEGIN -- process fsm`
146			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
147			`state <= IDLE_st;`
148			`counter := (OTHERS => '0');`
149			`Tx_En <= '0';`
150			`Rx_en <= '0';`
151			`DSTi_reg <= '1';`
152			`Drop := '0';`
153			`DSTo <= 'Z';`
154			`TxDisable <= '1';`
155			`F0od_n <= '1';`
156			`RxFrame <= '0';`
157			`GetNew <= '0';`
158			`ExtendFrame := '0';`
159			`SerDo <= '1';`
160			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
161
162			`CASE State IS`
163			`WHEN IDLE_st =>`
164			`DSTo <= 'Z';`
165			`Drop := '0';`
166
167			`Tx_En <= '0';`
168			`Rx_en <= '0';`
169
170			`IF F0_n = '0' THEN`
171
172			`State <= WRITE_st;`
173			`counter := (OTHERS => '0');`
174			`TxDisable <= NOT TxValidData;`
175			`GetNew <= '1';`
176
177			`END IF;`
178
179			`RxFrame <= '0';`
180
181			`IF ExtendFrame = '1' AND C2 = '0' THEN`
182			`F0od_n <= '1';`
183			`END IF;`
184
185			`IF C2 = '1' THEN`
186			`ExtendFrame := '1';`
187			`END IF;`
188
189
190			`WHEN WRITE_st =>`
191			`ExtendFrame := '0';`
192			`GetNew <= '0';`
193			`RxFrame <= '1';`
194
195			`F0od_n <= '1';`
196			`Rx_en <= '0';`
197
198			`IF C2 = '1' THEN`
199
200			`IF counter >= drop_count THEN`
201			`IF TxDisable = '1' THEN`
202			`DSTo <= '1';`
203			`Tx_En <= '0';`
204			`ELSE`
205
206			`IF (EnableSerialIF = '1') THEN`
207			`DSTo <= SerDi;`
208			`ELSE`
209			`DSTo <= Tx_reg(7);`
210			`END IF;`
211
212			`Tx_En <= '1';`
213			`END IF;`
214
215			`Drop := '0';`
216
217			`ELSE`
218			`DSTo <= 'Z';`
219			`Tx_En <= '0';`
220			`Drop := '1';`
221			`END IF;`
222
223			`State <= READ_st;`
224
225			`ELSE`
226
227			`Tx_En <= '0';`
228
229			`END IF;`
230
231			`WHEN READ_st =>`
232			`ExtendFrame := '0';`
233			`GetNew <= '0';`
234			`RxFrame <= '1';`
235			`Tx_En <= '0';`
236
237			`IF C2 = '0' THEN`
238
239			`DSTi_reg <= DSTi;`
240			`SerDo <= DSTi;`
241
242			`IF counter = Tot_count THEN`
243
244			`State <= IDLE_st;`
245			`F0od_n <= '0';`
246
247			`ELSE`
248			`State <= WRITE_st;`
249			`F0od_n <= '1';`
250
251			`END IF;`
252
253			`counter := counter + 1;`
254
255			`Rx_En <= NOT Drop;`
256			`ELSE`
257			`Rx_En <= '0';`
258			`END IF;`
259
260			`END CASE;`
261
262			`END IF;`
263			`END PROCESS fsm;`
264			`-------------------------------------------------------------------------------`
265			`-------------------------------------------------------------------------------`
266			`-- Rx Machines`
267			`-------------------------------------------------------------------------------`
268			`-- purpose: Rx Serial To parellel`
269			`-- type : sequential`
270			`RxS2P : PROCESS (CLK_I, rst_n)`
271			`VARIABLE Rx_count : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Rx Internal bit counter`
272
273			`BEGIN -- process RxS2P`
274			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
275			`Rx_count := "000";`
276			`RxFlag <= '0';`
277			`Rx_Reg <= (OTHERS => '1');`
278			`EnShift <= '0';`
279			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
280
281			`IF Rx_En = '1' THEN`
282
283			`Rx_Reg <= Rx_Reg(6 DOWNTO 0) & DSTi_reg;`
284
285			`IF Rx_count = "111" THEN`
286			`Rx_count := "000";`
287
288			`RxFlag <= '1';`
289
290			`EnShift <= '1';`
291			`ELSE`
292			`Rx_count := Rx_count + 1;`
293			`RxFlag <= '0';`
294			`EnShift <= '0';`
295			`END IF;`
296			`ELSE`
297			`RxFlag <= '0';`
298			`EnShift <= '0';`
299			`END IF;`
300
301			`END IF;`
302			`END PROCESS RxS2P;`
303			`-------------------------------------------------------------------------------`
304			`-- purpose: Rx Backend`
305			`-- type : sequential`
306			`-- inputs : CLK_I, rst_n`
307			`-- outputs:`
308			`RxBackend : PROCESS (CLK_I, rst_n)`
309			`VARIABLE state : STD_LOGIC; -- Internal State`
310			`BEGIN -- process RxBackend`
311			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
312			`State := '0';`
313			`RxD <= (OTHERS => '0');`
314			`RxRdy <= '0';`
315			`FramErr <= '0';`
316			`RxValidData <= '0';`
317
318			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
319
320			`CASE State IS`
321
322			`WHEN '0' =>`
323			`RxRdy <= '0';`
324			`FramErr <= '0';`
325
326			`IF RxFlag = '1' THEN`
327			`RxD <= Rx_Reg;`
328			`State := '1';`
329			`END IF;`
330
331			`WHEN '1' =>`
332			`RxRdy <= '1';`
333			`RxValidData <= RxFrame;`
334			`IF RxFlag = '1' THEN`
335			`State := '0';`
336			`FramErr <= '1';`
337			`-- RxValidData <= RxFrame;`
338			`ELSIF RxRead = '1' THEN`
339
340			`-- RxValidData <= RxFrame;`
341
342			`State := '0';`
343			`FramErr <= '0';`
344			`END IF;`
345
346			`WHEN OTHERS =>`
347			`RxRdy <= '0';`
348			`State := '0';`
349			`FramErr <= '1';`
350			`RxValidData <= RxFrame;`
351			`END CASE;`
352			`END IF;`
353			`END PROCESS RxBackend;`
354			`-------------------------------------------------------------------------------`
355			`-- Tx Machines`
356			`-------------------------------------------------------------------------------`
357			`-- purpose: Tx Parellel to serial`
358			`-- type : sequential`
359			`-- inputs : CLK_I, rst_n`
360			`-- outputs:`
361			`TxP2S : PROCESS (CLK_I, rst_n)`
362			`VARIABLE Tx_Count : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Tx Bit counter`
363			`BEGIN -- process TxP2S`
364			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
365			`Tx_Count := "000";`
366			`Tx_reg <= (OTHERS => '1');`
367			`TxFlag <= '0';`
368
369			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
370
371			`IF TxDisable = '0' AND GetNew = '1' THEN`
372			`Tx_reg <= Tx_reg_i;`
373			`TxFlag <= '1';`
374
375			`ELSE`
376			`IF Tx_En = '1' THEN`
377
378			`IF Tx_count = "111" THEN`
379			`Tx_count := "000";`
380
381			`Tx_Reg <= Tx_Reg_i;`
382			`TxFlag <= '1';`
383			`ELSE`
384			`Tx_count := Tx_count + 1;`
385			`TxFlag <= '0';`
386			`Tx_Reg <= Tx_Reg(6 DOWNTO 0) & '1';`
387
388			`END IF;`
389
390			`ELSE`
391			`TxFlag <= '0';`
392			`END IF;`
393			`END IF;`
394			`END IF;`
395			`END PROCESS TxP2S;`
396			`-------------------------------------------------------------------------------`
397			`-- purpose: Tx Backend machine`
398			`-- type : sequential`
399			`-- inputs : CLK_I, rst_n`
400			`-- outputs:`
401			`TxBackend : PROCESS (CLK_I, rst_n)`
402			`VARIABLE state : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Internal State`
403			`BEGIN -- process TxBackend`
404			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
405
406			`State := "11"; -- Wait for NewValidFrame`
407			`TxRdy <= '0';`
408			`TxErr <= '0';`
409			`Tx_Reg_i <= (OTHERS => '1');`
410
411			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
412
413			`CASE State IS`
414			`WHEN"11" =>`
415			`TxRdy <= '1';`
416
417			`IF TxValidData = '1' THEN`
418			`State := "01"; -- Get New byte`
419			`END IF;`
420
421			`WHEN "00" =>`
422			`TxRdy <= '0';`
423
424			`IF TxFlag = '1' THEN -- and TxDisable = '0' then`
425
426			`State := "01"; -- Get New Byte`
427			`END IF;`
428
429			`WHEN "01" =>`
430			`TxRdy <= '1';`
431
432			`IF TxFlag = '1' OR TxValidData = '0' THEN`
433			`State := "11"; -- Wait for New frame`
434			`TxErr <= '1';`
435			`Tx_Reg_i <= (OTHERS => '1');`
436			`ELSIF TxWrite = '1' THEN`
437			`State := "00";`
438			`TxErr <= '0';`
439			`Tx_Reg_i <= TxD;`
440			`END IF;`
441
442			`WHEN OTHERS =>`
443			`TxRdy <= '0';`
444			`State := "11";`
445			`TxErr <= '1';`
446			`Tx_Reg_i <= (OTHERS => '1');`
447			`END CASE;`
448			`END IF;`
449			`END PROCESS TxBackend;`
450			`-------------------------------------------------------------------------------`
451			`-------------------------------------------------------------------------------`
452			`-- Serial Interface logic`
453			`-------------------------------------------------------------------------------`
454			`Tx_en0 <= EnableRegister(0) AND Tx_En;`
455			`Tx_en1 <= EnableRegister(1) AND Tx_En;`
456			`Tx_en2 <= EnableRegister(2) AND Tx_En;`
457			`Rx_en0 <= EnableRegister(0) AND Rx_En;`
458			`Rx_en1 <= EnableRegister(1) AND Rx_En;`
459			`Rx_en2 <= EnableRegister(2) AND Rx_En;`
460			`-------------------------------------------------------------------------------`
461			`-- purpose: Serial Enable shift register`
462			`-- type : sequential`
463			`-- inputs : clock, rst_n`
464			`-- outputs:`
465			`SerialEnShift : PROCESS (CLK_I, rst_n)`
466
467			`BEGIN -- PROCESS SerialEnShift`
468
469			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
470			`EnableRegister <= "00000000000000000000000000000001";`
471			`ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
472
473			`IF (EnShift = '1') THEN`
474			`EnableRegister <= EnableRegister(30 DOWNTO 0) & EnableRegister(31);`
475			`END IF;`
476			`END IF;`
477
478			`END PROCESS SerialEnShift;`
479			`END tdm_cont_rtl;`