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        %% $Log: not supported by cvs2svn $
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        %% Revision 1.5  2001/05/25 18:43:39  jamil
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        %% PreRelease reviews
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        %%
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        %% Revision 1.4  2001/04/10 22:24:35  jamil
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        %% Wishbone logi added
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        %%
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        %% Revision 1.3  2001/04/09 21:33:54  jamil
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        %% FIFO buffers calculations added
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        %%
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        %% Revision 1.2  2001/04/04 21:28:56  jamil
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        %% ISDN support added
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        %%
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\documentclass[a4paper,11pt]{article}
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\usepackage{fancyheadings}
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\usepackage{lastpage}
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\pagestyle{fancy}
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\usepackage[dvips]{graphicx}
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%% defined commands
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\newcommand{\openhw}{\mbox{\textbf{\textit{OpenHW}}}}
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\newcommand{\opendesign}{\mbox{\textbf{\textit{OpenDesign}}}}
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\newcommand{\openipcore}{\mbox{\textbf{\textit{OpenIPCore}}}}
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\newcommand{\opencores}{\mbox{\textbf{\textit{www.OpenCores.org~}}}}
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%% addcomment command: Author name: Comments
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\newcommand{\addcomment}[2]{\rule{1ex}{1ex} \emph{Comment by \textbf{#1}: #2 }\rule{1ex}{1ex}}
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%% addauthor command: Author name : List of changes: date: contact address
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\newcommand{\addauthor}[4]{#1 & #2 & #3 & #4 \\ \hline}
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%% Optional suffix or prefix
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\newcommand{\prefix}[1]{[\textit{#1\_}]}
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\newcommand{\suffix}[1]{[\textit{\_#1}]}
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\author{Jamil Khatib}
42
\title{TDM controller core}
43
 
44
 
45
 
46
%% Hyphenation list %%
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\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}
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49
 
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%%Headers & footers
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\lhead{\uppercase\rightmark}
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\chead{}
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\rhead{\bfseries \opencores Project}
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\lfoot{TDM controller}
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\cfoot{}
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\rfoot{\thepage~ of \pageref{LastPage}}
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\setlength{\headrulewidth}{0.4pt}
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\setlength{\footrulewidth}{0.4pt}
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%% begin Document
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\begin{document}
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%% Cover page
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\maketitle
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65
\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}
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\thispagestyle{empty}
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69
\newpage
70
 
71
 
72
%%Table of contents page
73
\tableofcontents
74
 
75
 
76
\newpage
77
 
78
\section{List of authors and changes}
79
 
80
\begin{tabular}{|l|l|l|l|l|}
81
\hline
82
Name & Changes & Date & Contact address\\
83
\hline
84
\hline
85
 
86
\addauthor{Jamil Khatib}{Initial release}{3-2-2001}{khatib@ieee.org}
87
\addauthor{Jamil Khatib}{General review and CPU interface added}{10-2-2001}{khatib@ieee.org}
88
\addauthor{Jamil Khatib}{ISDN support added}{3-4-2001}{khatib@ieee.org}
89
\addauthor{Jamil Khatib}{Buffer Calculations added}{9-4-2001}{khatib@ieee.org}
90
\addauthor{Jamil Khatib}{General review}{25-5-2001}{khatib@ieee.org}
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%% use add author command here
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93
 
94
\end{tabular}
95
 
96
\newpage
97
 
98
%%- New section -%%
99
%%------------------------------------------%%
100
\section{Project Definition}
101
 
102
\subsection{Introduction}
103
Time devision multiplexing is a scheme used to communicate between systems or devices via shared interface lines. Each device or system gets the access to this interface in a single time slot.
104
 
105
\subsection{Objectives}
106
The aim of this project is to develop the basic TDM functionalities to be used by many communication systems like ISDN, E1, and voice codecs.
107
 
108
 
109
%%- New section -%%
110
%%------------------------------------------%%
111
\section{Specifications}
112
 
113
\subsection{System Features Specification}
114
\begin{enumerate}
115
\item Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps)
116
\item Supports ST-Bus (Serial Telecom bus) interface.
117
\item Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.
118
\item Supports read for all or partial TDM slots from the ST-bus.
119
\item Supports write for all or partial TDM slots to ST-bus.
120
\item It supports $N\times 64$ mode (i.e. it supports sampling (or writing) to $N$ consecutive time slots)
121
\item Supports two serial lines one input and one output.
122
\item Can be connected to other ST-Bus compatible devices via serial or star configurations.
123
\item If no data is available for transmission it sends all ones.
124
\item Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
125
\item Optional External FIFO buffer, configuration and status registers.
126
\item The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel.
127
\item ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots.
128
%\item Shared memory interface will be added in the future instead of the internal FIFOs for systems that support shared memory.
129
\end{enumerate}
130
 
131
\subsection{External Interfaces}
132
 
133
 
134
\begin{tabular}{|l|l|l|}
135
\hline
136
Signal name& Direction& Description\\
137
\hline
138
\hline
139
Control interface & & \\
140
\hline
141
\hline
142
CLK\_I & Input & System clock \\
143
Rst\_n & Input & System asynchronous reset (active low)\\
144
NoChannels[4:0] & Input & Number of time slots (Can be fixed)\\
145
DropChannels[4:0] & Input & Number of time slots to be dropped (Can be fixed)\\
146
\hline
147
\hline
148
Serial Interface (ST-Bus)& & \\
149
\hline
150
\hline
151
C2 & Input & Bus Clock\\
152
DSTi & Input& Receive serial Data\\
153
DSTo & Output & Transmit serial Data\\
154
F0\_n & Input & Framing pulse (active low)\\
155
F0od\_n & Output & Delayed Framing pulse (active low) generated after the channels has handled\\
156
\hline
157
\hline
158
Back-end Interface (Received)& &\\
159
\hline
160
\hline
161
RxD[7:0]& Output& Receive data bus\\
162
RxValidData& Output& Valid Data\\
163
FrameErr& Output& Error in the received data\\
164
Read& Input& Read byte\\
165
Ready& Output& Valid data exists\\
166
\hline
167
\hline
168
Back-end Interface (Transmited)& &\\
169
\hline
170
\hline
171
TxD[7:0]& Input& Transmit data bus\\
172
TxValidData& Input& Valid Data\\
173
Write& Input& Write byte\\
174
Ready& Output& Ready to get data\\
175
TxErr& Output& Buffer under flow\\
176
\hline
177
\end{tabular}
178
 
179
\subsubsection{Back-end interface mapping to Wishbone SoC bus}
180
The TDM backend interface is divided into two parts one for receive and one for transmit.It can be used as a slave core or master according to the below mapping. The core supports SINGLE READ/WRITE Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
181
\\
182
 
183
\begin{figure}[!h]
184
\includegraphics[angle=0,width=\textwidth,scale=.5]{wishlogo.ps}
185
\label{Logo}
186
\end{figure}
187
 
188
\begin{tabular}{|l|l|}
189
\hline
190
Signal Name& Wishbone signal\\
191
\hline
192
\hline
193
Master Configuration connected to FIFO& Receive channel\\
194
\hline
195
CLK\_I & CLK\_I\\
196
Rst & not RST\_I\\
197
RxD[7:0]& DAT\_O(7:0)\\
198
RxValidData& STB\_O\\
199
RxValidData& CYC\_O\\
200
Read& ACK\_I and not RTY\_I\\
201
Ready& WE\_O\\
202
FrameERR& TAG0\_O\\
203
\hline
204
 
205
Slave FIFO(two-clock domain FIFO)&\\
206
\hline
207
Data[7:0]& DAT\_I(7:0)\\
208
Chip Select& STB\_I\\
209
STB\_I and not FullFlag& ACK\_O\\
210
FullFlag& RTY\_O\\
211
Write& WE\_I\\
212
\hline
213
 
214
Slave Configuration &\\
215
\hline
216
 
217
CLK\_I & CLK\_I\\
218
Rst & not RST\_I\\
219
RxD[7:0]& DAT\_O(7:0)\\
220
RxValidData& TAG0\_O\\
221
ReadByte& not WE\_I\\
222
Ready& not RTY\_O\\
223
STB\_I and not WR\_I& ACK\_O\\
224
FrameERR& TAG1\_O\\
225
\hline
226
 
227
\end{tabular}
228
 
229
%%%%%%%%%%%%
230
\begin{tabular}{|l|l|}
231
\hline
232
Signal Name& Wishbone signal\\
233
\hline
234
\hline
235
Master Configuration connected to FIFO& Transmit channel\\
236
\hline
237
\hline
238
C2 & CLK\_I\\
239
Rst & not RST\_I\\
240
TxD[7:0]& DAT\_I(7:0)\\
241
Write& ACK\_I and not RTY\_I\\
242
Ready& not WE\_O\\
243
TxValidData& TAG0\_I\\
244
Always Active & CYC\_O\\
245
Always Active & STB\_O\\
246
 
247
\hline
248
 
249
Slave FIFO(two-clock domain FIFO)&\\
250
\hline
251
Data[31:0]& DAT\_I(31:0)\\
252
EmptyFlag& RTY\_O\\
253
Read& WE\_I\\
254
WE\_I and not EmptyFlag& ACK\_O\\
255
ChipSelect& STB\_I\\
256
 
257
\hline
258
 
259
Slave Configuration &\\
260
\hline
261
C2 & CLK\_I\\
262
Rst & not RST\_I\\
263
TxD[7:0]& DAT\_I(7:0)\\
264
TxValidData& STB\_I\\
265
Write&  WE\_I\\
266
Ready& not RTY\_O\\
267
STB\_I and WR\_I& ACK\_O\\
268
\hline
269
 
270
\end{tabular}
271
 
272
 
273
 
274
\subsubsection{CPU interface}
275
This interface is used when the FIFO and registers are included in the Core. This interface is compatible to WishBone slave bus interface that supports single read/write cycles and block cycles. The interface supports the following wishbone signals.
276
 
277
\begin{tabular}{|l|l|}
278
\hline
279
Signal& Note\\
280
\hline
281
\hline
282
RST\_I& Reset\\
283
CLK\_I& Clock\\
284
ADR\_I(2:0)& 3-bit address line\\
285
DAT\_O(7:0)& 8-bit receive data\\
286
DAT\_I(7:0)& 8-bit transmit data\\
287
WE\_I& Read/write\\
288
STB\_I& Strobe\\
289
ACK\_O& Acknowledge\\
290
CYC\_I& Cycle\\
291
RTY\_O& Retry\\
292
TAG0\_O& TxDone interrupt\\
293
TAG1\_O& RxReady interrupt\\
294
\hline
295
\end{tabular}
296
 
297
%%- New section -%%
298
%%------------------------------------------%%
299
\section{Internal Blocks}
300
 
301
 
302
%%- New section -%%
303
%%------------------------------------------%%
304
\section{Design description}
305
 
306
 
307
\subsection{ST-Bus interface}
308
The TDM controller interfaces to the TDM lines via serial telecom bus. The interface uses the external input clock (2.048MHz) for all of the internal serial logic. It detects the incoming framing pulse to synchronize the sampling and transmission of bits. The core reads and writes only the specified number of TDM channels (8-bits) by the size bus (No. of channels register). In the transmission mode the output pin should be disabled after writing the configured time slots. It generates also the output delayed framing pulse after it samples all the specified bits (TDM channels). This feature can be used to cascade controllers for different TDM channels.
309
 
310
\subsubsection{Design notes}
311
 
312
\subsubsection{Timing}
313
 
314
 
315
\subsection{External FIFO}
316
The controller has optional external FIFO buffers, one for data to be transmitted and one for data to be received. Status and control registers are available to control these FIFOs. These two blocks (FIFOs and registers) are  built around the TDM controller core which make them optional if the core is to be used in different kind of applications.
317
 
318
The current implementation supports the following configuration:
319
The size of the Transmit and receive FIFOs is $(8\times 32)$ bits which enables the whole TDM frame to be buffered.
320
 
321
The transmit buffer is used to prevent underflow while transmitting bytes to the line. All bytes will be available once the transmit is enabled. If the transmit FIFO is empty the core will transmit ones. The Receive buffer is used to provide data burst transfer to the Back end interface which prevents the back end from reading each byte alone. The FIFO size is suitable for operating frequencies 2.048MHz on the serial interface and 20 MHz on the back end interface. Other frequencies can operate if the back end can read the entire TDM frame before the first byte of the next frame is written (the next calculations is an example to be applied for different frequencies)
322
 
323
8 bits (Time needed to receive the first byte of the next frame) / 2.048MHz = 3.9 us
324
 
325
32 Bytes (Maximum frame size) / 20MHz = 1.6 us
326
 
327
These FIFOs are implemented on Single port memory. It is the responsibility of the external interface to write/read data to/from the FIFOs. TxDone and RxRdy interrupts are generated when the Tx buffer is empty and Rx buffer has data respectively .
328
 
329
\subsubsection{Notes}
330
\begin{itemize}
331
%%\item  \textbf{Transmit Operation:} The transmit FIFO interface uses RTY\_O signal when the FIFO is full which means that the core can not accept more data. The writing to the Transmit FIFO register can be retried when the RTY\_O signal is deasserted on the same cycle or on new burst cycle.
332
 
333
\item \textbf{Transmit Operation:} If the transmit FIFO is empty not enough data bytes is available according to no. of channels (caused by incomplete burst transfer}, the core sets the Aborted bit in the TX status and control register and sends all ones in the transmit serial line.
334
 
335
\item \textbf{Transmit Operation:} The back end (software) should write data to the Tx buffer register according to the configured number of time slots. The transmission will start only after the specified number of slots are available in the buffer other wise Aborted bit of the Tx Status register will be set and all ones will be transmitted  in this slot.
336
 
337
\item \textbf{Receive Operation:} When Receive FIFO is full It drops the second FIFO contents and sets overflow bit in the Rx Status and Control register.
338
 
339
\item \textbf{Receive Operation:} When RxRdy Interrupt is asserted (or RxRdy bit is set) the back end interface (software) must read the specified number of slots from the Rx Data buffer register or the buffer will not be marked as empty.
340
%\item  \textbf{Receive Operation:} When the FIFO is empty the core uses the RTY\_O signal to indicate no more read can be done from the Rx FIFO register.
341
\end{itemize}
342
 
343
\subsection{ISDN support}
344
In order to provide $(2B+D)$ ISDN support three HDLC controllers should be used on three time slots. The serial data the of first three time slots will enter (or get out) directly to (from) the three parallel HDLC controllers if HDLCen bit is set in the Tx Status and Control register. The HDLC controllers will be managed through the enable signals (each controller will be enabled on its corresponding time slot).
345
 
346
Eventhoush the ISDN controller is based on TDM but separate controller will be used that extracts and writes 2B+D only.
347
 
348
\begin{figure}[!h]
349
\includegraphics[angle=0,width=\textwidth]{tdm_ISDN_top.ps}
350
\caption{ISDN support}\label{isdn}
351
\end{figure}
352
 
353
 
354
\subsection{Registers}
355
All internal registers are 32-bit width.
356
 
357
\subsubsection{Transmit}
358
 
359
\begin{tabular}{l l}
360
\textbf{Tx Status and Control Register: Tx\_SC} & Offset Address = 0x0\\
361
\end{tabular}\\
362
 
363
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
364
\hline
365
\hline
366
BIT   & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
367
\hline
368
FIELD &N/A &N/A &N/A & N/A& must be set to 0& TxUnderflow& TxOverflow& TxDone(empty)\\
369
\hline
370
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
371
\hline
372
R/W   & RO& RO& RO&   RO&  RW&   RO& RO& RO\\
373
\hline
374
\end{tabular}\\
375
 
376
\begin{tabular}{l l}
377
\textbf{Tx FIFO buffer register: Tx\_Buffer} & Offset Address = 0x1\\
378
\end{tabular}\\
379
 
380
\begin{tabular}{|l||c|}
381
\hline
382
\hline
383
BIT   & 31-0\\
384
\hline
385
FIELD & Transmit Data\\
386
\hline
387
RESET & 0x0\\
388
\hline
389
R/W   & WO\\
390
\hline
391
\end{tabular}
392
writing before TxDone is set has no effect. Extra writes more than defined by noChannels - DropChannels has no effect either.
393
 
394
\subsubsection{Receive}
395
 
396
\begin{tabular}{l l}
397
\textbf{Rx Status and Control Register: Rx\_SC} & Offset Address = 0x2\\
398
\end{tabular}\\
399
 
400
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
401
\hline
402
\hline
403
BIT   & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
404
\hline
405
FIELD &N/A &N/A &N/A & N/A& N/A& RxBufferOverflow& RxLineOverflow& RxReady(Full)\\
406
\hline
407
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
408
\hline
409
R/W   & RO& RO& RO&   RO&  RO&   RO&  RO& RO\\
410
\hline
411
\end{tabular}\\
412
 
413
RxLineOverflow: Overflow on serial Line buffer.
414
 
415
\begin{tabular}{l l}
416
\textbf{Rx FIFO buffer register: Rx\_Buffer} & Offset Address = 0x3\\
417
\end{tabular}\\
418
 
419
\begin{tabular}{|l||c|}
420
\hline
421
\hline
422
BIT   & 31-0\\
423
\hline
424
FIELD & Received Data byte\\
425
\hline
426
RESET & 0x0\\
427
\hline
428
R/W   & RO\\
429
\hline
430
\end{tabular}\\
431
Reading before RxRdy is set or more than NoChannels-DropChannels carries no data.
432
 
433
\begin{tabular}{l l}
434
\textbf{configuration register: CFG} & Offset Address = 0x4\\
435
\end{tabular}\\
436
 
437
\begin{tabular}{|l||c|c|c|}
438
\hline
439
\hline
440
BIT  & 12-8 &7-5 &4-0\\
441
\hline
442
FIELD & DropChannels & reserved & No. of channels\\
443
\hline
444
RESET & 0x00 & 0X0 &0x00\\
445
\hline
446
R/W   & RW& RO & RW\\
447
\hline
448
\end{tabular}\\
449
No of channels indicates total number of channels to be handled after the framing pulse by the controller. Single channel at least must be handled so 0x00 indicates single channel and so on.\\
450
DropChannels indicates number of channels to be dropped (not handled) after the framing pulse and before the first channel to be handled.\\
451
 
452
Example number of channels to be read is 2 starting after 3 channels from the framing pulse: $NoChannels = 0x04$ and $DropChannels = 0x03$\\
453
 
454
 
455
\textbf{ISDN registers} The ISDN controller is a separate core that has three HDLC controllers. Each HDLC controller has its own Wishbone interface and registers for information about the HDLC registers refer to the HDLC core document.
456
 
457
 
458
 
459
\subsection{Diagrams}
460
 
461
\begin{figure}[!h]
462
\includegraphics[angle=0,width=\textwidth]{tdm_core.ps}
463
\caption{TDM core}\label{Core}
464
\end{figure}
465
 
466
 
467
\begin{figure}[!h]
468
\includegraphics[angle=0,width=\textwidth]{tdm_top.ps}
469
\caption{TDM controller}\label{top}
470
\end{figure}
471
 
472
%%- New section -%%
473
%%------------------------------------------%%
474
\section{Testing and verifications}
475
 
476
 
477
\begin{tabular}{|l|l|l|}
478
\hline
479
Requirement & Test method & Validation method \\
480
\hline
481
\hline
482
Interface timing & &\\
483
\hline
484
& & \\
485
\hline
486
\hline
487
Functionality & & \\
488
\hline
489
\end{tabular}
490
\subsection{Simulation and Test benches}
491
 
492
\subsection{Verification techniques and algorithms}
493
 
494
\subsection{Test plans}
495
 
496
%%- New section -%%
497
%%------------------------------------------%%
498
\section{Implementations}
499
 
500
The  design is implemented using the VHDL language. The design is divided into three blocks, serial interface, Buffers and Wishbone interface with internal registers. The TDM controller uses the wishbone clock as its main clock and uses the ST-bus clock as enables for the internal logic.
501
 
502
 
503
\subsection{Scripts, files and any other information}
504
\begin{tabular}{|l|l|}
505
\hline
506
Core Files & \\
507
\hline
508
tdm\_cont.vhd & Serial Interface\\
509
RxTDMBuff.vhd & Rx Buffer\\
510
TxTDMBuffer.vhd & Tx Buffer\\
511
tdm\_wb\_if.vhd & Wish bone interface and registers\\
512
tdm\_core\_top.vhd & TDM top block\\
513
components\_pkg.vhd & TDM core components\\
514
\hline
515
Script files & \\
516
Build\_TDM\_cont.csh & NC-sim build all files script\\
517
cds.lib & NC-sim configuration file\\
518
hdl.var & NC-sim configuration file\\
519
\hline
520
Test Bench files & \\
521
tdm\_cont\_top.vhd & TDM controller Top test bench\\
522
\hline
523
ISDN controller & \\
524
ISDN\_cont.vhd & Serial Interface\\
525
ISDN\_cont\_top.vhd & ISDN top block\\
526
\hline
527
\end{tabular}
528
Notes: in order to implement the ISDN controller HDLC core files must be included.
529
The following memory cores files must be included to implement the buffers: tools\_pkg.vhd , mem\_pkg.vhd and spmem.vhd
530
 
531
%%- New section -%%
532
%%------------------------------------------%%
533
\section{Reviews and comments}
534
 
535
%%- New section -%%
536
%%------------------------------------------%%
537
\section{References}
538
 
539
 
540
\end{document}

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