1 |
6 |
root |
`timescale 1ns / 1ns
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2 |
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3 |
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module tdm_switch_top (
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4 |
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clk_in,
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5 |
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clk_out,
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6 |
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frame_sync,
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7 |
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rx_stream,
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8 |
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tx_stream,
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9 |
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reset,
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10 |
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mpi_clk,
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11 |
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mpi_cs,
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12 |
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mpi_rw,
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13 |
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mpi_addr,
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14 |
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mpi_data_in,
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15 |
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mpi_data_out
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16 |
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);
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17 |
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18 |
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//=======================================================================================
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19 |
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//====================== IO PORT DESCRIPTION ============================================
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20 |
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21 |
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input clk_in;
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22 |
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output clk_out;
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23 |
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output frame_sync;
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24 |
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25 |
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input [7:0] rx_stream;
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26 |
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output [7:0] tx_stream;
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27 |
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28 |
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input reset;
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29 |
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30 |
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input mpi_clk;
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31 |
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input mpi_cs;
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32 |
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input mpi_rw;
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33 |
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input [8:0] mpi_addr;
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34 |
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input [8:0] mpi_data_in;
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35 |
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output [8:0] mpi_data_out;
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36 |
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37 |
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//=======================================================================================
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38 |
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//====================== PARAMETER DESCRIPTION ==========================================
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39 |
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40 |
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parameter pu = 1'b1;
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41 |
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parameter pd = 1'b0;
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42 |
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43 |
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//=======================================================================================
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44 |
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//====================== REGISTER DESCRIPTION ===========================================
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45 |
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46 |
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reg [7:0] rx_shift_reg_0;
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47 |
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reg [7:0] rx_shift_reg_1;
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48 |
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reg [7:0] rx_shift_reg_2;
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reg [7:0] rx_shift_reg_3;
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reg [7:0] rx_shift_reg_4;
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reg [7:0] rx_shift_reg_5;
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reg [7:0] rx_shift_reg_6;
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reg [7:0] rx_shift_reg_7;
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54 |
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55 |
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reg [7:0] tx_shift_reg_0;
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56 |
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reg [7:0] tx_shift_reg_1;
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57 |
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reg [7:0] tx_shift_reg_2;
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58 |
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reg [7:0] tx_shift_reg_3;
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59 |
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reg [7:0] tx_shift_reg_4;
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60 |
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reg [7:0] tx_shift_reg_5;
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61 |
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reg [7:0] tx_shift_reg_6;
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62 |
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reg [7:0] tx_shift_reg_7;
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63 |
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64 |
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reg [7:0] rx_buf_reg_0;
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65 |
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reg [7:0] rx_buf_reg_1;
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reg [7:0] rx_buf_reg_2;
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67 |
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reg [7:0] rx_buf_reg_3;
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68 |
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reg [7:0] rx_buf_reg_4;
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69 |
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reg [7:0] rx_buf_reg_5;
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reg [7:0] rx_buf_reg_6;
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71 |
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reg [7:0] rx_buf_reg_7;
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72 |
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73 |
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reg [7:0] tx_buf_reg_0;
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74 |
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reg [7:0] tx_buf_reg_1;
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reg [7:0] tx_buf_reg_2;
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reg [7:0] tx_buf_reg_3;
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reg [7:0] tx_buf_reg_4;
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reg [7:0] tx_buf_reg_5;
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reg [7:0] tx_buf_reg_6;
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80 |
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reg [7:0] tx_buf_reg_7;
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81 |
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82 |
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reg [1:0] frame_delay_cnt_0;
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reg [1:0] frame_delay_cnt_1;
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reg [1:0] frame_delay_cnt_2;
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reg [1:0] frame_delay_cnt_3;
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86 |
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reg [1:0] frame_delay_cnt_4;
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87 |
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reg [1:0] frame_delay_cnt_5;
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reg [1:0] frame_delay_cnt_6;
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reg [1:0] frame_delay_cnt_7;
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91 |
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reg [1:0] frame_delay_buf_0;
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reg [1:0] frame_delay_buf_1;
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reg [1:0] frame_delay_buf_2;
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reg [1:0] frame_delay_buf_3;
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reg [1:0] frame_delay_buf_4;
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reg [1:0] frame_delay_buf_5;
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reg [1:0] frame_delay_buf_6;
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reg [1:0] frame_delay_buf_7;
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100 |
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reg div_reg;
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101 |
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reg [8:0] frame_cnt;
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102 |
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reg [4:0] c_mem_addr_cnt;
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103 |
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reg [4:0] d_mem_addr_cnt;
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104 |
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reg [15:0] data_in_bus;
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105 |
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reg [1:0] ctrl_out_reg;
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106 |
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reg mem_page_sel;
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107 |
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108 |
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//=======================================================================================
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109 |
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//====================== WIRE DESCRIPTION ===============================================
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110 |
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111 |
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wire clk_4096k;
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112 |
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wire clk_2048k;
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113 |
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wire frame_8k;
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114 |
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wire g_rst;
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115 |
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116 |
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wire tx_sr_load;
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117 |
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wire rx_buf_load;
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118 |
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119 |
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wire load_rx_buf_0;
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120 |
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wire load_rx_buf_1;
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121 |
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wire load_rx_buf_2;
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122 |
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wire load_rx_buf_3;
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123 |
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wire load_rx_buf_4;
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124 |
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wire load_rx_buf_5;
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125 |
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wire load_rx_buf_6;
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126 |
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wire load_rx_buf_7;
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127 |
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128 |
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wire tx_buf_wen;
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129 |
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wire data_wen;
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130 |
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wire cd_en;
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131 |
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132 |
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wire [7:0] d_mem_addr;
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133 |
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wire [1:0] d_mem_low_addr;
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134 |
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wire [4:0] d_mem_high_addr;
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135 |
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136 |
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wire [7:0] c_mem_addr;
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137 |
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wire [2:0] c_mem_low_addr;
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138 |
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wire [4:0] c_mem_high_addr;
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139 |
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140 |
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wire [7:0] data_out_bus;
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141 |
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142 |
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wire [2:0] tx_buf_addr;
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143 |
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144 |
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wire [8:0] cd_mem_addr;
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145 |
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wire [15:0] cd_data;
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146 |
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147 |
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wire ram_en;
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148 |
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149 |
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wire [15:0] mpi_mem_bus_in;
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150 |
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wire [15:0] mpi_mem_bus_out;
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151 |
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152 |
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wire [1:0] ctrl_in;
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153 |
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wire [1:0] ctrl_out;
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154 |
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155 |
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//=======================================================================================
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156 |
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//====================== IO AND CLK BUFFERS =============================================
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157 |
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158 |
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assign g_rst = reset;
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159 |
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assign clk_4096k = clk_in;
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160 |
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assign clk_2048k = div_reg;
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161 |
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assign clk_out = clk_2048k;
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162 |
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assign frame_sync = frame_8k;
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163 |
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164 |
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always @ (posedge clk_4096k or negedge g_rst)
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165 |
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if (!g_rst)
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166 |
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div_reg <= 0;
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167 |
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else
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168 |
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div_reg <= ~div_reg;
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169 |
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170 |
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//=======================================================================================
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171 |
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//====================== FRAME SYNC GENERATION ==========================================
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172 |
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173 |
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always @ (negedge clk_4096k or negedge g_rst)
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174 |
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if (!g_rst)
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175 |
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frame_cnt <= 0;
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176 |
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else
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177 |
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frame_cnt <= frame_cnt + 1;
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178 |
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179 |
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assign frame_8k = (frame_cnt == 9'h00A) ? 1'b1 : 1'b0;
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180 |
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181 |
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//=======================================================================================
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182 |
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//====================== SYNC SIGNALS FOR INPUT STREAMS =================================
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183 |
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184 |
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assign rx_buf_load = (frame_cnt[3:0] == 4'hA) ? 1'b1 : 1'b0;
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185 |
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186 |
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always @ (negedge clk_2048k or posedge rx_buf_load)
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187 |
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if (rx_buf_load)
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188 |
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begin
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189 |
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frame_delay_cnt_0 <= frame_delay_buf_0 + 1;
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190 |
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frame_delay_cnt_1 <= frame_delay_buf_1 + 1;
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191 |
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frame_delay_cnt_2 <= frame_delay_buf_2 + 1;
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192 |
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frame_delay_cnt_3 <= frame_delay_buf_3 + 1;
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193 |
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frame_delay_cnt_4 <= frame_delay_buf_4 + 1;
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194 |
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frame_delay_cnt_5 <= frame_delay_buf_5 + 1;
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195 |
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frame_delay_cnt_6 <= frame_delay_buf_6 + 1;
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196 |
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frame_delay_cnt_7 <= frame_delay_buf_7 + 1;
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197 |
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end
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198 |
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else
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199 |
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begin
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200 |
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if (frame_delay_cnt_0 == 0)
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201 |
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frame_delay_cnt_0 <= frame_delay_cnt_0;
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202 |
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else
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203 |
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frame_delay_cnt_0 <= frame_delay_cnt_0 + 2'b11;
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204 |
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205 |
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if (frame_delay_cnt_1 == 0)
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206 |
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frame_delay_cnt_1 <= frame_delay_cnt_1;
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207 |
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else
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208 |
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frame_delay_cnt_1 <= frame_delay_cnt_1 + 2'b11;
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209 |
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210 |
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if (frame_delay_cnt_2 == 0)
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211 |
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frame_delay_cnt_2 <= frame_delay_cnt_2;
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212 |
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else
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213 |
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frame_delay_cnt_2 <= frame_delay_cnt_2 + 2'b11;
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214 |
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215 |
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if (frame_delay_cnt_3 == 0)
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216 |
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frame_delay_cnt_3 <= frame_delay_cnt_3;
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217 |
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else
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218 |
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frame_delay_cnt_3 <= frame_delay_cnt_3 + 2'b11;
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219 |
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220 |
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if (frame_delay_cnt_4 == 0)
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221 |
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frame_delay_cnt_4 <= frame_delay_cnt_4;
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222 |
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else
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223 |
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frame_delay_cnt_4 <= frame_delay_cnt_4 + 2'b11;
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224 |
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225 |
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if (frame_delay_cnt_5 == 0)
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226 |
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frame_delay_cnt_5 <= frame_delay_cnt_5;
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227 |
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else
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228 |
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frame_delay_cnt_5 <= frame_delay_cnt_5 + 2'b11;
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229 |
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230 |
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if (frame_delay_cnt_6 == 0)
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231 |
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frame_delay_cnt_6 <= frame_delay_cnt_6;
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232 |
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else
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233 |
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frame_delay_cnt_6 <= frame_delay_cnt_6 + 2'b11;
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234 |
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235 |
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if (frame_delay_cnt_7 == 0)
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236 |
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frame_delay_cnt_7 <= frame_delay_cnt_7;
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237 |
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else
|
238 |
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frame_delay_cnt_7 <= frame_delay_cnt_7 + 2'b11;
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239 |
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end
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240 |
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|
241 |
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assign load_rx_buf_0 = (frame_delay_cnt_0 == 2'b01) ? 1'b1 : 1'b0;
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242 |
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assign load_rx_buf_1 = (frame_delay_cnt_1 == 2'b01) ? 1'b1 : 1'b0;
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243 |
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assign load_rx_buf_2 = (frame_delay_cnt_2 == 2'b01) ? 1'b1 : 1'b0;
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244 |
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assign load_rx_buf_3 = (frame_delay_cnt_3 == 2'b01) ? 1'b1 : 1'b0;
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245 |
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assign load_rx_buf_4 = (frame_delay_cnt_4 == 2'b01) ? 1'b1 : 1'b0;
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246 |
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assign load_rx_buf_5 = (frame_delay_cnt_5 == 2'b01) ? 1'b1 : 1'b0;
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247 |
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assign load_rx_buf_6 = (frame_delay_cnt_6 == 2'b01) ? 1'b1 : 1'b0;
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248 |
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assign load_rx_buf_7 = (frame_delay_cnt_7 == 2'b01) ? 1'b1 : 1'b0;
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249 |
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250 |
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//=======================================================================================
|
251 |
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//====================== SERIAL INPUT TO PARALLEL CONVERTIONS ===========================
|
252 |
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253 |
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always @ (negedge clk_2048k)
|
254 |
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begin
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255 |
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rx_shift_reg_0 <= {rx_stream[0], rx_shift_reg_0[7:1]};
|
256 |
|
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rx_shift_reg_1 <= {rx_stream[1], rx_shift_reg_1[7:1]};
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257 |
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rx_shift_reg_2 <= {rx_stream[2], rx_shift_reg_2[7:1]};
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258 |
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rx_shift_reg_3 <= {rx_stream[3], rx_shift_reg_3[7:1]};
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259 |
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rx_shift_reg_4 <= {rx_stream[4], rx_shift_reg_4[7:1]};
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260 |
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rx_shift_reg_5 <= {rx_stream[5], rx_shift_reg_5[7:1]};
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261 |
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rx_shift_reg_6 <= {rx_stream[6], rx_shift_reg_6[7:1]};
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262 |
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rx_shift_reg_7 <= {rx_stream[7], rx_shift_reg_7[7:1]};
|
263 |
|
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end
|
264 |
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|
265 |
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//=======================================================================================
|
266 |
|
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//====================== Rx BUFFER LOAD =================================================
|
267 |
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|
268 |
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always @ (posedge clk_2048k)
|
269 |
|
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if (load_rx_buf_0)
|
270 |
|
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rx_buf_reg_0 <= rx_shift_reg_0;
|
271 |
|
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else
|
272 |
|
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rx_buf_reg_0 <= rx_buf_reg_0;
|
273 |
|
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|
274 |
|
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always @ (posedge clk_2048k)
|
275 |
|
|
if (load_rx_buf_1)
|
276 |
|
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rx_buf_reg_1 <= rx_shift_reg_1;
|
277 |
|
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else
|
278 |
|
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rx_buf_reg_1 <= rx_buf_reg_1;
|
279 |
|
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|
280 |
|
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always @ (posedge clk_2048k)
|
281 |
|
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if (load_rx_buf_2)
|
282 |
|
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rx_buf_reg_2 <= rx_shift_reg_2;
|
283 |
|
|
else
|
284 |
|
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rx_buf_reg_2 <= rx_buf_reg_2;
|
285 |
|
|
|
286 |
|
|
always @ (posedge clk_2048k)
|
287 |
|
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if (load_rx_buf_3)
|
288 |
|
|
rx_buf_reg_3 <= rx_shift_reg_3;
|
289 |
|
|
else
|
290 |
|
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rx_buf_reg_3 <= rx_buf_reg_3;
|
291 |
|
|
|
292 |
|
|
always @ (posedge clk_2048k)
|
293 |
|
|
if (load_rx_buf_4)
|
294 |
|
|
rx_buf_reg_4 <= rx_shift_reg_4;
|
295 |
|
|
else
|
296 |
|
|
rx_buf_reg_4 <= rx_buf_reg_4;
|
297 |
|
|
|
298 |
|
|
always @ (posedge clk_2048k)
|
299 |
|
|
if (load_rx_buf_5)
|
300 |
|
|
rx_buf_reg_5 <= rx_shift_reg_5;
|
301 |
|
|
else
|
302 |
|
|
rx_buf_reg_5 <= rx_buf_reg_5;
|
303 |
|
|
|
304 |
|
|
always @ (posedge clk_2048k)
|
305 |
|
|
if (load_rx_buf_6)
|
306 |
|
|
rx_buf_reg_6 <= rx_shift_reg_6;
|
307 |
|
|
else
|
308 |
|
|
rx_buf_reg_6 <= rx_buf_reg_6;
|
309 |
|
|
|
310 |
|
|
always @ (posedge clk_2048k)
|
311 |
|
|
if (load_rx_buf_7)
|
312 |
|
|
rx_buf_reg_7 <= rx_shift_reg_7;
|
313 |
|
|
else
|
314 |
|
|
rx_buf_reg_7 <= rx_buf_reg_7;
|
315 |
|
|
|
316 |
|
|
//=======================================================================================
|
317 |
|
|
//====================== PARALLEL TO SERIAL OUTPUT CONVERTIONS ==========================
|
318 |
|
|
|
319 |
|
|
assign tx_sr_load = (frame_cnt[3:0] == 4'hA) ? 1'b1 : 1'b0;
|
320 |
|
|
|
321 |
|
|
always @ (posedge clk_2048k)
|
322 |
|
|
if (tx_sr_load)
|
323 |
|
|
begin
|
324 |
|
|
tx_shift_reg_0 <= tx_buf_reg_0;
|
325 |
|
|
tx_shift_reg_1 <= tx_buf_reg_1;
|
326 |
|
|
tx_shift_reg_2 <= tx_buf_reg_2;
|
327 |
|
|
tx_shift_reg_3 <= tx_buf_reg_3;
|
328 |
|
|
tx_shift_reg_4 <= tx_buf_reg_4;
|
329 |
|
|
tx_shift_reg_5 <= tx_buf_reg_5;
|
330 |
|
|
tx_shift_reg_6 <= tx_buf_reg_6;
|
331 |
|
|
tx_shift_reg_7 <= tx_buf_reg_7;
|
332 |
|
|
end
|
333 |
|
|
else
|
334 |
|
|
begin
|
335 |
|
|
tx_shift_reg_0 <= {1'b0, tx_shift_reg_0[7:1]};
|
336 |
|
|
tx_shift_reg_1 <= {1'b0, tx_shift_reg_1[7:1]};
|
337 |
|
|
tx_shift_reg_2 <= {1'b0, tx_shift_reg_2[7:1]};
|
338 |
|
|
tx_shift_reg_3 <= {1'b0, tx_shift_reg_3[7:1]};
|
339 |
|
|
tx_shift_reg_4 <= {1'b0, tx_shift_reg_4[7:1]};
|
340 |
|
|
tx_shift_reg_5 <= {1'b0, tx_shift_reg_5[7:1]};
|
341 |
|
|
tx_shift_reg_6 <= {1'b0, tx_shift_reg_6[7:1]};
|
342 |
|
|
tx_shift_reg_7 <= {1'b0, tx_shift_reg_7[7:1]};
|
343 |
|
|
end
|
344 |
|
|
|
345 |
|
|
assign tx_stream[0] = tx_shift_reg_0[0];
|
346 |
|
|
assign tx_stream[1] = tx_shift_reg_1[0];
|
347 |
|
|
assign tx_stream[2] = tx_shift_reg_2[0];
|
348 |
|
|
assign tx_stream[3] = tx_shift_reg_3[0];
|
349 |
|
|
assign tx_stream[4] = tx_shift_reg_4[0];
|
350 |
|
|
assign tx_stream[5] = tx_shift_reg_5[0];
|
351 |
|
|
assign tx_stream[6] = tx_shift_reg_6[0];
|
352 |
|
|
assign tx_stream[7] = tx_shift_reg_7[0];
|
353 |
|
|
|
354 |
|
|
//=======================================================================================
|
355 |
|
|
//====================== Tx BUFFER LOAD =================================================
|
356 |
|
|
|
357 |
|
|
assign tx_buf_addr = frame_cnt[2:0] + 3'b110;
|
358 |
|
|
assign tx_buf_wen = ((frame_cnt[3:0] > 4'h1) & (frame_cnt[3:0] < 4'hA)) ? 1'b1 : 1'b0;
|
359 |
|
|
|
360 |
|
|
always @ (posedge clk_4096k)
|
361 |
|
|
case ({tx_buf_wen, tx_buf_addr})
|
362 |
|
|
4'h8 : tx_buf_reg_0 <= data_out_bus;
|
363 |
|
|
4'h9 : tx_buf_reg_1 <= data_out_bus;
|
364 |
|
|
4'hA : tx_buf_reg_2 <= data_out_bus;
|
365 |
|
|
4'hB : tx_buf_reg_3 <= data_out_bus;
|
366 |
|
|
4'hC : tx_buf_reg_4 <= data_out_bus;
|
367 |
|
|
4'hD : tx_buf_reg_5 <= data_out_bus;
|
368 |
|
|
4'hE : tx_buf_reg_6 <= data_out_bus;
|
369 |
|
|
4'hF : tx_buf_reg_7 <= data_out_bus;
|
370 |
|
|
endcase
|
371 |
|
|
|
372 |
|
|
//=======================================================================================
|
373 |
|
|
//====================== DATA MEMORY ADDRESS GENERATION =================================
|
374 |
|
|
|
375 |
|
|
assign d_mem_addr = {mem_page_sel, d_mem_high_addr, d_mem_low_addr};
|
376 |
|
|
|
377 |
|
|
assign d_mem_high_addr = d_mem_addr_cnt;
|
378 |
|
|
|
379 |
|
|
assign d_mem_low_addr = frame_cnt[2:1] + 2'b11;
|
380 |
|
|
|
381 |
|
|
always @ (posedge clk_2048k or negedge g_rst)
|
382 |
|
|
if (!g_rst)
|
383 |
|
|
mem_page_sel <= 0;
|
384 |
|
|
else
|
385 |
|
|
if (frame_8k)
|
386 |
|
|
mem_page_sel <= ~mem_page_sel;
|
387 |
|
|
else
|
388 |
|
|
mem_page_sel <= mem_page_sel;
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
always @ (posedge clk_2048k)
|
392 |
|
|
if (tx_sr_load & frame_8k)
|
393 |
|
|
d_mem_addr_cnt <= 5'h1F;
|
394 |
|
|
else
|
395 |
|
|
if (tx_sr_load)
|
396 |
|
|
d_mem_addr_cnt <= d_mem_addr_cnt + 1;
|
397 |
|
|
else
|
398 |
|
|
d_mem_addr_cnt <= d_mem_addr_cnt;
|
399 |
|
|
|
400 |
|
|
//=======================================================================================
|
401 |
|
|
//====================== CONNECTION MEMORY ADDRESS GENERATION ===========================
|
402 |
|
|
|
403 |
|
|
assign c_mem_addr = {c_mem_high_addr, c_mem_low_addr};
|
404 |
|
|
|
405 |
|
|
assign c_mem_high_addr = c_mem_addr_cnt;
|
406 |
|
|
|
407 |
|
|
assign c_mem_low_addr = frame_cnt[2:0];
|
408 |
|
|
|
409 |
|
|
always @ (posedge clk_2048k)
|
410 |
|
|
if (rx_buf_load & frame_8k)
|
411 |
|
|
c_mem_addr_cnt <= 5'h01;
|
412 |
|
|
else
|
413 |
|
|
if (rx_buf_load)
|
414 |
|
|
c_mem_addr_cnt <= c_mem_addr_cnt + 1;
|
415 |
|
|
else
|
416 |
|
|
c_mem_addr_cnt <= c_mem_addr_cnt;
|
417 |
|
|
|
418 |
|
|
//=======================================================================================
|
419 |
|
|
//====================== DATA MEMORY MODULE =============================================
|
420 |
|
|
|
421 |
|
|
always @ (d_mem_addr[1:0], rx_buf_reg_7, rx_buf_reg_6, rx_buf_reg_5, rx_buf_reg_4, rx_buf_reg_3, rx_buf_reg_2, rx_buf_reg_1, rx_buf_reg_0)
|
422 |
|
|
case (d_mem_addr[1:0])
|
423 |
|
|
2'b00 : data_in_bus = {rx_buf_reg_1, rx_buf_reg_0};
|
424 |
|
|
2'b01 : data_in_bus = {rx_buf_reg_3, rx_buf_reg_2};
|
425 |
|
|
2'b10 : data_in_bus = {rx_buf_reg_5, rx_buf_reg_4};
|
426 |
|
|
default : data_in_bus = {rx_buf_reg_7, rx_buf_reg_6};
|
427 |
|
|
endcase
|
428 |
|
|
|
429 |
|
|
assign cd_mem_addr = {~mem_page_sel, cd_data[7:0]};
|
430 |
|
|
assign data_wen = ((frame_cnt[3:0] > 4'h1) & (frame_cnt[3:0] < 4'hA)) ? 1'b1 : 1'b0;
|
431 |
|
|
assign cd_en = (frame_cnt[3:0] < 4'h8) ? 1'b1 : 1'b0;
|
432 |
|
|
|
433 |
|
|
RAMB4_S8_S16 d_mem (
|
434 |
|
|
.DOA (data_out_bus),
|
435 |
|
|
.DOB (),
|
436 |
|
|
.ADDRA (cd_mem_addr),
|
437 |
|
|
.ADDRB (d_mem_addr),
|
438 |
|
|
.CLKA (clk_4096k),
|
439 |
|
|
.CLKB (clk_2048k),
|
440 |
|
|
.DIA ({8{pd}}),
|
441 |
|
|
.DIB (data_in_bus),
|
442 |
|
|
.ENA (pu),
|
443 |
|
|
.ENB (data_wen),
|
444 |
|
|
.RSTA (~g_rst),
|
445 |
|
|
.RSTB (~g_rst),
|
446 |
|
|
.WEA (pd),
|
447 |
|
|
.WEB (pu),
|
448 |
|
|
.GSR (~g_rst)
|
449 |
|
|
);
|
450 |
|
|
|
451 |
|
|
//=======================================================================================
|
452 |
|
|
//====================== CONNECTION MEMORY MODULE =======================================
|
453 |
|
|
|
454 |
|
|
assign mpi_data_out = (mpi_cs & ~mpi_addr[8]) ? mpi_mem_bus_out[8:0] :
|
455 |
|
|
(mpi_cs & mpi_addr[8]) ? {7'h00, ctrl_out} : 9'hzzz;
|
456 |
|
|
|
457 |
|
|
assign mpi_mem_bus_in = {{7{pd}}, mpi_data_in};
|
458 |
|
|
assign ram_en = mpi_cs & ~mpi_addr[8];
|
459 |
|
|
|
460 |
|
|
RAMB4_S16_S16 c_mem (
|
461 |
|
|
.DOA (cd_data),
|
462 |
|
|
.DOB (mpi_mem_bus_out),
|
463 |
|
|
.ADDRA (c_mem_addr),
|
464 |
|
|
.ADDRB (mpi_addr[7:0]),
|
465 |
|
|
.CLKA (clk_4096k),
|
466 |
|
|
.CLKB (mpi_clk),
|
467 |
|
|
.DIA ({16{pd}}),
|
468 |
|
|
.DIB (mpi_mem_bus_in),
|
469 |
|
|
.ENA (cd_en),
|
470 |
|
|
.ENB (ram_en),
|
471 |
|
|
.RSTA (~g_rst),
|
472 |
|
|
.RSTB (~g_rst),
|
473 |
|
|
.WEA (pd),
|
474 |
|
|
.WEB (~mpi_rw),
|
475 |
|
|
.GSR (~g_rst)
|
476 |
|
|
);
|
477 |
|
|
|
478 |
|
|
//=======================================================================================
|
479 |
|
|
//====================== TO CONTROLL REGISTER ACCESS UNIT ===============================
|
480 |
|
|
|
481 |
|
|
assign ctrl_in = mpi_data_in[1:0];
|
482 |
|
|
|
483 |
|
|
always @ (posedge mpi_clk)
|
484 |
|
|
case ({mpi_rw, mpi_cs, mpi_addr[8], mpi_addr[3:0]})
|
485 |
|
|
7'b0110000 : frame_delay_buf_0 <= ctrl_in;
|
486 |
|
|
7'b0110001 : frame_delay_buf_1 <= ctrl_in;
|
487 |
|
|
7'b0110010 : frame_delay_buf_2 <= ctrl_in;
|
488 |
|
|
7'b0110011 : frame_delay_buf_3 <= ctrl_in;
|
489 |
|
|
7'b0110100 : frame_delay_buf_4 <= ctrl_in;
|
490 |
|
|
7'b0110101 : frame_delay_buf_5 <= ctrl_in;
|
491 |
|
|
7'b0110110 : frame_delay_buf_6 <= ctrl_in;
|
492 |
|
|
7'b0110111 : frame_delay_buf_7 <= ctrl_in;
|
493 |
|
|
endcase
|
494 |
|
|
|
495 |
|
|
always @ (posedge mpi_clk)
|
496 |
|
|
case ({mpi_cs, mpi_addr[8], mpi_addr[3:0]})
|
497 |
|
|
6'b110000 : ctrl_out_reg <= frame_delay_buf_0;
|
498 |
|
|
6'b110001 : ctrl_out_reg <= frame_delay_buf_1;
|
499 |
|
|
6'b110010 : ctrl_out_reg <= frame_delay_buf_2;
|
500 |
|
|
6'b110011 : ctrl_out_reg <= frame_delay_buf_3;
|
501 |
|
|
6'b110100 : ctrl_out_reg <= frame_delay_buf_4;
|
502 |
|
|
6'b110101 : ctrl_out_reg <= frame_delay_buf_5;
|
503 |
|
|
6'b110110 : ctrl_out_reg <= frame_delay_buf_6;
|
504 |
|
|
6'b110111 : ctrl_out_reg <= frame_delay_buf_7;
|
505 |
|
|
endcase
|
506 |
|
|
|
507 |
|
|
assign ctrl_out = ctrl_out_reg;
|
508 |
|
|
|
509 |
|
|
//=======================================================================================
|
510 |
|
|
//====================== ================================================================
|
511 |
|
|
|
512 |
|
|
//=======================================================================================
|
513 |
|
|
|
514 |
|
|
endmodule
|