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plutonium |
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-- Author: Martin Kumm
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-- Contact: kumm@uni-kassel.de
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-- License: LGPL
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-- Date: 03.04.2013
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-- Compatibility: Altera Arria I,II,V and Stratix II-V FPGAs
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--
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-- Description:
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-- Implementation of a ternary adder including subtraction of up to two inputs.
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-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of
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-- 'input_word_size' while the output has a word size of input_word_size+2.
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--
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-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true.
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-- Signed operation is activated by using the 'is_signed' generic.
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-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z'
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-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources.
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---------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ternary_adder is
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generic(
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input_word_size : integer := 10;
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subtract_y : boolean := false;
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subtract_z : boolean := false;
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use_output_ff : boolean := true
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);
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port(
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clk_i : in std_logic;
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rst_i : in std_logic;
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x_i : in std_logic_vector((input_word_size - 1) downto 0);
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y_i : in std_logic_vector((input_word_size - 1) downto 0);
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z_i : in std_logic_vector((input_word_size - 1) downto 0);
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sum_o : out std_logic_vector((input_word_size + 1) downto 0)
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);
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end entity;
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architecture behavior of ternary_adder is
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signal sum : std_logic_vector(input_word_size + 1 downto 0);
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signal sum_tmp : std_logic_vector(input_word_size+3 downto 0);
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signal x_i_ext : std_logic_vector(input_word_size+1 downto 0);
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signal y_i_ext : std_logic_vector(input_word_size+1 downto 0);
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signal z_i_ext : std_logic_vector(input_word_size+1 downto 0);
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begin
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add_sub_case1_gen: if subtract_y = false and subtract_z = false generate
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sum <= std_logic_vector(resize(signed(x_i),input_word_size+2) + resize(signed(y_i),input_word_size+2) + resize(signed(z_i),input_word_size+2));
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end generate;
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add_sub_case2_gen: if subtract_y = false and subtract_z = true generate
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x_i_ext <= x_i & "00";
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y_i_ext <= y_i & "10";
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z_i_ext <= (not z_i) & "10";
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sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4));
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sum <= sum_tmp(input_word_size+3 downto 2);
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end generate;
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add_sub_case3_gen: if subtract_y = true and subtract_z = false generate
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x_i_ext <= x_i & "00";
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y_i_ext <= (not y_i) & "10";
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z_i_ext <= z_i & "10";
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sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4));
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sum <= sum_tmp(input_word_size+3 downto 2);
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end generate;
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add_sub_case4_gen: if subtract_y = true and subtract_z = true generate
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x_i_ext <= x_i & "11";
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y_i_ext <= (not y_i) & "11";
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z_i_ext <= (not z_i) & "11";
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sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4));
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sum <= sum_tmp(input_word_size+3 downto 2);
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end generate;
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use_output_ff_gen: if use_output_ff = true generate
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process(clk_i,rst_i)
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begin
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if rst_i = '1' then
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sum_o <= (others => '0');
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elsif clk_i'event and clk_i='1' then
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sum_o <= sum;
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end if;
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end process;
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end generate;
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dont_use_output_ff_gen: if use_output_ff = false generate
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sum_o <= sum;
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end generate;
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end architecture;
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