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///////////////////////////////////////////////////////////////////////////////////////////////////
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// //
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// file name: memstate2.v //
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// description: memory opertions for z80 //
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// project: wb_z80 //
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// //
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// Author: B.J. Porcella //
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// e-mail: bporcella@sbcglobal.net //
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// //
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// //
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// //
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2000-2002 B.J. Porcella //
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// Real Time Solutions //
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// //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //
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// POSSIBILITY OF SUCH DAMAGE. //
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// //
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//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0
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// The memory state controller controls the wb bus, and provides address sequencing.
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// Insructions are fetched in order (using PC) until the istate machine indicates that
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// a complete instruction is in the first pipline stage (ir1). In general, operands are being
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// fetched (stored) to satisfy ir1 while concurrently instructions are being executed from ir2.
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// this situation can result in a number of potential hazards. As an example, if the ir2
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// instruction changes the flag register and the ir1 instruction is a conditional jump,
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// a hazard is generated by the hazard logic, and execution of the ir1 operation is delayed
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// until the completion of the flag update.
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//
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// Reset starts execution at 0.
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// The PC and SP are described in this file. modifications to other index registers -
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// HL IX and IY are computed here --
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// For the block moves address updates are computed here -- and commanded here.
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// Strobes for the second address update are generally co-incident with count updates, but
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// we provide seperate strobe update lines for clarity.
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//
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// BASIC ARCHITECTURE OF THIS FILE pc and sp not shown, but are inputs to src mux.
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// _____ and may be updated from adder output.
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// | |
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// | | pc-1 register is required to implement relative jumps.
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// | |
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// _____ |lit | |\
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// | | | | | \
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// | | |src2 | | \ _____ _____
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// | | | |----->| | | | | |
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// |src | |_____| |adder|------->| | | |
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// |mux | | | | | | |
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// | |------------------->| / |2/1 |------->|wb |
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// | | | | / |mux | |adr |
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// |_____| | |/ | | | |
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// ------------------->| | | |
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// |_____| |_____|
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//
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//
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//
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//
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// Operand Stores:
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// At first cut, I thought I'ld execute operand stores immediately from the memory sequencer
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// (essentially before ir2 got the store data). While this might be modestly faster in
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// systems that take multiple clocks to complete a memory store, On consideration, I decided
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// to forgo the extra speed for conceptual simplicity.... execute operand stores on op_ph1,
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// and let the inst_exec engine suply the operand.
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//
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// On second thought, above is not only wastful of time, but also inconsistent with the overall
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// schems of things - and so somewhat more complex. If we simply execute the OS from ir1,
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// There is less state to contdend with, as well as extra speed.
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//
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// Block Moves fundamentally execute from ir2. We initiate the first operand fetch from ir1.
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//
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// 3/18/2004 Second time through. In impleenting the execution logic it became clear that
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// there were "minor" problems with the handling of the DD and FD prefix insts (especially
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// DDCD and FDCB --- collectively called PFxCB below. On review, I had to question the
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// value of "breaking up" the ir0 execution engine between the istate sequencer and the
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// memstate sequencer. While I dislike state sequencers of much more than 16 states --
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// the interaction between these sequencers was becomming harder to track than a single
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// state macine. Thus - this file is getting re-worked. I will call it memstate2 (at least
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// for awhile) as I wish to keep the old file around. I want to show (in the state machine
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// logic) what the next memory operation is.... guess the best method consistent with my
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// documentation practices is to define a register (mem_op) = { if, wb_we, wb_cyc }.
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// This will require auxillary logic for computing the address --- but most of the decodes
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// required will be there anyway.
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// On further reflection, I think I will bite-the-bullet and use an always to define next_state.
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// I don't like to use always to define wires, but I also want to dicument the setting of
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// exec_ir2 in the same place - that is 3 different things.
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//
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// Hazards:
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// There are 2 kinds of hazards: mem_hazard => we are storing into the next instruction location
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// reg_hazard => we are modifying a register (ir2) that we are using
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// here (ir1)
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// In the former case, we throw out the instruction that arrives on the next tick, and restart the
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// instruction pipeline, In the latter case, we simply wait a tick for the ir2 operaton to
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// complete before starting the ir1 operation
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//
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mihal |
// $Id: memstate2.v,v 1.6 2004-04-19 08:22:34 mihal Exp $
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//
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// $Date: 2004-04-19 08:22:34 $
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// $Revision: 1.6 $
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// $Author: mihal $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2004/04/19 08:10:36 mihal
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// testing lint
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//
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// Revision 1.4 2004/04/19 07:52:39 mihal
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// testing lint
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//
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// Revision 1.3 2004/04/19 07:28:58 mihal
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// testing lint
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//
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// Revision 1.2 2004/04/17 08:02:00 mihal
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// testing lint
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//
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// Revision 1.1 2004/04/17 07:39:21 mihal
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// testing lint
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//
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// Revision 1.4 2004/04/16 18:16:57 bporcella
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// try lint
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//
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// Revision 1.3 2004/04/16 17:06:54 bporcella
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// no code change - added a comment and test lint
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//
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// Revision 1.2 2004/04/16 16:21:04 bporcella
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// no code change - added a comment and test lint
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//
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// Revision 1.1.1.1 2004/04/13 23:50:19 bporcella
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// import first files
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//
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//
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//
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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mihal |
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mihal |
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, add_out,
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exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
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upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
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beq0, ceq0,
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ar, fr, br, cr, dr, er, hr, lr,
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ixr, iyr,
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wb_dat_i, wb_ack, clk, rst,
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wb_int_rq,
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add16
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);
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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// mod only to checkout lint
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// mod again for lint check -- first check pretty wierd
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// 3rd lint try
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output [15:0] wb_adr;
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output wb_we;
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output wb_cyc;
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output wb_stb;
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output wb_lock; // bit set and clear insts should be atomic - could matter sometime
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output wb_tga_io;
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output wb_dat_o; // from nn
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output [15:0] add_out; // output of adder (may not wb_adr)
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output exec_ir2;
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output [9:0] ir1, ir2;
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output ir1dd, ir2dd;
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output ir1fd, ir2fd;
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output [15:0] nn;
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output [15:0] sp;
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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input upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;
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input beq0, ceq0;
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input [7:0] ar, fr, br, cr, dr, er, hr, lr;
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input [15:0] ixr, iyr;
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input [7:0] wb_dat_i;
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input wb_ack, clk, rst;
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input wb_int_rq;
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input [15:0] add16; // ir2 execution engine output for sp updates
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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`include "opcodes.v" // states of the main memory sequencer
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parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to
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TAG_INT = 2'b10; // document this.
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// 12na
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parameter IPIPE_NOP = 4'b0000,
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IPIPE_A2 = 4'b0001,
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IPIPE_ENN = 4'b0010,
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IPIPE_ENNA2 = 4'b0011,
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IPIPE_EN2 = 4'b0100,
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IPIPE_EN2A2 = 4'b0101,
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IPIPE_ENNEN2 = 4'b0110,
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IPIPE_ENNEN2A2 = 4'b0111,
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IPIPE_EN1 = 4'b1000,
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IPIPE_EN1A2 = 4'b1001,
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IPIPE_BOGUS = 4'b1010, // no reason (yet) to load both n and ir1
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IPIPE_BOUS2 = 4'b1011,
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IPIPE_EN12 = 4'b1100,
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IPIPE_EN12A2 = 4'b1101,
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IPIPE_BOGUS3 = 4'b1110,
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IPIPE_BOGUS4 = 4'b1111;
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// well at first cut I tried to make this 2 state macines both less than 16 states.
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// this is 56 states at first cut. Assignemnt is subject to change.
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// ------ mem state decoder state machine states --------------------------------
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parameter DEC_IDLE = 6'h00,
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DEC_HALT = 6'h01,
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DEC_IF1 = 6'h02,
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DEC_IF2 = 6'h03,
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DEC_IF2A = 6'h04,
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DEC_EXEC = 6'h05,
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DEC_CB = 6'h06,
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DEC_DDFD = 6'h07,
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DEC_ED = 6'h08,
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DEC_EDNN1 = 6'h09,
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DEC_EDNN2 = 6'h0a,
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DEC_EDRD1 = 6'h0b,
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DEC_EDRD2 = 6'h0c,
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DEC_EDWR = 6'h0d,
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DEC_EDBCP1 = 6'h0e,
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DEC_EDBCP2 = 6'h0f,
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DEC_EDBCP3 = 6'h10,
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DEC_EDBIN1 = 6'h11,
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DEC_EDBIN2 = 6'h12,
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DEC_EDBIN3 = 6'h13,
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DEC_EDBOUT1 = 6'h14,
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DEC_EDBOUT2 = 6'h15,
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DEC_EDBOUT3 = 6'h16,
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DEC_EDBMV1 = 6'h17,
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DEC_EDBMV2 = 6'h18,
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DEC_EDBMV3 = 6'h19,
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DEC_N = 6'h1a,
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DEC_NIN = 6'h1b,
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DEC_NN = 6'h1c,
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DEC_NNCALL1 = 6'h1d,
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DEC_NNCALL2 = 6'h1e,
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DEC_NNOS1 = 6'h1f,
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DEC_NNOS2 = 6'h20,
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DEC_NNOS3 = 6'h21,
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DEC_NNOF1 = 6'h22,
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DEC_NNOF2 = 6'h23,
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DEC_NNOF3 = 6'h24,
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DEC_NNOF4 = 6'h25,
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DEC_DDOS = 6'h26,
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DEC_DDOF = 6'h27,
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DEC_OF = 6'h28,
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DEC_POP = 6'h29,
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DEC_PUSH = 6'h2a,
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DEC_RMW = 6'h2b,
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DEC_RMW2 = 6'h2c,
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DEC_CBM = 6'h2d,
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DEC_PFxCB = 6'h2e,
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DEC_PFxCB2 = 6'h2f,
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DEC_PFxCB3 = 6'h30,
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DEC_PFxCB4 = 6'h31,
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DEC_INT1 = 6'h32,
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DEC_INT2 = 6'h33,
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DEC_INT3 = 6'h34,
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DEC_INT4 = 6'h35,
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DEC_INT5 = 6'h36,
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DEC_RET = 6'h37,
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DEC_NNJMP = 6'h38,
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DEC_RET2 = 6'h39 ;
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// initial decode assignemnts. These assignemens are made to wires on an initial decode
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// to help document next state transitions
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parameter I1_CB = 4'h0,
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I1_DDFD = 4'h1,
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I1_ED = 4'h2,
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I1_JMP = 4'h3,
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I1_N = 4'h4,
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I1_NN = 4'h5,
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I1_OF = 4'h6,
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I1_OS = 4'h7,
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I1_POP = 4'h8,
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I1_PUSH = 4'h9,
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I1_RET = 4'ha,
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I1_RMW = 4'hb,
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I1_RST = 4'hc,
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I1_R2R = 4'hd ;
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// A note here on the choices of mnemonics..... in general, the target registers of
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// memory ops are specified by an instruction register (ir1 for stores ir2 for loads).
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// so Menomics in general are specifying the address source. However, there are exceptions.
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//
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parameter MEM_NOP = 5'h00,
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MEM_IFPP1 = 5'h01,
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MEM_OS1 = 5'h02, // only invoked on I1 OS multiple address sources and data sources
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|
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MEM_OF1 = 5'h03, // Address from HL unless LD A,(BC) or LD A,(DE) (used for rmw)
|
316 |
|
|
MEM_OFSP = 5'h04, // works for both POP and RET
|
317 |
|
|
MEM_OSSP = 5'h05, // if DEC_EXEC op from ir1 else msb nn (implies we store from lsb nn)
|
318 |
|
|
// used in CALL also.
|
319 |
|
|
MEM_OFIXpD = 5'h06, // used for prefix op fetches - all single bytes
|
320 |
|
|
MEM_OSIXpD = 5'h07, // data source is same as MEM_OS1
|
321 |
|
|
MEM_OSADR = 5'h08, // used (at lesat) for prefixed rmw -- perhaps others.
|
322 |
|
|
|
323 |
|
|
MEM_CALL = 5'h09, // pc<=nn, nn<=pc, wb_adr<=sp OS
|
324 |
|
|
MEM_OSNN = 5'h0a, // if DEC_EXEC op from ir1 else msb nn
|
325 |
|
|
MEM_OFNN = 5'h0b, // striaghtfoward
|
326 |
|
|
MEM_OFADRP1 = 5'h0c, // used (at least) when double ops above
|
327 |
|
|
MEM_OSADRP1 = 5'h0d, // "" "" ""
|
328 |
|
|
|
329 |
|
|
MEM_IFRST = 5'h0e, // special address transfer
|
330 |
|
|
MEM_IFREL_N = 5'h0f, // special address transfer for jmp rel
|
331 |
|
|
MEM_JMPHL = 5'h10, // another special jump transfer
|
332 |
|
|
MEM_IFNN = 5'h11, // used by call and return
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
MEM_OFHL_PM = 5'h12, // special block move ops
|
336 |
|
|
MEM_OSHL_PM = 5'h13, // special block move ops
|
337 |
|
|
MEM_OSDE_PM = 5'h14, // special block move ops
|
338 |
|
|
|
339 |
|
|
MEM_IOF_C = 5'h15, // special i/o ops
|
340 |
|
|
MEM_IOS_C = 5'h16, // operand is ar
|
341 |
|
|
MEM_IOF_N = 5'h17,
|
342 |
|
|
MEM_IOS_N = 5'h18,
|
343 |
|
|
MEM_OS_HL_N = 5'h19,
|
344 |
|
|
|
345 |
|
|
MEM_OSSP_PCM2 = 5'h1a, // int code (call
|
346 |
|
|
MEM_OSSP_P = 5'h1b, //
|
347 |
|
|
MEM_INTA = 5'h1c,
|
348 |
|
|
MEM_IFINT = 5'h1d,
|
349 |
|
|
MEM_DECPC = 5'h1e ;
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
wire use_sp;
|
363 |
|
|
wire use_pc;
|
364 |
|
|
wire use_hl;
|
365 |
|
|
wire use_de;
|
366 |
|
|
wire use_bc;
|
367 |
|
|
wire use_flags;
|
368 |
|
|
wire cb_mem;
|
369 |
|
|
wire br_test8t; // branch test true (8 test field)
|
370 |
|
|
wire br_test4t; // branch test true (4 test field)
|
371 |
|
|
|
372 |
|
|
wire ofos;
|
373 |
|
|
wire any_os; // most terms above only valid on mem_exec this includes all stores
|
374 |
|
|
wire wb_rdy_nhz;
|
375 |
|
|
wire dec_blk_inc;
|
376 |
|
|
wire we_next;
|
377 |
|
|
wire hazard;
|
378 |
|
|
wire wb_int;
|
379 |
|
|
wire [15:0] hl, de, bc;
|
380 |
|
|
wire mem_exec_dec;
|
381 |
|
|
|
382 |
|
|
wire use_a ;
|
383 |
|
|
wire use_b ;
|
384 |
|
|
wire use_c ;
|
385 |
|
|
wire use_d ;
|
386 |
|
|
wire use_e ;
|
387 |
|
|
wire use_h ;
|
388 |
|
|
wire use_l ;
|
389 |
|
|
// don't forget that as 1r1 is executed it is transferred to ir2. Anything I need to know
|
390 |
|
|
// about subsequent operations must be stored.
|
391 |
|
|
// 6 5 4 15
|
392 |
|
|
// assign {next_dec_state, next_mem_state, next_pipe_state} = next_state;
|
393 |
|
|
wire [5:0] next_dec_state;
|
394 |
|
|
wire [4:0] next_mem_state;
|
395 |
|
|
wire [3:0] next_pipe_state;
|
396 |
|
|
wire ed_dbl_rd;
|
397 |
|
|
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0
|
398 |
|
|
|
399 |
|
|
reg [15:0] pc;
|
400 |
|
|
reg [15:0] sp;
|
401 |
|
|
reg [15:0] wb_adr;
|
402 |
|
|
reg wb_we;
|
403 |
|
|
reg wb_cyc;
|
404 |
|
|
reg wb_stb;
|
405 |
|
|
reg wb_lock;
|
406 |
|
|
reg wb_tga_io;
|
407 |
|
|
|
408 |
|
|
reg blk_inc_flg;
|
409 |
|
|
reg [9:0] ir1, ir2;
|
410 |
|
|
reg ir1dd, ir2dd;
|
411 |
|
|
reg ir1fd, ir2fd;
|
412 |
|
|
reg [15:0] nn;
|
413 |
|
|
|
414 |
|
|
reg [15:0] next_state; // a wire assigned in an alowys loop.
|
415 |
|
|
|
416 |
|
|
reg [5:0] dec_state; // the register set each clock from next_dec_state;
|
417 |
|
|
|
418 |
|
|
reg of16_reg, os16_reg, rmw8_reg, call_reg, ret_reg, ioi;
|
419 |
|
|
reg push_reg;
|
420 |
|
|
reg pop_reg;
|
421 |
|
|
reg inst_haz;
|
422 |
|
|
reg exec_ir2;
|
423 |
|
|
reg blk_rpt_flg;
|
424 |
|
|
reg blk_io_flg;
|
425 |
|
|
reg flag_os1;
|
426 |
|
|
reg int_en, en_int_next;
|
427 |
|
|
reg wb_irq_sync;
|
428 |
|
|
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
|
429 |
|
|
//
|
430 |
|
|
// ir is 10 bits most significant codes ir1[9:8] = { EDgrp, CBgrp } DDgrp and FDgrp are modifiers
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
assign wb_dat_o = nn[15:8];
|
434 |
|
|
|
435 |
|
|
wire sf, zf, f5f, hf, f3f, pvf, nf, cf;
|
436 |
|
|
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr;
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
assign hl = {hr, lr};
|
440 |
|
|
assign de = {dr, er};
|
441 |
|
|
assign bc = {br, cr};
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
// this "groups" the instructions to determine first memory operation
|
445 |
|
|
|
446 |
|
|
parameter I1DCNT = 4; // parameter used below simply to make possible change easier.
|
447 |
|
|
assign mem_exec_dec =
|
448 |
|
|
{I1DCNT {CBgrp == ir1}} & I1_CB |// CBgrp is rotates and bi
|
449 |
|
|
{I1DCNT {DDgrp == ir1}} & I1_DDFD|// DDgrp
|
450 |
|
|
{I1DCNT {FDgrp == ir1}} & I1_DDFD|// FDgrp FD
|
451 |
|
|
{I1DCNT {EDgrp == ir1}} & I1_ED |// EDgrp ED
|
452 |
|
|
{I1DCNT {JPsHL == ir1}} & I1_JMP |// JP HL ; E9 // doc
|
453 |
|
|
{I1DCNT {ADCsA_N == ir1}} & I1_N |// ADC A,N ; CE XX
|
454 |
|
|
{I1DCNT {ADDsA_N == ir1}} & I1_N |// ADD A,N ; C6 XX
|
455 |
|
|
{I1DCNT {ANDsN == ir1}} & I1_N |// AND N ; E6 XX
|
456 |
|
|
{I1DCNT {CPsN == ir1}} & I1_N |// CP N ; FE XX
|
457 |
|
|
{I1DCNT {INsA_6N7 == ir1}} & I1_N |// IN A,(N) ; DB XX
|
458 |
|
|
{I1DCNT {JRs$t2 == ir1}} & I1_N |// JR $+2 ; 18 XX
|
459 |
|
|
{I1DCNT {JRsC_$t2 == ir1}} & I1_N |// JR C,$+2 ; 38 XX
|
460 |
|
|
{I1DCNT {JRsNC_$t2 == ir1}} & I1_N |// JR NC,$+2 ; 30 XX
|
461 |
|
|
{I1DCNT {JRsZ_$t2 == ir1}} & I1_N |// JR Z,$+2 ; 28 XX
|
462 |
|
|
{I1DCNT {JRsNZ_$t2 == ir1}} & I1_N |// JR NZ,$+2 ; 20 XX
|
463 |
|
|
{I1DCNT {LDs6HL7_N == ir1}} & I1_N |// LD (HL),N ; 36 XX
|
464 |
|
|
{I1DCNT {LDsA_N == ir1}} & I1_N |// LD A,N ; 3E XX
|
465 |
|
|
{I1DCNT {LDsB_N == ir1}} & I1_N |// LD B,N ; 06 XX
|
466 |
|
|
{I1DCNT {LDsC_N == ir1}} & I1_N |// LD C,N ; 0E XX
|
467 |
|
|
{I1DCNT {LDsD_N == ir1}} & I1_N |// LD D,N ; 16 XX
|
468 |
|
|
{I1DCNT {LDsE_N == ir1}} & I1_N |// LD E,N ; 1E XX
|
469 |
|
|
{I1DCNT {LDsH_N == ir1}} & I1_N |// LD H,N ; 26 XX
|
470 |
|
|
{I1DCNT {LDsL_N == ir1}} & I1_N |// LD L,N ; 2E XX
|
471 |
|
|
{I1DCNT {ORsN == ir1}} & I1_N |// OR N ; F6 XX
|
472 |
|
|
{I1DCNT {OUTs6N7_A == ir1}} & I1_N |// OUT (N),A ; D3 XX
|
473 |
|
|
{I1DCNT {SBCsA_N == ir1}} & I1_N |// SBC A,N ; DE XX
|
474 |
|
|
{I1DCNT {SUBsN == ir1}} & I1_N |// SUB N ; D6 XX
|
475 |
|
|
{I1DCNT {XORsN == ir1}} & I1_N |// XOR N ; EE XX
|
476 |
|
|
{I1DCNT {CALLsC_NN == ir1}} & I1_NN |// CALL C,NN ; DC XX XX
|
477 |
|
|
{I1DCNT {CALLsNC_NN == ir1}} & I1_NN |// CALL NC,NN ; D4 XX XX
|
478 |
|
|
{I1DCNT {CALLsNN == ir1}} & I1_NN |// CALL NN ; CD XX XX
|
479 |
|
|
{I1DCNT {CALLsNZ_NN == ir1}} & I1_NN |// CALL NZ,NN ; C4 XX XX
|
480 |
|
|
{I1DCNT {CALLsPE_NN == ir1}} & I1_NN |// CALL PE,NN ; EC XX XX
|
481 |
|
|
{I1DCNT {CALLsPO_NN == ir1}} & I1_NN |// CALL PO,NN ; E4 XX XX
|
482 |
|
|
{I1DCNT {CALLsP_NN == ir1}} & I1_NN |// CALL P,NN ; F4 XX XX
|
483 |
|
|
{I1DCNT {CALLsZ_NN == ir1}} & I1_NN |// CALL Z,NN ; CC XX XX
|
484 |
|
|
{I1DCNT {CALLsM_NN == ir1}} & I1_NN |// CALL M,NN ; FC XX XX
|
485 |
|
|
{I1DCNT {JP == ir1}} & I1_NN |// JP ; C3 XX XX
|
486 |
|
|
{I1DCNT {JPsC == ir1}} & I1_NN |// JP C ; DA XX XX
|
487 |
|
|
{I1DCNT {JPsM == ir1}} & I1_NN |// JP M, ; FA XX XX
|
488 |
|
|
{I1DCNT {JPsNC == ir1}} & I1_NN |// JP NC, ; D2 XX XX
|
489 |
|
|
{I1DCNT {JPsNZ == ir1}} & I1_NN |// JP NZ ; C2 XX XX
|
490 |
|
|
{I1DCNT {JPsP == ir1}} & I1_NN |// JP P ; F2 XX XX
|
491 |
|
|
{I1DCNT {JPsPE == ir1}} & I1_NN |// JP PE, ; EA XX XX
|
492 |
|
|
{I1DCNT {JPsPO == ir1}} & I1_NN |// JP PO ; E2 XX XX
|
493 |
|
|
{I1DCNT {JPsZ == ir1}} & I1_NN |// JP Z ; CA XX XX
|
494 |
|
|
{I1DCNT {LDs6NN7_A == ir1}} & I1_NN |// LD (NN),A ; 32 XX XX
|
495 |
|
|
{I1DCNT {LDs6NN7_HL == ir1}} & I1_NN |// LD (NN),HL ; 22 XX XX
|
496 |
|
|
{I1DCNT {LDsA_6NN7 == ir1}} & I1_NN |// LD A,(NN) ; 3A XX XX
|
497 |
|
|
{I1DCNT {LDsBC_NN == ir1}} & I1_NN |// LD BC,NN ; 01 XX XX
|
498 |
|
|
{I1DCNT {LDsDE_NN == ir1}} & I1_NN |// LD DE,NN ; 11 XX XX
|
499 |
|
|
{I1DCNT {LDsHL_6NN7 == ir1}} & I1_NN |// LD HL,(NN) ; 2A XX XX
|
500 |
|
|
{I1DCNT {LDsHL_NN == ir1}} & I1_NN |// LD HL,NN ; 21 XX XX
|
501 |
|
|
{I1DCNT {LDsSP_NN == ir1}} & I1_NN |// LD SP,NN ; 31 XX XX
|
502 |
|
|
{I1DCNT {ADCsA_6HL7 == ir1}} & I1_OF |// ADC A,(HL) ; 8E
|
503 |
|
|
{I1DCNT {ADDsA_6HL7 == ir1}} & I1_OF |// ADD A,(HL) ; 86
|
504 |
|
|
{I1DCNT {ANDs6HL7 == ir1}} & I1_OF |// AND (HL) ; A6
|
505 |
|
|
{I1DCNT {CPs6HL7 == ir1}} & I1_OF |// CP (HL) ; BE
|
506 |
|
|
{I1DCNT {LDsA_6BC7 == ir1}} & I1_OF |// LD A,(BC) ; 0A
|
507 |
|
|
{I1DCNT {LDsA_6DE7 == ir1}} & I1_OF |// LD A,(DE) ; 1A
|
508 |
|
|
{I1DCNT {LDsA_6HL7 == ir1}} & I1_OF |// LD A,(HL) ; 7E
|
509 |
|
|
{I1DCNT {LDsB_6HL7 == ir1}} & I1_OF |// LD B,(HL) ; 46
|
510 |
|
|
{I1DCNT {LDsC_6HL7 == ir1}} & I1_OF |// LD C,(HL) ; 4E
|
511 |
|
|
{I1DCNT {LDsD_6HL7 == ir1}} & I1_OF |// LD D,(HL) ; 56
|
512 |
|
|
{I1DCNT {LDsE_6HL7 == ir1}} & I1_OF |// LD E,(HL) ; 5E
|
513 |
|
|
{I1DCNT {LDsH_6HL7 == ir1}} & I1_OF |// LD H,(HL) ; 66
|
514 |
|
|
{I1DCNT {LDsL_6HL7 == ir1}} & I1_OF |// LD L,(HL) ; 6E
|
515 |
|
|
{I1DCNT {ORs6HL7 == ir1}} & I1_OF |// OR (HL) ; B6
|
516 |
|
|
{I1DCNT {SBCs6HL7 == ir1}} & I1_OF |// SBC (HL) ; 9E
|
517 |
|
|
{I1DCNT {SUBs6HL7 == ir1}} & I1_OF |// SUB (HL) ; 96
|
518 |
|
|
{I1DCNT {XORs6HL7 == ir1}} & I1_OF |// XOR (HL) ; AE
|
519 |
|
|
{I1DCNT {LDs6BC7_A == ir1}} & I1_OS |// LD (BC),A ; 02
|
520 |
|
|
{I1DCNT {LDs6DE7_A == ir1}} & I1_OS |// LD (DE),A ; 12
|
521 |
|
|
{I1DCNT {LDs6HL7_A == ir1}} & I1_OS |// LD (HL),A ; 77
|
522 |
|
|
{I1DCNT {LDs6HL7_B == ir1}} & I1_OS |// LD (HL),B ; 70
|
523 |
|
|
{I1DCNT {LDs6HL7_C == ir1}} & I1_OS |// LD (HL),C ; 71
|
524 |
|
|
{I1DCNT {LDs6HL7_D == ir1}} & I1_OS |// LD (HL),D ; 72
|
525 |
|
|
{I1DCNT {LDs6HL7_E == ir1}} & I1_OS |// LD (HL),E ; 73
|
526 |
|
|
{I1DCNT {LDs6HL7_H == ir1}} & I1_OS |// LD (HL),H ; 74
|
527 |
|
|
{I1DCNT {LDs6HL7_L == ir1}} & I1_OS |// LD (HL),L ; 75
|
528 |
|
|
{I1DCNT {POPsAF == ir1}} & I1_POP |// POP AF ; F1
|
529 |
|
|
{I1DCNT {POPsBC == ir1}} & I1_POP |// POP BC ; C1
|
530 |
|
|
{I1DCNT {POPsDE == ir1}} & I1_POP |// POP DE ; D1
|
531 |
|
|
{I1DCNT {POPsHL == ir1}} & I1_POP |// POP HL ; E1
|
532 |
|
|
{I1DCNT {PUSHsAF == ir1}} & I1_PUSH|// PUSH AF ; F5
|
533 |
|
|
{I1DCNT {PUSHsBC == ir1}} & I1_PUSH|// PUSH BC ; C5
|
534 |
|
|
{I1DCNT {PUSHsDE == ir1}} & I1_PUSH|// PUSH DE ; D5
|
535 |
|
|
{I1DCNT {PUSHsHL == ir1}} & I1_PUSH|// PUSH HL ; E5
|
536 |
|
|
{I1DCNT {ADCsA_A == ir1}} & I1_R2R |// ADC A,A ; 8F
|
537 |
|
|
{I1DCNT {ADCsA_B == ir1}} & I1_R2R |// ADC A,B ; 88
|
538 |
|
|
{I1DCNT {ADCsA_C == ir1}} & I1_R2R |// ADC A,C ; 89
|
539 |
|
|
{I1DCNT {ADCsA_D == ir1}} & I1_R2R |// ADC A,D ; 8A
|
540 |
|
|
{I1DCNT {ADCsA_E == ir1}} & I1_R2R |// ADC A,E ; 8B
|
541 |
|
|
{I1DCNT {ADCsA_H == ir1}} & I1_R2R |// ADC A,H ; 8C
|
542 |
|
|
{I1DCNT {ADCsA_L == ir1}} & I1_R2R |// ADC A,L ; 8D
|
543 |
|
|
{I1DCNT {ADDsA_A == ir1}} & I1_R2R |// ADD A,A ; 87
|
544 |
|
|
{I1DCNT {ADDsA_B == ir1}} & I1_R2R |// ADD A,B ; 80
|
545 |
|
|
{I1DCNT {ADDsA_C == ir1}} & I1_R2R |// ADD A,C ; 81
|
546 |
|
|
{I1DCNT {ADDsA_D == ir1}} & I1_R2R |// ADD A,D ; 82
|
547 |
|
|
{I1DCNT {ADDsA_E == ir1}} & I1_R2R |// ADD A,E ; 83
|
548 |
|
|
{I1DCNT {ADDsA_H == ir1}} & I1_R2R |// ADD A,H ; 84
|
549 |
|
|
{I1DCNT {ADDsA_L == ir1}} & I1_R2R |// ADD A,L ; 85
|
550 |
|
|
{I1DCNT {ADDsHL_BC == ir1}} & I1_R2R |// ADD HL,BC ; 09
|
551 |
|
|
{I1DCNT {ADDsHL_DE == ir1}} & I1_R2R |// ADD HL,DE ; 19
|
552 |
|
|
{I1DCNT {ADDsHL_HL == ir1}} & I1_R2R |// ADD HL,HL ; 29
|
553 |
|
|
{I1DCNT {ADDsHL_SP == ir1}} & I1_R2R |// ADD HL,SP ; 39
|
554 |
|
|
{I1DCNT {ANDsA == ir1}} & I1_R2R |// AND A ; A7
|
555 |
|
|
{I1DCNT {ANDsB == ir1}} & I1_R2R |// AND B ; A0
|
556 |
|
|
{I1DCNT {ANDsC == ir1}} & I1_R2R |// AND C ; A1
|
557 |
|
|
{I1DCNT {ANDsD == ir1}} & I1_R2R |// AND D ; A2
|
558 |
|
|
{I1DCNT {ANDsE == ir1}} & I1_R2R |// AND E ; A3
|
559 |
|
|
{I1DCNT {ANDsH == ir1}} & I1_R2R |// AND H ; A4
|
560 |
|
|
{I1DCNT {ANDsL == ir1}} & I1_R2R |// AND L ; A5
|
561 |
|
|
{I1DCNT {CCF == ir1}} & I1_R2R |// CCF ; 3F
|
562 |
|
|
{I1DCNT {CPL == ir1}} & I1_R2R |// CPL ; 2F
|
563 |
|
|
{I1DCNT {CPsA == ir1}} & I1_R2R |// CP A ; BF
|
564 |
|
|
{I1DCNT {CPsB == ir1}} & I1_R2R |// CP B ; B8
|
565 |
|
|
{I1DCNT {CPsC == ir1}} & I1_R2R |// CP C ; B9
|
566 |
|
|
{I1DCNT {CPsD == ir1}} & I1_R2R |// CP D ; BA
|
567 |
|
|
{I1DCNT {CPsE == ir1}} & I1_R2R |// CP E ; BB
|
568 |
|
|
{I1DCNT {CPsH == ir1}} & I1_R2R |// CP H ; BC
|
569 |
|
|
{I1DCNT {CPsL == ir1}} & I1_R2R |// CP L ; BD
|
570 |
|
|
{I1DCNT {DAA == ir1}} & I1_R2R |// DAA ; 27
|
571 |
|
|
{I1DCNT {DECsA == ir1}} & I1_R2R |// DEC A ; 3D
|
572 |
|
|
{I1DCNT {DECsB == ir1}} & I1_R2R |// DEC B ; 05
|
573 |
|
|
{I1DCNT {DECsBC == ir1}} & I1_R2R |// DEC BC ; 0B
|
574 |
|
|
{I1DCNT {DECsC == ir1}} & I1_R2R |// DEC C ; 0D
|
575 |
|
|
{I1DCNT {DECsD == ir1}} & I1_R2R |// DEC D ; 15
|
576 |
|
|
{I1DCNT {DECsDE == ir1}} & I1_R2R |// DEC DE ; 1B
|
577 |
|
|
{I1DCNT {DECsE == ir1}} & I1_R2R |// DEC E ; 1D
|
578 |
|
|
{I1DCNT {DECsH == ir1}} & I1_R2R |// DEC H ; 25
|
579 |
|
|
{I1DCNT {DECsHL == ir1}} & I1_R2R |// DEC HL ; 2B
|
580 |
|
|
{I1DCNT {DECsL == ir1}} & I1_R2R |// DEC L ; 2D
|
581 |
|
|
{I1DCNT {DECsSP == ir1}} & I1_R2R |// DEC SP ; 3B
|
582 |
|
|
{I1DCNT {DI == ir1}} & I1_R2R |// DI ; F3
|
583 |
|
|
{I1DCNT {DJNZs$t2 == ir1}} & I1_R2R |// DJNZ $+2 ; 10 XX
|
584 |
|
|
{I1DCNT {EI == ir1}} & I1_R2R |// EI ; FB
|
585 |
|
|
{I1DCNT {EXX == ir1}} & I1_R2R |// EXX ; D9
|
586 |
|
|
{I1DCNT {EXsAF_AFp == ir1}} & I1_R2R |// EX AF,AF' ; 08
|
587 |
|
|
{I1DCNT {EXsDE_HL == ir1}} & I1_R2R |// EX DE,HL ; EB
|
588 |
|
|
{I1DCNT {HALT == ir1}} & I1_R2R |// HALT ; 76
|
589 |
|
|
{I1DCNT {INCsA == ir1}} & I1_R2R |// INC A ; 3C
|
590 |
|
|
{I1DCNT {INCsB == ir1}} & I1_R2R |// INC B ; 04
|
591 |
|
|
{I1DCNT {INCsBC == ir1}} & I1_R2R |// INC BC ; 03
|
592 |
|
|
{I1DCNT {INCsC == ir1}} & I1_R2R |// INC C ; 0C
|
593 |
|
|
{I1DCNT {INCsD == ir1}} & I1_R2R |// INC D ; 14
|
594 |
|
|
{I1DCNT {INCsDE == ir1}} & I1_R2R |// INC DE ; 13
|
595 |
|
|
{I1DCNT {INCsE == ir1}} & I1_R2R |// INC E ; 1C
|
596 |
|
|
{I1DCNT {INCsH == ir1}} & I1_R2R |// INC H ; 24
|
597 |
|
|
{I1DCNT {INCsHL == ir1}} & I1_R2R |// INC HL ; 23
|
598 |
|
|
{I1DCNT {INCsL == ir1}} & I1_R2R |// INC L ; 2C
|
599 |
|
|
{I1DCNT {INCsSP == ir1}} & I1_R2R |// INC SP ; 33
|
600 |
|
|
{I1DCNT {LDsA_A == ir1}} & I1_R2R |// LD A,A ; 7F
|
601 |
|
|
{I1DCNT {LDsA_B == ir1}} & I1_R2R |// LD A,B ; 78
|
602 |
|
|
{I1DCNT {LDsA_C == ir1}} & I1_R2R |// LD A,C ; 79
|
603 |
|
|
{I1DCNT {LDsA_D == ir1}} & I1_R2R |// LD A,D ; 7A
|
604 |
|
|
{I1DCNT {LDsA_E == ir1}} & I1_R2R |// LD A,E ; 7B
|
605 |
|
|
{I1DCNT {LDsA_H == ir1}} & I1_R2R |// LD A,H ; 7C
|
606 |
|
|
{I1DCNT {LDsA_L == ir1}} & I1_R2R |// LD A,L ; 7D
|
607 |
|
|
{I1DCNT {LDsB_A == ir1}} & I1_R2R |// LD B,A ; 47
|
608 |
|
|
{I1DCNT {LDsB_B == ir1}} & I1_R2R |// LD B,B ; 40
|
609 |
|
|
{I1DCNT {LDsB_C == ir1}} & I1_R2R |// LD B,C ; 41
|
610 |
|
|
{I1DCNT {LDsB_D == ir1}} & I1_R2R |// LD B,D ; 42
|
611 |
|
|
{I1DCNT {LDsB_E == ir1}} & I1_R2R |// LD B,E ; 43
|
612 |
|
|
{I1DCNT {LDsB_H == ir1}} & I1_R2R |// LD B,H ; 44
|
613 |
|
|
{I1DCNT {LDsB_L == ir1}} & I1_R2R |// LD B,L ; 45
|
614 |
|
|
{I1DCNT {LDsC_A == ir1}} & I1_R2R |// LD C,A ; 4F
|
615 |
|
|
{I1DCNT {LDsC_B == ir1}} & I1_R2R |// LD C,B ; 48
|
616 |
|
|
{I1DCNT {LDsC_C == ir1}} & I1_R2R |// LD C,C ; 49
|
617 |
|
|
{I1DCNT {LDsC_D == ir1}} & I1_R2R |// LD C,D ; 4A
|
618 |
|
|
{I1DCNT {LDsC_E == ir1}} & I1_R2R |// LD C,E ; 4B
|
619 |
|
|
{I1DCNT {LDsC_H == ir1}} & I1_R2R |// LD C,H ; 4C
|
620 |
|
|
{I1DCNT {LDsC_L == ir1}} & I1_R2R |// LD C,L ; 4D
|
621 |
|
|
{I1DCNT {LDsD_A == ir1}} & I1_R2R |// LD D,A ; 57
|
622 |
|
|
{I1DCNT {LDsD_B == ir1}} & I1_R2R |// LD D,B ; 50
|
623 |
|
|
{I1DCNT {LDsD_C == ir1}} & I1_R2R |// LD D,C ; 51
|
624 |
|
|
{I1DCNT {LDsD_D == ir1}} & I1_R2R |// LD D,D ; 52
|
625 |
|
|
{I1DCNT {LDsD_E == ir1}} & I1_R2R |// LD D,E ; 53
|
626 |
|
|
{I1DCNT {LDsD_H == ir1}} & I1_R2R |// LD D,H ; 54
|
627 |
|
|
{I1DCNT {LDsD_L == ir1}} & I1_R2R |// LD D,L ; 55
|
628 |
|
|
{I1DCNT {LDsE_A == ir1}} & I1_R2R |// LD E,A ; 5F
|
629 |
|
|
{I1DCNT {LDsE_B == ir1}} & I1_R2R |// LD E,B ; 58
|
630 |
|
|
{I1DCNT {LDsE_C == ir1}} & I1_R2R |// LD E,C ; 59
|
631 |
|
|
{I1DCNT {LDsE_D == ir1}} & I1_R2R |// LD E,D ; 5A
|
632 |
|
|
{I1DCNT {LDsE_E == ir1}} & I1_R2R |// LD E,E ; 5B
|
633 |
|
|
{I1DCNT {LDsE_H == ir1}} & I1_R2R |// LD E,H ; 5C
|
634 |
|
|
{I1DCNT {LDsE_L == ir1}} & I1_R2R |// LD E,L ; 5D
|
635 |
|
|
{I1DCNT {LDsH_A == ir1}} & I1_R2R |// LD H,A ; 67
|
636 |
|
|
{I1DCNT {LDsH_B == ir1}} & I1_R2R |// LD H,B ; 60
|
637 |
|
|
{I1DCNT {LDsH_C == ir1}} & I1_R2R |// LD H,C ; 61
|
638 |
|
|
{I1DCNT {LDsH_D == ir1}} & I1_R2R |// LD H,D ; 62
|
639 |
|
|
{I1DCNT {LDsH_E == ir1}} & I1_R2R |// LD H,E ; 63
|
640 |
|
|
{I1DCNT {LDsH_H == ir1}} & I1_R2R |// LD H,H ; 64
|
641 |
|
|
{I1DCNT {LDsH_L == ir1}} & I1_R2R |// LD H,L ; 65
|
642 |
|
|
{I1DCNT {LDsL_A == ir1}} & I1_R2R |// LD L,A ; 6F
|
643 |
|
|
{I1DCNT {LDsL_B == ir1}} & I1_R2R |// LD L,B ; 68
|
644 |
|
|
{I1DCNT {LDsL_C == ir1}} & I1_R2R |// LD L,C ; 69
|
645 |
|
|
{I1DCNT {LDsL_D == ir1}} & I1_R2R |// LD L,D ; 6A
|
646 |
|
|
{I1DCNT {LDsL_E == ir1}} & I1_R2R |// LD L,E ; 6B
|
647 |
|
|
{I1DCNT {LDsL_H == ir1}} & I1_R2R |// LD L,H ; 6C
|
648 |
|
|
{I1DCNT {LDsL_L == ir1}} & I1_R2R |// LD L,L ; 6D
|
649 |
|
|
{I1DCNT {LDsSP_HL == ir1}} & I1_R2R |// LD SP,HL ; F9
|
650 |
|
|
{I1DCNT {NOP == ir1}} & I1_R2R |// NOP ; 00
|
651 |
|
|
{I1DCNT {ORsA == ir1}} & I1_R2R |// OR A ; B7
|
652 |
|
|
{I1DCNT {ORsB == ir1}} & I1_R2R |// OR B ; B0
|
653 |
|
|
{I1DCNT {ORsC == ir1}} & I1_R2R |// OR C ; B1
|
654 |
|
|
{I1DCNT {ORsD == ir1}} & I1_R2R |// OR D ; B2
|
655 |
|
|
{I1DCNT {ORsE == ir1}} & I1_R2R |// OR E ; B3
|
656 |
|
|
{I1DCNT {ORsH == ir1}} & I1_R2R |// OR H ; B4
|
657 |
|
|
{I1DCNT {ORsL == ir1}} & I1_R2R |// OR L ; B5
|
658 |
|
|
{I1DCNT {RLA == ir1}} & I1_R2R |// RLA ; 17
|
659 |
|
|
{I1DCNT {RLCA == ir1}} & I1_R2R |// RLCA ; 07
|
660 |
|
|
{I1DCNT {RRA == ir1}} & I1_R2R |// RRA ; 1F
|
661 |
|
|
{I1DCNT {RRCA == ir1}} & I1_R2R |// RRCA ; 0F
|
662 |
|
|
{I1DCNT {SBCsA == ir1}} & I1_R2R |// SBC A ; 9F
|
663 |
|
|
{I1DCNT {SBCsB == ir1}} & I1_R2R |// SBC B ; 98
|
664 |
|
|
{I1DCNT {SBCsC == ir1}} & I1_R2R |// SBC C ; 99
|
665 |
|
|
{I1DCNT {SBCsD == ir1}} & I1_R2R |// SBC D ; 9A
|
666 |
|
|
{I1DCNT {SBCsE == ir1}} & I1_R2R |// SBC E ; 9B
|
667 |
|
|
{I1DCNT {SBCsH == ir1}} & I1_R2R |// SBC H ; 9C
|
668 |
|
|
{I1DCNT {SBCsL == ir1}} & I1_R2R |// SBC L ; 9D
|
669 |
|
|
{I1DCNT {SCF == ir1}} & I1_R2R |// SCF ; 37
|
670 |
|
|
{I1DCNT {SUBsA == ir1}} & I1_R2R |// SUB A ; 97
|
671 |
|
|
{I1DCNT {SUBsB == ir1}} & I1_R2R |// SUB B ; 90
|
672 |
|
|
{I1DCNT {SUBsC == ir1}} & I1_R2R |// SUB C ; 91
|
673 |
|
|
{I1DCNT {SUBsD == ir1}} & I1_R2R |// SUB D ; 92
|
674 |
|
|
{I1DCNT {SUBsE == ir1}} & I1_R2R |// SUB E ; 93
|
675 |
|
|
{I1DCNT {SUBsH == ir1}} & I1_R2R |// SUB H ; 94
|
676 |
|
|
{I1DCNT {SUBsL == ir1}} & I1_R2R |// SUB L ; 95
|
677 |
|
|
{I1DCNT {XORsA == ir1}} & I1_R2R |// XOR A ; AF
|
678 |
|
|
{I1DCNT {XORsB == ir1}} & I1_R2R |// XOR B ; A8
|
679 |
|
|
{I1DCNT {XORsC == ir1}} & I1_R2R |// XOR C ; A9
|
680 |
|
|
{I1DCNT {XORsD == ir1}} & I1_R2R |// XOR D ; AA
|
681 |
|
|
{I1DCNT {XORsE == ir1}} & I1_R2R |// XOR E ; AB
|
682 |
|
|
{I1DCNT {XORsH == ir1}} & I1_R2R |// XOR H ; AC
|
683 |
|
|
{I1DCNT {XORsL == ir1}} & I1_R2R |// XOR L ; AD
|
684 |
|
|
{I1DCNT {RET == ir1}} & I1_RET |// RET ; C9
|
685 |
|
|
{I1DCNT {RETsC == ir1 & cf }} & I1_RET |// RET C ; D8
|
686 |
|
|
{I1DCNT {RETsM == ir1 & sf }} & I1_RET |// RET M ; F8
|
687 |
|
|
{I1DCNT {RETsNC== ir1 & ~cf }} & I1_RET |// RET NC ; D0
|
688 |
|
|
{I1DCNT {RETsP == ir1 & ~sf }} & I1_RET |// RET P ; F0
|
689 |
|
|
{I1DCNT {RETsPE== ir1 & pvf }} & I1_RET |// RET PE ; E8
|
690 |
|
|
{I1DCNT {RETsPO== ir1 & ~pvf}} & I1_RET |// RET PO ; E0
|
691 |
|
|
{I1DCNT {RETsNZ== ir1 & ~zf }} & I1_RET |// RET NZ ; C0
|
692 |
|
|
{I1DCNT {RETsZ == ir1 & zf }} & I1_RET |// RET Z ; C8
|
693 |
|
|
{I1DCNT {EXs6SP7_HL == ir1}} & I1_RMW |// EX (SP),HL ; E3
|
694 |
|
|
{I1DCNT {DECs6HL7 == ir1}} & I1_RMW |// DEC (HL) ; 35
|
695 |
|
|
{I1DCNT {INCs6HL7 == ir1}} & I1_RMW |// INC (HL) ; 34
|
696 |
|
|
{I1DCNT {RSTs0 == ir1}} & I1_RST |// RST 0 ; C7
|
697 |
|
|
{I1DCNT {RSTs10H == ir1}} & I1_RST |// RST 10H ; D7
|
698 |
|
|
{I1DCNT {RSTs18H == ir1}} & I1_RST |// RST 18H ; DF
|
699 |
|
|
{I1DCNT {RSTs20H == ir1}} & I1_RST |// RST 20H ; E7
|
700 |
|
|
{I1DCNT {RSTs28H == ir1}} & I1_RST |// RST 28H ; EF
|
701 |
|
|
{I1DCNT {RSTs30H == ir1}} & I1_RST |// RST 30H ; F7
|
702 |
|
|
{I1DCNT {RSTs38H == ir1}} & I1_RST |// RST 38H ; FF
|
703 |
|
|
{I1DCNT {RSTs8H == ir1}} & I1_RST ;// RST 8H ; CF
|
704 |
|
|
|
705 |
|
|
//-------- CB decodes -----------------------
|
706 |
|
|
|
707 |
|
|
// First cut below
|
708 |
|
|
// CB_RLC = 7'b01_00_000, // these must be compaired with ir[9:3]
|
709 |
|
|
// CB_RRC = 7'b01_00_001, // these must be compaired with ir[9:3]
|
710 |
|
|
// CB_RL = 7'b01_00_010, // these must be compaired with ir[9:3]
|
711 |
|
|
// CB_RR = 7'b01_00_011, // these must be compaired with ir[9:3]
|
712 |
|
|
// CB_SLA = 7'b01_00_100, // these must be compaired with ir[9:3]
|
713 |
|
|
// CB_SRA = 7'b01_00_101, // these must be compaired with ir[9:3]
|
714 |
|
|
// CB_SLL = 7'b01_00_110, // these must be compaired with ir[9:3]
|
715 |
|
|
// CB_SRL = 7'b01_00_111, // these must be compaired with ir[9:3]
|
716 |
|
|
|
717 |
|
|
// CB_BIT = 4'b01_01, // these must be compaired with ir[9:6]
|
718 |
|
|
// CB_RES = 4'b01_10, // these must be compaired with ir[9:6]
|
719 |
|
|
// CB_SET = 4'b01_11, // these must be compaired with ir[9:6]
|
720 |
|
|
|
721 |
|
|
// note these are all read-modify-writ except CB_BIT
|
722 |
|
|
assign cb_mem = (CB_MEM == ir1[2:0]); // this must be compaired with ir[2:0]
|
723 |
|
|
|
724 |
|
|
// The ED Group
|
725 |
|
|
// These are the "unique instructions in the 46, 47 rows that NEED? to be implemented
|
726 |
|
|
// Not sure I want to worry about all undocumented stuff in these rows - hard to believe
|
727 |
|
|
// It will matter.(IM modes are very system dependent - hard to believe even a programmer
|
728 |
|
|
// would use undocumented instructions to muck with this stuff)
|
729 |
|
|
// reg 2 reg simply executed by ir2 logic
|
730 |
|
|
// ED_IMs0 = 10'h246// IM 0 ; ED 46 set IM0
|
731 |
|
|
// ED_LDsI_A = 10'h247// LD I,A ; ED 47 move a to I
|
732 |
|
|
// ED_IMs1 = 10'h256// IM 1 ; ED 56 set IM1
|
733 |
|
|
// ED_LDsA_I = 10'h257// LD A,I ; ED 57 move I to A
|
734 |
|
|
// ED_IMs2 = 10'h25E// IM 2 ; ED 5E set IM2
|
735 |
|
|
// ED_RRD = 10'h267// RRD ; ED 67 nibble roates A HL
|
736 |
|
|
// ED_RLD = 10'h26F// RLD ; ED 6F nibble roates A HL
|
737 |
|
|
|
738 |
|
|
// set (or clear) repeat flag at DEC_EB.
|
739 |
|
|
// set (or clear) inc flag at DEC_EB.
|
740 |
|
|
// seperate flows for LD, CP, IN, OUT.
|
741 |
|
|
// ED_LDI == ir1// LDI ; ED A0 These are block move
|
742 |
|
|
// ED_CPI == ir1// CPI ; ED A1 type insts that don't repeat
|
743 |
|
|
// ED_INI == ir1// INI ; ED A2
|
744 |
|
|
// ED_OUTI == ir1// OUTI ; ED A3
|
745 |
|
|
// ED_LDD == ir1// LDD ; ED A8
|
746 |
|
|
// ED_CPD == ir1// CPD ; ED A9
|
747 |
|
|
// ED_IND == ir1// IND ; ED AA
|
748 |
|
|
// ED_OUTD == ir1// OUTD ; ED AB
|
749 |
|
|
wire dec_blk_rpt =
|
750 |
|
|
ED_LDIR == ir1 |// LDIR ; ED B0 These are block move
|
751 |
|
|
ED_CPIR == ir1 |// CPIR ; ED B1 type insts that DO repeat
|
752 |
|
|
ED_INIR == ir1 |// INIR ; ED B2
|
753 |
|
|
ED_OTIR == ir1 |// OTIR ; ED B3
|
754 |
|
|
ED_LDDR == ir1 |// LDDR ; ED B8
|
755 |
|
|
ED_CPDR == ir1 |// CPDR ; ED B9
|
756 |
|
|
ED_INDR == ir1 |// INDR ; ED BA
|
757 |
|
|
ED_OTDR == ir1 ;// OTDR ; ED BB
|
758 |
|
|
wire ed_blk_mv = ED_LDIR == ir1 | ED_LDI == ir1 |
|
759 |
|
|
ED_LDDR == ir1 | ED_LDD == ir1 ;
|
760 |
|
|
wire ed_blk_cp = ED_CPIR == ir1 | ED_CPI == ir1 |
|
761 |
|
|
ED_CPDR == ir1 | ED_CPD == ir1 ;
|
762 |
|
|
wire ed_blk_in = ED_INIR == ir1 | ED_INI == ir1 |
|
763 |
|
|
ED_INDR == ir1 | ED_IND == ir1 ;
|
764 |
|
|
|
765 |
|
|
wire ed_blk_out = ED_OTIR == ir1 | ED_OUTI == ir1 |
|
766 |
|
|
ED_OTDR == ir1 | ED_OUTD == ir1 ;
|
767 |
|
|
|
768 |
|
|
wire dec_blk_io = ed_blk_in | ed_blk_in;
|
769 |
|
|
|
770 |
|
|
wire blk_done = ~blk_rpt_flg | beq0 & ceq0 | blk_io_flg & ceq0;
|
771 |
|
|
|
772 |
|
|
assign dec_blk_inc = ED_LDIR == ir1 |
|
773 |
|
|
ED_CPIR == ir1 |
|
774 |
|
|
ED_INIR == ir1 |
|
775 |
|
|
ED_OTIR == ir1 |
|
776 |
|
|
ED_LDI == ir1 |
|
777 |
|
|
ED_CPI == ir1 |
|
778 |
|
|
ED_INI == ir1 |
|
779 |
|
|
ED_OUTI == ir1 ;
|
780 |
|
|
|
781 |
|
|
|
782 |
|
|
//The ED70 instruction reads from I/O port C,
|
783 |
|
|
//but does not store the result.
|
784 |
|
|
//It just affects the flags. Hard to test. like the other IN x,(C) instruction.
|
785 |
|
|
//
|
786 |
|
|
//ED71 simply outs the value 0 to I/O port C.
|
787 |
|
|
// This suggests that we should decode as follows:
|
788 |
|
|
// I hope if I don't get all the IM duplicates right it won't be a tragedy
|
789 |
|
|
// ED_INsREG_6C7 = 7'b1001___000,// compair with {ir[7:6],ir[2:0]}
|
790 |
|
|
//
|
791 |
|
|
// ED_SBCsHL_REG = 8'b1001__0010, // compair with {ir[9:6],ir[3:0]}
|
792 |
|
|
// ED_ADCsHL_REG = 8'b1001__1010, // compair with {ir[9:6],ir[3:0]}
|
793 |
|
|
// ED_LDs6NN7_REG = 8'b1001__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
|
794 |
|
|
// ED_LDsREG_6NN7 = 8'b1001__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
|
795 |
|
|
// ED_NEG = 7'b1001___100, // compair with {ir[9:6],ir[2:0]} all A<= -A
|
796 |
|
|
// ED_RETN = 7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti
|
797 |
|
|
wire ed_nn = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} |
|
798 |
|
|
ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]} ;
|
799 |
|
|
|
800 |
|
|
// we use all these to enable interrupts
|
801 |
|
|
wire ed_retn = ED_RETN == {ir1[9:6],ir1[2:0]};
|
802 |
|
|
|
803 |
|
|
assign ed_dbl_rd = ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]};
|
804 |
|
|
|
805 |
|
|
|
806 |
|
|
// assign cb_mem = CB_MEM = ir1[2:0]; // CB_MEM = 3'h110,
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
|
810 |
|
|
|
811 |
|
|
wire jmpr_true =
|
812 |
|
|
JRs$t2 == ir1 |
|
813 |
|
|
JRsC_$t2 == ir1 & fr[0] |
|
814 |
|
|
JRsNC_$t2 == ir1 & ~fr[0] |
|
815 |
|
|
JRsZ_$t2 == ir1 & fr[6] |
|
816 |
|
|
JRsNZ_$t2 == ir1 & ~fr[6] ;
|
817 |
|
|
|
818 |
|
|
//assign { sf, zf. f5f, hf, f3f, pvf, nf, cf} = fr;
|
819 |
|
|
wire callnn_true = CALLsC_NN == ir1 & cf |
|
820 |
|
|
CALLsNC_NN == ir1 & ~cf |
|
821 |
|
|
CALLsNN == ir1 |
|
822 |
|
|
CALLsNZ_NN == ir1 & ~zf |
|
823 |
|
|
CALLsPE_NN == ir1 & pvf |
|
824 |
|
|
CALLsPO_NN == ir1 & ~pvf|
|
825 |
|
|
CALLsP_NN == ir1 & ~sf |
|
826 |
|
|
CALLsZ_NN == ir1 & zf |
|
827 |
|
|
CALLsM_NN == ir1 & sf ;
|
828 |
|
|
|
829 |
|
|
wire jmpnn_true = JPsC == ir1 & cf |
|
830 |
|
|
JPsNC == ir1 & ~cf |
|
831 |
|
|
JP == ir1 |
|
832 |
|
|
JPsNZ == ir1 & ~zf |
|
833 |
|
|
JPsPE == ir1 & pvf |
|
834 |
|
|
JPsPO == ir1 & ~pvf|
|
835 |
|
|
JPsP == ir1 & ~sf |
|
836 |
|
|
JPsZ == ir1 & zf |
|
837 |
|
|
JPsM == ir1 & sf ;
|
838 |
|
|
|
839 |
|
|
// PUSHsAF == ir1
|
840 |
|
|
// PUSHsBC == ir1
|
841 |
|
|
// PUSHsDE == ir1
|
842 |
|
|
// PUSHsHL == ir1
|
843 |
|
|
|
844 |
|
|
wire os_a = LDs6BC7_A == ir1 | // LD (BC),A ; 02
|
845 |
|
|
LDs6DE7_A == ir1 | // LD (DE),A ; 12
|
846 |
|
|
LDs6HL7_A == ir1 | // LD (HL),A ; 77
|
847 |
|
|
LDs6NN7_A == ir1 | // LD (NN),A ; 32 XX XX
|
848 |
|
|
PUSHsAF == ir1 |
|
849 |
|
|
OUTs6N7_A == ir1 |
|
850 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0] && REG8_A == ir1[5:3]} ;
|
851 |
|
|
|
852 |
|
|
wire os_b = LDs6HL7_B == ir1 | // LD (HL),B ; 70
|
853 |
|
|
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_BC == ir1[5:4] |
|
854 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_B == ir1[5:3] ;
|
855 |
|
|
|
856 |
|
|
wire os_c = LDs6HL7_C == ir1 | // LD (HL),C ; 71
|
857 |
|
|
PUSHsBC == ir1 | // PUSH BC
|
858 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_C == ir1[5:3] ;
|
859 |
|
|
|
860 |
|
|
wire os_d = LDs6HL7_D == ir1 | // LD (HL),D ; 72
|
861 |
|
|
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_DE == ir1[5:4] |
|
862 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_D == ir1[5:3] ;
|
863 |
|
|
|
864 |
|
|
|
865 |
|
|
wire os_e = LDs6HL7_E == ir1 | // LD (HL),E ; 73
|
866 |
|
|
PUSHsDE == ir1 | // PUSH DE
|
867 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_E == ir1[5:3] ;
|
868 |
|
|
|
869 |
|
|
wire os_h = LDs6HL7_H == ir1 | // LD (HL),H ; 74
|
870 |
|
|
LDs6NN7_HL == ir1 | // LD (NN),HL ; 22 XX XX
|
871 |
|
|
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_HL == ir1[5:4] |
|
872 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_H == ir1[5:3] ;
|
873 |
|
|
|
874 |
|
|
wire os_l = LDs6HL7_L == ir1 | // LD (HL),L ; 75
|
875 |
|
|
PUSHsHL == ir1 |
|
876 |
|
|
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_L == ir1[5:3] ;
|
877 |
|
|
|
878 |
|
|
wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4];
|
879 |
|
|
|
880 |
|
|
wire os_f = PUSHsAF == ir1 ;
|
881 |
|
|
|
882 |
|
|
|
883 |
|
|
//---------------- inst hazard ----------------------------------------------------------
|
884 |
|
|
//
|
885 |
|
|
// On some reflection, I don't think I'm going to worry about this immediately - it
|
886 |
|
|
// should be easy to kludge in a fix if necessary -- and there are more important things
|
887 |
|
|
// todo. It is a very bad programming practice to muck with the instruction stream in any
|
888 |
|
|
// case -- I have to believe most target applications do not do this -- although I'll probably
|
889 |
|
|
// get hit pretty early with a instruction test that does. Oh well -- if that happens we fix
|
890 |
|
|
// it.
|
891 |
|
|
// Well -- think some here -- the hazard is because of a change in design.
|
892 |
|
|
// If used to any extent.. Somebody WILL
|
893 |
|
|
// want this to act the same way as the origional - even if the programming is "poor".
|
894 |
|
|
// >>>>>>>> bite the bullet and do it.
|
895 |
|
|
//
|
896 |
|
|
// if we do an operand store and the address == pc-1 its an inst hazard, We need to execute the
|
897 |
|
|
// store decrement pc and re-fetch. This is a high priority interrupt.
|
898 |
|
|
// what about multi-byte stores - like LDs6NN7_A or LDs6NN7_HL - i guess we do an IF - to start
|
899 |
|
|
// the pipe before the os -- same logic.
|
900 |
|
|
//
|
901 |
|
|
|
902 |
|
|
|
903 |
|
|
//-----------------data hazard ----------------------------------------------------------
|
904 |
|
|
//
|
905 |
|
|
// Issues here have evolved to a degree as the design progressed. However the
|
906 |
|
|
// Key has always been that for each instruction (no matter how complex) there
|
907 |
|
|
// is only a single state in which the previous instruction can also be active
|
908 |
|
|
// and that is the DEC_EXEC state. If there is a data hazard, we need to delay
|
909 |
|
|
// execution of that state until the ir2 execution completes (which it always does
|
910 |
|
|
// in a single tick). Note that only the RET instructions test the flag register
|
911 |
|
|
// on DEC_EXEC.
|
912 |
|
|
//
|
913 |
|
|
// WARNING: be very careful about this. Data hazard logic is very difficult to
|
914 |
|
|
// verify as there are so many instruction pairs to test.
|
915 |
|
|
//
|
916 |
|
|
// Situations 1) operand stores from ir1 when register is updated in ir2
|
917 |
|
|
// 2) flag tests when fr is being updated
|
918 |
|
|
// 3) sp issues see below LDsSP_HL DECsSP INCsSP
|
919 |
|
|
// ANY OTHERS ???
|
920 |
|
|
//
|
921 |
|
|
// upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
|
922 |
|
|
wire use_hl_exec = LDsSP_HL == ir1;
|
923 |
|
|
wire use_sp_exec = MEM_OFSP == next_mem_state |
|
924 |
|
|
MEM_OSSP == next_mem_state ;
|
925 |
|
|
wire upd_sp_exec = DECsSP == ir2 |
|
926 |
|
|
INCsSP == ir2 ;
|
927 |
|
|
|
928 |
|
|
|
929 |
|
|
|
930 |
|
|
wire use_fr_exec = ( RETsC == ir1 |
|
931 |
|
|
RETsM == ir1 |
|
932 |
|
|
RETsNC == ir1 |
|
933 |
|
|
RETsP == ir1 |
|
934 |
|
|
RETsPE == ir1 |
|
935 |
|
|
RETsPO == ir1 |
|
936 |
|
|
RETsNZ == ir1 |
|
937 |
|
|
RETsZ == ir1 ) ;
|
938 |
|
|
|
939 |
|
|
assign hazard = (dec_state == DEC_EXEC & exec_ir2 ) & ( upd_fr & use_fr_exec |
|
940 |
|
|
upd_ar & os_a |
|
941 |
|
|
upd_br & os_b |
|
942 |
|
|
upd_cr & os_c |
|
943 |
|
|
upd_dr & os_d |
|
944 |
|
|
upd_er & os_e |
|
945 |
|
|
upd_hr & os_h |
|
946 |
|
|
upd_lr & os_l |
|
947 |
|
|
upd_hr & use_hl_exec |
|
948 |
|
|
upd_lr & use_hl_exec |
|
949 |
|
|
upd_sp_exec & use_sp_exec );
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
|
953 |
|
|
|
954 |
|
|
|
955 |
|
|
|
956 |
|
|
// does not include extension stuff as we are mostly looking for hazards here
|
957 |
|
|
// course we do use these terms to build more decodes
|
958 |
|
|
//
|
959 |
|
|
wire opadr_bc = LDsA_6BC7 == ir1 | LDs6BC7_A == ir1;
|
960 |
|
|
wire opadr_de = LDsA_6DE7 == ir1 | LDs6DE7_A == ir1;
|
961 |
|
|
wire opadr_hl = LDsB_6HL7 == ir1 | ORs6HL7 == ir1 | LDs6HL7_B == ir1 |
|
962 |
|
|
LDsD_6HL7 == ir1 | LDsC_6HL7 == ir1 | LDs6HL7_C == ir1 |
|
963 |
|
|
LDsH_6HL7 == ir1 | LDsE_6HL7 == ir1 | LDs6HL7_D == ir1 |
|
964 |
|
|
ADDsA_6HL7 == ir1 | LDsL_6HL7 == ir1 | LDs6HL7_E == ir1 |
|
965 |
|
|
SUBs6HL7 == ir1 | LDsA_6HL7 == ir1 | LDs6HL7_H == ir1 |
|
966 |
|
|
ANDs6HL7 == ir1 | ADCsA_6HL7 == ir1 | LDs6HL7_L == ir1 |
|
967 |
|
|
XORs6HL7 == ir1 | SBCs6HL7 == ir1 | CPs6HL7 == ir1 ;
|
968 |
|
|
|
969 |
|
|
assign use_a = os_a;
|
970 |
|
|
assign use_b = os_b | opadr_bc;
|
971 |
|
|
assign use_c = os_c | opadr_bc;
|
972 |
|
|
assign use_d = os_d | opadr_de;
|
973 |
|
|
assign use_e = os_e | opadr_de;
|
974 |
|
|
assign use_h = os_h | opadr_hl;
|
975 |
|
|
assign use_l = os_l | opadr_hl;
|
976 |
|
|
|
977 |
|
|
|
978 |
|
|
|
979 |
|
|
assign use_flags = c_jmp8 | c_jmp4 | c_call | c_ret;
|
980 |
|
|
|
981 |
|
|
|
982 |
|
|
|
983 |
|
|
wire bc_eq0 = beq0 & ceq0;
|
984 |
|
|
// ??? not used ? why defined ?
|
985 |
|
|
//assign rpt_blk_mv = (blk_mv_reg ) & !bc_eq0 |
|
986 |
|
|
// (blk_cmp_reg) & !bc_eq0 & (nn[7:0] != 8'h0) |
|
987 |
|
|
// (blk_in_reg | blk_out_reg) & !b_eq0 ;
|
988 |
|
|
|
989 |
|
|
|
990 |
|
|
|
991 |
|
|
|
992 |
|
|
|
993 |
|
|
|
994 |
|
|
|
995 |
|
|
// BASIC ARCHITECTURE OF THIS FILE pc and sp not shown, but are inputs to src mux.
|
996 |
|
|
// _____ and may be updated from adder output.
|
997 |
|
|
// | |
|
998 |
|
|
// | | pc-1 register is required to implement relative jumps.
|
999 |
|
|
// | |
|
1000 |
|
|
// _____ |lit | |\
|
1001 |
|
|
// | | | | | \
|
1002 |
|
|
// | | |src2 | | \ _____ _____
|
1003 |
|
|
// | | | |----->| | | | | |
|
1004 |
|
|
// |src | |_____| |adder|------->| | | |
|
1005 |
|
|
// |mux | | | | | | |
|
1006 |
|
|
// | |------------------->| / |2/1 |------->|wb |
|
1007 |
|
|
// | | | | / |mux | |adr |
|
1008 |
|
|
// |_____| | |/ | | | |
|
1009 |
|
|
// ------------------->| | | |
|
1010 |
|
|
// |_____| |_____|
|
1011 |
|
|
// MEM_NOP
|
1012 |
|
|
// MEM_IFPP1 MEM_OFIXpD MEM_CALL MEM_IFRST MEM_OFHL_PM MEM_IOF_C
|
1013 |
|
|
// MEM_OS1, MEM_OSIXpD MEM_OSNN, MEM_IFREL_N MEM_OSHL_PM MEM_IOS_C
|
1014 |
|
|
// MEM_OF1, MEM_OSADR MEM_OFNN MEM_JMPHL MEM_OSDE_PM MEM_IOF_N
|
1015 |
|
|
// MEM_OFSP MEM_OSSP_PCM2 MEM_OFADRP1 MEM_IFNN MEM_INTA MEM_IOS_N
|
1016 |
|
|
// MEM_OSSP MEM_OSSP_P MEM_OSADRP1 MEM_IFINT MEM_OS_HL_N
|
1017 |
|
|
//
|
1018 |
|
|
|
1019 |
|
|
wire src_sp = next_mem_state == MEM_OF1 & EXs6SP7_HL == ir1 | //special case rmw
|
1020 |
|
|
next_mem_state == MEM_OFSP |
|
1021 |
|
|
next_mem_state == MEM_OSSP |
|
1022 |
|
|
next_mem_state == MEM_CALL ;
|
1023 |
|
|
wire src_pc = next_mem_state == MEM_IFPP1 |
|
1024 |
|
|
next_mem_state == MEM_IFREL_N ;
|
1025 |
|
|
|
1026 |
|
|
wire src_nn = next_mem_state == MEM_IFNN |
|
1027 |
|
|
next_mem_state == MEM_OSNN |
|
1028 |
|
|
next_mem_state == MEM_OFNN ;
|
1029 |
|
|
|
1030 |
|
|
|
1031 |
|
|
wire src_de = dec_state == DEC_EXEC & LDsA_6DE7 == ir1 | // MEM_OS1 MEM_OF1
|
1032 |
|
|
dec_state == DEC_EXEC & LDs6DE7_A == ir1 | // are both true at this time
|
1033 |
|
|
next_mem_state == MEM_OSDE_PM ;
|
1034 |
|
|
wire src_bc = dec_state == DEC_EXEC & LDsA_6BC7 == ir1 |
|
1035 |
|
|
dec_state == DEC_EXEC & LDs6BC7_A == ir1 |
|
1036 |
|
|
next_mem_state ==MEM_IOF_C |
|
1037 |
|
|
next_mem_state ==MEM_IOS_C ;
|
1038 |
|
|
|
1039 |
|
|
|
1040 |
|
|
// don't forget that hl source can be modified by prefix
|
1041 |
|
|
// this gets messy as we use wb_adr for some of these.
|
1042 |
|
|
//
|
1043 |
|
|
wire src_hl = next_mem_state == MEM_OF1 &
|
1044 |
|
|
(dec_state == DEC_EXEC) &
|
1045 |
|
|
!src_de & !src_bc & !src_sp |
|
1046 |
|
|
next_mem_state == MEM_OS1 &
|
1047 |
|
|
(dec_state == DEC_EXEC) &
|
1048 |
|
|
!src_de & !src_bc |
|
1049 |
|
|
next_mem_state == MEM_OFHL_PM |
|
1050 |
|
|
next_mem_state == MEM_OSHL_PM |
|
1051 |
|
|
next_mem_state == MEM_OS_HL_N |
|
1052 |
|
|
next_mem_state == MEM_JMPHL ;
|
1053 |
|
|
|
1054 |
|
|
wire src_ix = next_mem_state == MEM_OFIXpD & ir1dd |
|
1055 |
|
|
next_mem_state == MEM_OSIXpD & ir1dd ;
|
1056 |
|
|
|
1057 |
|
|
wire src_iy = next_mem_state == MEM_OFIXpD & ir1fd |
|
1058 |
|
|
next_mem_state == MEM_OSIXpD & ir1fd ;
|
1059 |
|
|
|
1060 |
|
|
wire src_adr = next_mem_state == MEM_OFADRP1 |
|
1061 |
|
|
next_mem_state == MEM_OSADRP1 |
|
1062 |
|
|
next_mem_state == MEM_NOP |
|
1063 |
|
|
next_mem_state == MEM_OSADR ;
|
1064 |
|
|
|
1065 |
|
|
wire src_int = next_mem_state == MEM_IOF_N |
|
1066 |
|
|
next_mem_state == MEM_IOS_N ;
|
1067 |
|
|
|
1068 |
|
|
|
1069 |
|
|
|
1070 |
|
|
wire src_mux = {16{ src_sp }} & sp |
|
1071 |
|
|
{16{ src_pc }} & pc |
|
1072 |
|
|
{16{ src_nn }} & nn |
|
1073 |
|
|
{16{ src_hl }} & hl |
|
1074 |
|
|
{16{ src_de }} & de |
|
1075 |
|
|
{16{ src_bc }} & bc |
|
1076 |
|
|
{16{ src_ix }} & ixr |
|
1077 |
|
|
{16{ src_iy }} & iyr |
|
1078 |
|
|
{16{ src_adr }} & wb_adr |
|
1079 |
|
|
{16{ src_int }} & { intr, nn[15:8] } |
|
1080 |
|
|
{16{next_mem_state == MEM_IFRST}} & {10'h0, ir1[6:4], 3'h0} ;
|
1081 |
|
|
|
1082 |
|
|
wire block_mv_inc = (dec_state == DEC_ED) ? dec_blk_inc : blk_inc_flg; // flag set at DEC_ED
|
1083 |
|
|
|
1084 |
|
|
|
1085 |
|
|
|
1086 |
|
|
wire inc_s2 = next_mem_state ==MEM_OFADRP1 |
|
1087 |
|
|
next_mem_state ==MEM_OSADRP1 |
|
1088 |
|
|
next_mem_state ==MEM_OFHL_PM & block_mv_inc |
|
1089 |
|
|
next_mem_state ==MEM_OSHL_PM & block_mv_inc |
|
1090 |
|
|
next_mem_state ==MEM_OSDE_PM & block_mv_inc |
|
1091 |
|
|
next_mem_state ==MEM_OFSP |
|
1092 |
|
|
next_mem_state ==MEM_IFPP1 |
|
1093 |
|
|
next_mem_state ==MEM_OSSP_PCM2 |
|
1094 |
|
|
next_mem_state ==MEM_OSSP_P ;
|
1095 |
|
|
|
1096 |
|
|
wire dec_s2 = next_mem_state ==MEM_OFHL_PM & ~block_mv_inc |
|
1097 |
|
|
next_mem_state ==MEM_OSHL_PM & ~block_mv_inc |
|
1098 |
|
|
next_mem_state ==MEM_OSDE_PM & ~block_mv_inc |
|
1099 |
|
|
next_mem_state == MEM_OFSP ;
|
1100 |
|
|
|
1101 |
|
|
|
1102 |
|
|
wire reln_s2 = next_mem_state == MEM_IFREL_N |
|
1103 |
|
|
next_mem_state == MEM_OFIXpD |
|
1104 |
|
|
next_mem_state == MEM_OSIXpD ;
|
1105 |
|
|
|
1106 |
|
|
wire src2 = {16{ inc }} & 16'h0001 |
|
1107 |
|
|
{16{ dec }} & 16'hffff |
|
1108 |
|
|
{16{ rel }} & {{8{nn[15]}},nn[15:8]}|
|
1109 |
|
|
{16{~(rel_jmp|inc|dec)}} & 16'h0 ;
|
1110 |
|
|
|
1111 |
|
|
wire adr_alu = src2 + src_mux;
|
1112 |
|
|
|
1113 |
|
|
|
1114 |
|
|
wire pre_inc_dec = next_mem_state == MEM_CALL |
|
1115 |
|
|
next_mem_state == MEM_OSSP_P |
|
1116 |
|
|
next_mem_state == MEM_OSSP ;
|
1117 |
|
|
|
1118 |
|
|
|
1119 |
|
|
wire mux21 = pre_inc_dec ? alu : src_mux;
|
1120 |
|
|
|
1121 |
|
|
assign wb_rdy_nhz = (!wb_cyc | wb_ack ) & ~hazard; // wishbone ready with no hazard
|
1122 |
|
|
wire wb_rdy = !wb_cyc | wb_ack;
|
1123 |
|
|
|
1124 |
|
|
assign we_next = next_mem_state == MEM_OS1 |
|
1125 |
|
|
next_mem_state == MEM_OSP |
|
1126 |
|
|
next_mem_state == MEM_OSIXpD |
|
1127 |
|
|
next_mem_state == MEM_OSADR |
|
1128 |
|
|
next_mem_state == MEM_OSSP_PCM2 |
|
1129 |
|
|
next_mem_state == MEM_OSSP_P |
|
1130 |
|
|
next_mem_state == MEM_CALL |
|
1131 |
|
|
next_mem_state == MEM_OSNN |
|
1132 |
|
|
next_mem_state == MEM_OSADRP1 |
|
1133 |
|
|
next_mem_state == MEM_OSHL_PM |
|
1134 |
|
|
next_mem_state == MEM_OSDE_PM |
|
1135 |
|
|
next_mem_state == MEM_OS_HL_N |
|
1136 |
|
|
next_mem_state == MEM_IOS_C |
|
1137 |
|
|
next_mem_state == MEM_IOS_N ;
|
1138 |
|
|
|
1139 |
|
|
|
1140 |
|
|
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
|
1141 |
|
|
// we do this just to save virtual paper below.
|
1142 |
|
|
// 6 5 4 15
|
1143 |
|
|
assign {next_dec_state, next_mem_state, next_pipe_state} = next_state;
|
1144 |
|
|
|
1145 |
|
|
always @(ir1 or wb_int or inst_haz or wb_int or dec_state or mem_exec_dec or cb_mem or ed_nn or
|
1146 |
|
|
ed_blk_cp or ed_blk_in or ed_blk_out or ed_retn or ed_blk_mv or ed_dbl_rd or blk_done or
|
1147 |
|
|
fr or jmpr_true or callnn_true or jmpnn_true )
|
1148 |
|
|
|
1149 |
|
|
begin
|
1150 |
|
|
case (dec_state)
|
1151 |
|
|
DEC_IDLE: next_state = {DEC_IF1, MEM_NOP, IPIPE_NOP};
|
1152 |
|
|
|
1153 |
|
|
DEC_HALT:
|
1154 |
|
|
if (wb_int) next_state = {DEC_INT1,MEM_NOP ,IPIPE_NOP};// stay here until interrupt or reset
|
1155 |
|
|
else next_state = {DEC_HALT,MEM_NOP ,IPIPE_NOP};
|
1156 |
|
|
DEC_IF1 : next_state = {DEC_IF2 ,MEM_IFPP1 ,IPIPE_NOP};
|
1157 |
|
|
DEC_IF2 : next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_EN1};
|
1158 |
|
|
DEC_IF2A: next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_NOP};
|
1159 |
|
|
DEC_EXEC:
|
1160 |
|
|
if (inst_haz) next_state = {DEC_IF1, MEM_DECPC , IPIPE_NOP};
|
1161 |
|
|
else if (wb_int) next_state = {DEC_INT1,MEM_NOP ,IPIPE_NOP};
|
1162 |
|
|
else
|
1163 |
|
|
case (mem_exec_dec) // full case but can all tools understand ? just make a default
|
1164 |
|
|
I1_CB : next_state = {DEC_CB, MEM_IFPP1, IPIPE_EN1};// IF2_NOP -> nn <= (MEM)
|
1165 |
|
|
I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1};// gets real inst
|
1166 |
|
|
I1_ED : next_state = {DEC_ED, MEM_IFPP1, IPIPE_EN1};
|
1167 |
|
|
I1_JMP : next_state = {DEC_IF2, MEM_JMPHL, IPIPE_NOP};
|
1168 |
|
|
I1_N : next_state = {DEC_N, MEM_IFPP1, IPIPE_ENN};
|
1169 |
|
|
I1_NN : next_state = {DEC_NN, MEM_IFPP1, IPIPE_ENN};
|
1170 |
|
|
I1_OF : next_state = {DEC_OF, MEM_OF1, IPIPE_EN12};//transfer, don't activate
|
1171 |
|
|
I1_OS : next_state = {DEC_IF2, MEM_OS1, IPIPE_EN1}; // -> ir2_NOP
|
1172 |
|
|
I1_POP : next_state = {DEC_POP, MEM_OFSP, IPIPE_EN12};
|
1173 |
|
|
I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP, IPIPE_EN12};
|
1174 |
|
|
I1_RET : next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12};
|
1175 |
|
|
I1_RMW : next_state = {DEC_RMW, MEM_OF1, IPIPE_EN12};//can't activate till data rdy
|
1176 |
|
|
I1_RST : next_state = {DEC_IF2, MEM_IFRST, IPIPE_ENN};
|
1177 |
|
|
I1_R2R : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};
|
1178 |
|
|
default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R
|
1179 |
|
|
endcase
|
1180 |
|
|
DEC_CB: if (cb_mem) next_state = {DEC_CBM, MEM_OF1, IPIPE_EN12};
|
1181 |
|
|
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};
|
1182 |
|
|
DEC_DDFD: // except for CB and EB these all act the same H and L get modified by prefix
|
1183 |
|
|
case (mem_exec_dec)
|
1184 |
|
|
I1_CB : next_state = {DEC_PFxCB,MEM_IFPP1, IPIPE_EN1};// IF2_NOP -> nn <= (MEM)
|
1185 |
|
|
I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1};
|
1186 |
|
|
I1_ED : next_state = {DEC_ED, MEM_IFPP1, IPIPE_EN1};//How do we clear the prefix?
|
1187 |
|
|
I1_JMP : next_state = {DEC_IF2, MEM_JMPHL, IPIPE_NOP};
|
1188 |
|
|
I1_N : next_state = {DEC_N, MEM_IFPP1, IPIPE_ENN};
|
1189 |
|
|
I1_NN : next_state = {DEC_NN, MEM_IFPP1, IPIPE_ENN};
|
1190 |
|
|
I1_OF : next_state = {DEC_DDOF, MEM_IFPP1, IPIPE_ENN}; // d to nn - need to get d
|
1191 |
|
|
// LD A,(BC) LD A,(DE) will
|
1192 |
|
|
// become ix+d - do we care ?
|
1193 |
|
|
// i hope not
|
1194 |
|
|
I1_OS : next_state = {DEC_DDOS, MEM_IFPP1, IPIPE_ENN}; // d to nn
|
1195 |
|
|
I1_POP : next_state = {DEC_POP, MEM_OFSP, IPIPE_EN12};
|
1196 |
|
|
I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP, IPIPE_EN12};
|
1197 |
|
|
I1_RET : next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12};
|
1198 |
|
|
I1_RMW : next_state = {DEC_RMW, MEM_OF1, IPIPE_EN12};
|
1199 |
|
|
I1_RST : next_state = {DEC_IF2, MEM_IFRST, IPIPE_NOP}; // just dump next inst
|
1200 |
|
|
I1_R2R : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R
|
1201 |
|
|
default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R
|
1202 |
|
|
endcase
|
1203 |
|
|
DEC_ED:
|
1204 |
|
|
if (ed_nn) next_state = {DEC_EDNN1, MEM_IFPP1, IPIPE_ENN};
|
1205 |
|
|
// we need to set inc and io and repeat flags on this state for continued block
|
1206 |
|
|
// processing -- keep the states of this machine somewhat manageable.
|
1207 |
|
|
else if (ed_blk_cp ) next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_EN12};// MEM_OFHL_PM triggers --BC
|
1208 |
|
|
else if (ed_blk_in ) next_state = {DEC_EDBIN1, MEM_IOF_C, IPIPE_EN12};// MEM_IOF_C triggers --B
|
1209 |
|
|
else if (ed_blk_out) next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_EN12};
|
1210 |
|
|
else if (ed_blk_mv ) next_state = {DEC_EDBMV1, MEM_OFHL_PM, IPIPE_EN12};
|
1211 |
|
|
else if (ed_retn ) next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12};// see int logic below
|
1212 |
|
|
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};
|
1213 |
|
|
// double register reads and writes here
|
1214 |
|
|
DEC_EDNN1: next_state = {DEC_EDNN2, MEM_NOP, IPIPE_ENN}; // address to nn
|
1215 |
|
|
DEC_EDNN2:
|
1216 |
|
|
if (ed_dbl_rd) next_state = {DEC_EDRD1, MEM_OFNN, IPIPE_NOP};
|
1217 |
|
|
else next_state = {DEC_EDWR, MEM_OSNN, IPIPE_NOP};// OSNN selects data ok?
|
1218 |
|
|
DEC_EDRD1: next_state = {DEC_EDRD2, MEM_OFADRP1, IPIPE_ENN}; // 1st byte 2n
|
1219 |
|
|
DEC_EDRD2: next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2}; // 2nd byte 2nn
|
1220 |
|
|
DEC_EDWR: next_state = {DEC_IF1, MEM_OSADRP1, IPIPE_NOP};
|
1221 |
|
|
|
1222 |
|
|
// ED block moves
|
1223 |
|
|
DEC_EDBCP1:
|
1224 |
|
|
if (blk_done) next_state = {DEC_EXEC, MEM_IFPP1,IPIPE_ENNA2};
|
1225 |
|
|
else if(wb_int) next_state = {DEC_INT1, MEM_NOP, IPIPE_ENNA2};
|
1226 |
|
|
else next_state = {DEC_EDBCP2, MEM_NOP, IPIPE_ENNA2};//set flags
|
1227 |
|
|
DEC_EDBCP2: next_state = {DEC_EDBCP3, MEM_NOP, IPIPE_NOP};//wait for fr. alu_out is slow
|
1228 |
|
|
DEC_EDBCP3: if (fr[7]) next_state = {DEC_EXEC , MEM_IFPP1, IPIPE_NOP};
|
1229 |
|
|
else next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_NOP};
|
1230 |
|
|
|
1231 |
|
|
DEC_EDBIN1: next_state = {DEC_EDBIN2, MEM_NOP, IPIPE_ENN};
|
1232 |
|
|
DEC_EDBIN2: if (blk_done) next_state = {DEC_IF2A, MEM_OSHL_PM,IPIPE_NOP}; // implies nn
|
1233 |
|
|
else if (wb_int) next_state = {DEC_INT1, MEM_OSHL_PM,IPIPE_NOP};
|
1234 |
|
|
else next_state = {DEC_EDBIN1,MEM_OSHL_PM,IPIPE_NOP};//set flags
|
1235 |
|
|
DEC_EDBIN3: next_state = {DEC_EDBIN1, MEM_IOF_C, IPIPE_NOP};
|
1236 |
|
|
|
1237 |
|
|
DEC_EDBOUT1: next_state = {DEC_EDBOUT2, MEM_NOP, IPIPE_ENN};
|
1238 |
|
|
DEC_EDBOUT2:if (blk_done) next_state = {DEC_EXEC, MEM_IOS_C,IPIPE_NOP};
|
1239 |
|
|
else if (wb_int) next_state = {DEC_INT1, MEM_IOS_C,IPIPE_NOP}; // DEC_EDBOUT: if (blk_rpt)
|
1240 |
|
|
else next_state = {DEC_EDBOUT3,MEM_IOS_C,IPIPE_NOP};
|
1241 |
|
|
|
1242 |
|
|
DEC_EDBOUT3: next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_NOP};
|
1243 |
|
|
|
1244 |
|
|
DEC_EDBMV1: next_state = {DEC_EDBMV2, MEM_NOP, IPIPE_ENN};
|
1245 |
|
|
DEC_EDBMV2: if (blk_done) next_state = {DEC_EXEC, MEM_OSDE_PM,IPIPE_NOP};
|
1246 |
|
|
else if (wb_int) next_state = {DEC_INT1, MEM_OSDE_PM,IPIPE_NOP}; //DEC_EDBOUT: if (blk_rpt)
|
1247 |
|
|
else next_state = {DEC_EDBMV3,MEM_OSDE_PM,IPIPE_NOP};
|
1248 |
|
|
|
1249 |
|
|
DEC_EDBMV3: next_state = {DEC_EDBMV1,MEM_OFHL_PM, IPIPE_NOP};
|
1250 |
|
|
|
1251 |
|
|
DEC_N:
|
1252 |
|
|
if (INsA_6N7== ir1) next_state = {DEC_NIN, MEM_IOF_N, IPIPE_EN12};
|
1253 |
|
|
else if (OUTs6N7_A==ir1) next_state = {DEC_IF1, MEM_IOS_N, IPIPE_EN12};
|
1254 |
|
|
else if (LDs6HL7_N==ir1) next_state = {DEC_IF1, MEM_OS_HL_N, IPIPE_EN12};
|
1255 |
|
|
else if (jmpr_true) next_state = {DEC_IF2, MEM_IFREL_N, IPIPE_NOP};
|
1256 |
|
|
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};//r2r or false jumps
|
1257 |
|
|
DEC_NIN: next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2};
|
1258 |
|
|
|
1259 |
|
|
|
1260 |
|
|
//ISSUES: LDsSP_NN - load commanded from ir2 decode? and mechaninsm for updating PC on
|
1261 |
|
|
// JMP and CALL
|
1262 |
|
|
// on CALL We have IFNN for JMP
|
1263 |
|
|
// For CALL Use MEM_CALL to transfer pc<=nn, nn<=pc, adr<=sp then MEM_OSSP then IFPP1
|
1264 |
|
|
// For LDsSP_NN yes update from ir2 decode.
|
1265 |
|
|
DEC_NN:
|
1266 |
|
|
if (callnn_true) next_state = {DEC_NNCALL1, MEM_NOP, IPIPE_ENN}; // this gets new adr in nn
|
1267 |
|
|
// if we store from nn we can't do
|
1268 |
|
|
// a mem op now
|
1269 |
|
|
|
1270 |
|
|
else if (jmpnn_true) next_state = {DEC_NNJMP, MEM_NOP, IPIPE_ENN}; // gotta get nn before we can
|
1271 |
|
|
// transfer to adr.
|
1272 |
|
|
else if (LDs6NN7_A==ir1) next_state = {DEC_NNOS3, MEM_IFPP1, IPIPE_ENN};
|
1273 |
|
|
else if (LDs6NN7_HL==ir1) next_state = {DEC_NNOS1, MEM_IFPP1, IPIPE_ENN};
|
1274 |
|
|
else if (LDsA_6NN7==ir1) next_state = {DEC_NNOF3, MEM_IFPP1, IPIPE_ENN};
|
1275 |
|
|
else if (LDsHL_6NN7==ir1) next_state = {DEC_NNOF1, MEM_IFPP1, IPIPE_ENN};
|
1276 |
|
|
else next_state = { DEC_IF2, MEM_IFPP1, IPIPE_ENNEN2A2};
|
1277 |
|
|
|
1278 |
|
|
DEC_NNCALL1: next_state = {DEC_NNCALL2, MEM_CALL , IPIPE_NOP};
|
1279 |
|
|
DEC_NNCALL2: next_state = {DEC_IF1, MEM_OSSP, IPIPE_ENN};//A1 activates r2r xfers from ir1
|
1280 |
|
|
DEC_NNJMP: next_state = {DEC_IF2, MEM_IFNN , IPIPE_NOP};
|
1281 |
|
|
|
1282 |
|
|
// ISSUE: we blow out ir1 here - so need to keep some status to execute OSNN2.
|
1283 |
|
|
// general solution if not DEC_EXEC we get op frmo nn high byte.
|
1284 |
|
|
// note that first MEM_OSNN trabsferrs nn to wb_adr.
|
1285 |
|
|
DEC_NNOS1: next_state = {DEC_NNOS2, MEM_OSNN, IPIPE_EN1};
|
1286 |
|
|
DEC_NNOS2: next_state = {DEC_IF2A, MEM_OSNN, IPIPE_NOP};
|
1287 |
|
|
DEC_NNOS3: next_state = {DEC_IF2A, MEM_OSNN, IPIPE_EN1};
|
1288 |
|
|
|
1289 |
|
|
DEC_NNOF1: next_state = {DEC_NNOF2, MEM_OFNN, IPIPE_EN12};
|
1290 |
|
|
DEC_NNOF2: next_state = {DEC_NNOF4, MEM_OFNN, IPIPE_ENN};
|
1291 |
|
|
DEC_NNOF3: next_state = {DEC_NNOF4, MEM_OFNN, IPIPE_EN12};
|
1292 |
|
|
DEC_NNOF4: next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_ENNA2};
|
1293 |
|
|
|
1294 |
|
|
DEC_DDOS: next_state = {DEC_IF2A, MEM_OSIXpD, IPIPE_EN12};
|
1295 |
|
|
DEC_DDOF: next_state = {DEC_OF , MEM_OFIXpD, IPIPE_EN12};
|
1296 |
|
|
|
1297 |
|
|
|
1298 |
|
|
DEC_OF: next_state = {DEC_EXEC, MEM_IFPP1 , IPIPE_ENNA2};
|
1299 |
|
|
DEC_POP: next_state = {DEC_NNOF4, MEM_OFSP, IPIPE_ENN };
|
1300 |
|
|
DEC_PUSH: next_state = {DEC_IF2A , MEM_OSSP, IPIPE_NOP };
|
1301 |
|
|
|
1302 |
|
|
|
1303 |
|
|
DEC_RET: next_state = { DEC_RET2, MEM_OFSP, IPIPE_ENN };
|
1304 |
|
|
DEC_RET2: next_state = { DEC_NNCALL2, MEM_NOP, IPIPE_ENN };
|
1305 |
|
|
// blow off a tick so we don't gronk adr
|
1306 |
|
|
DEC_RMW: next_state = {DEC_RMW2, MEM_NOP, IPIPE_ENNA2}; //activate
|
1307 |
|
|
DEC_RMW2: next_state = {DEC_IF1 , MEM_OSADR, IPIPE_NOP }; // from nn
|
1308 |
|
|
|
1309 |
|
|
|
1310 |
|
|
// IF memory -- rmw else these are all reg 2 reg
|
1311 |
|
|
DEC_CBM: if (CB_BIT==ir1[9:6]) next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2};
|
1312 |
|
|
else next_state = {DEC_RMW2 , MEM_NOP, IPIPE_ENNA2};
|
1313 |
|
|
|
1314 |
|
|
// The DDCB anf FDCB all assume memory operands
|
1315 |
|
|
// These beauties always rmw memory. If a register op is default, they also
|
1316 |
|
|
// update the register. Programmers think of this as 2 ops for the price of 1.
|
1317 |
|
|
// unfortunately it is 2 ops for the price of 4.-- its not the number of lines
|
1318 |
|
|
// of assembler code that count but the number of bytes assembled. Oh well I signed
|
1319 |
|
|
// up for this...... and had a notion of what I was getting into.
|
1320 |
|
|
//
|
1321 |
|
|
DEC_PFxCB: next_state = { DEC_PFxCB2, MEM_IFPP1, IPIPE_ENN}; // this gets d
|
1322 |
|
|
DEC_PFxCB2: next_state = { DEC_PFxCB3, MEM_OFIXpD, IPIPE_EN1}; //actual inst
|
1323 |
|
|
DEC_PFxCB3: next_state = { DEC_PFxCB4, MEM_IFPP1, IPIPE_ENNEN2A2};
|
1324 |
|
|
DEC_PFxCB4: next_state = { DEC_IF2A, MEM_OSADR, IPIPE_EN1}; //execute ir2
|
1325 |
|
|
|
1326 |
|
|
// crap gotta subtract 2 (we always increment pc 2 times relative to the inst
|
1327 |
|
|
// that got interrupted. also can't push and dec pc without 2 adders.
|
1328 |
|
|
// choices: 1) fix up pc in 2 ticks 2) fix in 1 tick 3) add adder and do it fast
|
1329 |
|
|
// if there's anyone who knows is there anyone who cares.
|
1330 |
|
|
// guess I'll do it fast -- just a 16 bit subtractor. heck silicon is
|
1331 |
|
|
// cheap.
|
1332 |
|
|
DEC_INT1: next_state <= {DEC_INT2, MEM_OSSP_PCM2, IPIPE_NOP}; //must derement PC
|
1333 |
|
|
DEC_INT2: next_state <= {DEC_INT3, MEM_OSSP_P, IPIPE_NOP}; //must dec sp and PC 2 ops?
|
1334 |
|
|
DEC_INT3: next_state <= {DEC_INT4, MEM_INTA, IPIPE_NOP};
|
1335 |
|
|
DEC_INT4: next_state <= {DEC_INT5, MEM_NOP, IPIPE_ENN};
|
1336 |
|
|
DEC_INT5: next_state <= {DEC_IF2, MEM_IFINT, IPIPE_NOP};
|
1337 |
|
|
default: next_state <= {DEC_IDLE, MEM_NOP, IPIPE_NOP};
|
1338 |
|
|
endcase
|
1339 |
|
|
end
|
1340 |
|
|
|
1341 |
|
|
|
1342 |
|
|
always @(posedge clk or posedge rst)
|
1343 |
|
|
if (rst) dec_state <= DEC_IDLE;
|
1344 |
|
|
else if (wb_rdy_nhz ) dec_state <= next_dec_state;
|
1345 |
|
|
|
1346 |
|
|
|
1347 |
|
|
//-----------------------instruction register #1 ----------------------------------
|
1348 |
|
|
// // next_pipe_state {ir1,ir2,nn,act_ir2}
|
1349 |
|
|
|
1350 |
|
|
wire update_prefix = dec_state == DEC_EXEC | dec_state == DEC_DDFD;
|
1351 |
|
|
|
1352 |
|
|
always @(posedge clk or posedge rst)
|
1353 |
|
|
if (rst) ir1 <= NOP;
|
1354 |
|
|
else if (wb_rdy_nhz & next_pipe_state[3]) ir1 <= {2'b0, wb_dat_i} ;
|
1355 |
|
|
else if ( wb_rdy_nhz &update_prefix ) ir1 <= {ir1[7:0]==8'hed, ir1[7:0]==8'hcd, ir1[7:0]};
|
1356 |
|
|
|
1357 |
|
|
//----------- prefix states -----------------------------------------
|
1358 |
|
|
// strings of prefix insts are ignored up to last one. Also dded and fded are ignored
|
1359 |
|
|
// but ddcd and fdcd are defined prefix sets.
|
1360 |
|
|
//
|
1361 |
|
|
always @(posedge clk)
|
1362 |
|
|
if (wb_rdy_nhz & next_pipe_state[3]) {ir1dd, ir1fd } <= 2'b0;
|
1363 |
|
|
else if ( wb_rdy_nhz & update_prefix )
|
1364 |
|
|
{ir1dd, ir1fd } <= {ir1dd | (ir1[7:0]==8'hdd ) & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hfd),
|
1365 |
|
|
ir1fd | (ir1[7:0]==8'hfd ) & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hdd) };
|
1366 |
|
|
|
1367 |
|
|
//------------------- inst reg #2 -----------------------------------
|
1368 |
|
|
// This stuff is key to the data hazard logic. Hazards arise only AFTER activation of
|
1369 |
|
|
// a previous instruction. Fundamentally all state changes related to ir1 may be
|
1370 |
|
|
// delayed eithor by a delay in wb response, or by a hazard. Ir2 state changes
|
1371 |
|
|
// are keyed off exec_ir2 - and always happen immediately. ( exec_ir2 always is
|
1372 |
|
|
// immediately reset - unless of course a new instruction is transferred and executed.
|
1373 |
|
|
//
|
1374 |
|
|
//
|
1375 |
|
|
//
|
1376 |
|
|
always @(posedge clk or posedge rst)
|
1377 |
|
|
if (rst) ir2 <= 10'h0;
|
1378 |
|
|
else if (wb_rdy_nhz & next_pipe_state[2]) ir2 <= ir1;
|
1379 |
|
|
|
1380 |
|
|
always @(posedge clk or posedge rst)
|
1381 |
|
|
if (rst)
|
1382 |
|
|
begin
|
1383 |
|
|
ir2dd <= 1'b0;
|
1384 |
|
|
ir2fd <= 1'b0;
|
1385 |
|
|
end
|
1386 |
|
|
else if (wb_rdy_nhz & next_pipe_state[2])
|
1387 |
|
|
begin
|
1388 |
|
|
ir2dd <= ir1dd;
|
1389 |
|
|
ir2fd <= ir1fd;
|
1390 |
|
|
end
|
1391 |
|
|
|
1392 |
|
|
always @(posedge clk )
|
1393 |
|
|
if (wb_rdy_nhz & next_pipe_state[0]) exec_ir2 <= 1'b1;
|
1394 |
|
|
else exec_ir2 <= 1'b0;
|
1395 |
|
|
|
1396 |
|
|
|
1397 |
|
|
|
1398 |
|
|
|
1399 |
|
|
|
1400 |
|
|
//--------------- block move flags ------------------------
|
1401 |
|
|
always @(posedge clk)
|
1402 |
|
|
if (dec_state == DEC_ED) blk_inc_flg <= dec_blk_inc;
|
1403 |
|
|
|
1404 |
|
|
always @(posedge clk)
|
1405 |
|
|
if (dec_state == DEC_ED) blk_rpt_flg <= dec_blk_rpt;
|
1406 |
|
|
|
1407 |
|
|
|
1408 |
|
|
always @(posedge clk)
|
1409 |
|
|
if (dec_state == DEC_ED) blk_io_flg <= dec_blk_io;
|
1410 |
|
|
|
1411 |
|
|
|
1412 |
|
|
//-------------------------- memory interface stuff ----------------------------
|
1413 |
|
|
|
1414 |
|
|
|
1415 |
|
|
// -- wb_adr
|
1416 |
|
|
always @(posedge clk) if (wb_rdy) wb_adr <= mux21;
|
1417 |
|
|
|
1418 |
|
|
// -- wb_we;
|
1419 |
|
|
|
1420 |
|
|
always @(posedge clk or posedge rst)
|
1421 |
|
|
if (rst) wb_we <= 1'b0;
|
1422 |
|
|
else if (wb_rdy_nhz) wb_we <= we_next;
|
1423 |
|
|
|
1424 |
|
|
|
1425 |
|
|
|
1426 |
|
|
// -- wb_cyc
|
1427 |
|
|
|
1428 |
|
|
wire no_wb_start = mem_idle | mem_halt | mem_op3 & blk_cmp_reg | mem_op1 & rmw_reg;
|
1429 |
|
|
always @(posedge clk or posedge rst)
|
1430 |
|
|
if (rst) wb_cyc <= 1'b0;
|
1431 |
|
|
else if (wb_rdy_nhz) wb_cyc <= next_mem_state != MEM_NOP ;
|
1432 |
|
|
|
1433 |
|
|
// -- wb_stb;
|
1434 |
|
|
|
1435 |
|
|
always @(posedge clk or posedge rst)
|
1436 |
|
|
if (rst) wb_stb <= 1'b0;
|
1437 |
|
|
else if (wb_rdy_nhz) wb_stb <= next_mem_state != MEM_NOP ;
|
1438 |
|
|
|
1439 |
|
|
|
1440 |
|
|
// -- wb_lock lets not worry about lock unless somebody thinks it matters.
|
1441 |
|
|
|
1442 |
|
|
// -- wb_tga_io
|
1443 |
|
|
always @(posedge clk or posedge rst)
|
1444 |
|
|
if (rst) wb_tga_io <= 2'b0;
|
1445 |
|
|
else if (wb_rdy_nhz)
|
1446 |
|
|
begin
|
1447 |
|
|
if (next_mem_state == MEM_IOF_C |
|
1448 |
|
|
next_mem_state == MEM_IOS_C |
|
1449 |
|
|
next_mem_state == MEM_IOF_N |
|
1450 |
|
|
next_mem_state == MEM_IOS_N ) wb_tga_io <= TAG_IO;
|
1451 |
|
|
|
1452 |
|
|
else if (next_mem_state == MEM_INTA ) wb_tga_io <= TAG_INT;
|
1453 |
|
|
else wb_tga_io <= 2'b0 ;
|
1454 |
|
|
end
|
1455 |
|
|
|
1456 |
|
|
//------------ the input-output data register (nn) -----------------------------------------
|
1457 |
|
|
// basicaly we store lsb's folowed by msb's
|
1458 |
|
|
// input is always to msb (of input regiser) first (if a 2 byte operand, lsb<=msb before transfer)
|
1459 |
|
|
// this gets nn to position { msb, lsb } before we execute 2 byte transfer.
|
1460 |
|
|
//
|
1461 |
|
|
// if we don't update - we byte swap as well as
|
1462 |
|
|
// when we read
|
1463 |
|
|
// IMPORTANT We store from MSB's so that on block moves read and write from same place.
|
1464 |
|
|
// this makes the output look somewhat bass-ackwards but who is looking?
|
1465 |
|
|
//
|
1466 |
|
|
// There is probably a simpler way to do this. Unfortunately there are a lot of
|
1467 |
|
|
// dependencies here. Ill continue as planned till it proves untractable.
|
1468 |
|
|
// Issue is that we are using ir1 to provide the op specification -- but in general
|
1469 |
|
|
// ir1 gets gronked before 2nd store (if it happens) - so we need to capture both
|
1470 |
|
|
// data first time OSIXpD OS1 OSSP, and MEM_OSNN
|
1471 |
|
|
//
|
1472 |
|
|
// on consideration lets make a flag flag_firstos that gets set on first store after
|
1473 |
|
|
// DEC_EXEC
|
1474 |
|
|
// ISSUE reads both here and in ir1 need to execute on wb_ack ?
|
1475 |
|
|
// I recall wb_ack must stay active until a change in cycle ?
|
1476 |
|
|
// need to review wb spec.
|
1477 |
|
|
//
|
1478 |
|
|
//issue: how is EXs6SP7_HL implemented -- it is known as a rmw - and only trick for this file is
|
1479 |
|
|
// that nn must be properly updates with ir2
|
1480 |
|
|
|
1481 |
|
|
always @(posedge clk or posedge rst)
|
1482 |
|
|
if (rst) flag_os1 <= 1'b0;
|
1483 |
|
|
else if ((DEC_EXEC == next_dec_state) & wb_rdy) flag_os1 <= 1'b0;
|
1484 |
|
|
else if ( we_next ) flag_os1 <= 1'b1;
|
1485 |
|
|
|
1486 |
|
|
|
1487 |
|
|
wire [15:0] pc_2 = pc - 16'h2;
|
1488 |
|
|
always @(posedge clk)
|
1489 |
|
|
if (wb_rdy_nhz)
|
1490 |
|
|
begin
|
1491 |
|
|
if ( we_next & flag_os1) nn <= { nn[7:0], nn[15:8] } ;
|
1492 |
|
|
else if(we_next & ( next_mem_state == MEM_CALL)) nn <= {pc[7:0], pc[15:8]};
|
1493 |
|
|
else if(we_next & ( next_mem_state == MEM_OSSP_PCM2)) nn <= {pc_2[7:0], pc_2[15:8]};
|
1494 |
|
|
else if(EXs6SP7_HL== ir2 & ir2dd & exec_ir2) nn <= ixr;
|
1495 |
|
|
else if(EXs6SP7_HL== ir2 & ir2fd & exec_ir2) nn <= iyr;
|
1496 |
|
|
else if(EXs6SP7_HL== ir2 & exec_ir2) nn <= hl;
|
1497 |
|
|
// these are the general cases with ir1 providing register specification
|
1498 |
|
|
else if(we_next & ( next_mem_state == MEM_OS1 |
|
1499 |
|
|
next_mem_state == MEM_OSIXpD |
|
1500 |
|
|
next_mem_state == MEM_OSSP |
|
1501 |
|
|
next_mem_state == MEM_OSNN ) )
|
1502 |
|
|
begin
|
1503 |
|
|
if (os_a) nn[15:8] <= ar;
|
1504 |
|
|
if (os_b) nn[15:8] <= br;
|
1505 |
|
|
if (os_c) nn <= {cr, br }; // use for PUSHsBC
|
1506 |
|
|
if (os_d) nn[15:8] <= dr;
|
1507 |
|
|
if (os_e) nn <= {er, dr }; // use for PUSHsDE
|
1508 |
|
|
if (os_h) nn[15:8] <= hr;
|
1509 |
|
|
if (os_l) nn <= {lr, hr }; // use for PUSHsHL
|
1510 |
|
|
if (os_f) nn <= {fr, ar }; // use for PUSHsAF
|
1511 |
|
|
end
|
1512 |
|
|
|
1513 |
|
|
else nn <= { wb_dat_i, nn[15:8] };
|
1514 |
|
|
end
|
1515 |
|
|
|
1516 |
|
|
|
1517 |
|
|
|
1518 |
|
|
//------------------- pc and sp ----------------------------------------------------
|
1519 |
|
|
always @(posedge clk or posedge rst)
|
1520 |
|
|
if (rst) pc <= 16'h0;
|
1521 |
|
|
else if (wb_rdy_nhz)
|
1522 |
|
|
begin
|
1523 |
|
|
if (next_mem_state == MEM_DECPC) pc <= pc - 16'h1; // decrementer could perhaps be shared.
|
1524 |
|
|
if (next_mem_state == MEM_IFPP1) pc <= adr_alu;
|
1525 |
|
|
if (next_mem_state == MEM_CALL ) pc <= nn; //Use MEM_CALL to exchange pc<=>nn
|
1526 |
|
|
if (next_mem_state == MEM_IFRST) pc <= src_mux;
|
1527 |
|
|
if (next_mem_state == MEM_JMPHL) pc <= src_mux;
|
1528 |
|
|
if (next_mem_state == MEM_IFNN ) pc <= src_mux;
|
1529 |
|
|
if (next_mem_state == MEM_IFINT) pc <= src_mux;
|
1530 |
|
|
end
|
1531 |
|
|
|
1532 |
|
|
//---------------------------------- sp -----------------------------------------------------
|
1533 |
|
|
//
|
1534 |
|
|
// with pc updates are always made from ir1 as the PC is so critical to instruction flow.
|
1535 |
|
|
// (this of course creates the possibility of an "inst_hazard" - where data is stored in an
|
1536 |
|
|
// instruction already fetched - see below)
|
1537 |
|
|
// with sp the situation is not so simple.
|
1538 |
|
|
// Issues - especially regarding hazards.
|
1539 |
|
|
//
|
1540 |
|
|
// LDsSP_NN this should be done from ir2 - no hazard as active state is ALWAYS IF2
|
1541 |
|
|
//
|
1542 |
|
|
// ADDsHL_SP The add is a pre-add so sp cannot be modified before inst is executed from ir2
|
1543 |
|
|
// DECsSP Just do it with ir1 at DEC_EXEC gotcha need -- IFPP1 in general use ir2 -> hazard
|
1544 |
|
|
// EXs6SP7_HL rmw - no change to sp - no issue here
|
1545 |
|
|
// INCsSP Just do it with ir1 at DEC_EXEC gotcha -- IFPP1 use ir2 -> hazard
|
1546 |
|
|
// LDsSP_HL do from ir1 and use standard hazard logic (if H or L is being
|
1547 |
|
|
// updated -- wait)
|
1548 |
|
|
//
|
1549 |
|
|
// ED_LDs6NN7_REG REG== SP // needs to be done from ir2
|
1550 |
|
|
// ED_LDsREG_6NN7 REG== SP // do from ir2 - no hazard as executed on IF2 - refill pipe
|
1551 |
|
|
|
1552 |
|
|
always @(posedge clk )
|
1553 |
|
|
if (exec_ir2 ) // this has priority of course
|
1554 |
|
|
begin
|
1555 |
|
|
if (LDsSP_NN == ir2) sp <= nn;
|
1556 |
|
|
if (ED_LDsREG_6NN7 == ir2) sp <= nn;
|
1557 |
|
|
if ( DECsSP == ir2 ) sp <= add16;
|
1558 |
|
|
if ( INCsSP == ir2 ) sp <= add16;
|
1559 |
|
|
end
|
1560 |
|
|
else if (wb_rdy_nhz)
|
1561 |
|
|
begin
|
1562 |
|
|
if ( DECsSP == ir1 & dec_state == DEC_EXEC) sp <= adr_alu;
|
1563 |
|
|
if ( INCsSP == ir1 & dec_state == DEC_EXEC) sp <= adr_alu;
|
1564 |
|
|
if ( LDsSP_HL == ir1 & dec_state == DEC_EXEC) sp <= {hr,lr};
|
1565 |
|
|
if (next_mem_state == MEM_OFSP ) sp <= adr_alu;
|
1566 |
|
|
if (next_mem_state == MEM_OSSP ) sp <= adr_alu;
|
1567 |
|
|
if (next_mem_state == MEM_OSSP_PCM2 ) sp <= adr_alu;
|
1568 |
|
|
if (next_mem_state == MEM_OSSP_P ) sp <= adr_alu;
|
1569 |
|
|
end
|
1570 |
|
|
//----------------- inst hazard logic ------------------------------------------
|
1571 |
|
|
|
1572 |
|
|
|
1573 |
|
|
|
1574 |
|
|
always @(posedge clk or posedge rst)
|
1575 |
|
|
if (rst) inst_haz <= 1'b0;
|
1576 |
|
|
else if (we_next & (pc - 16'h1) == mux21) inst_haz <= 1'b1;
|
1577 |
|
|
else if (dec_state == DEC_EXEC) inst_haz <= 1'b0; // highest priority interrupt
|
1578 |
|
|
|
1579 |
|
|
//-------------------- int logic ----------------------------------------
|
1580 |
|
|
// We have a wishbone interrupt system - which i guess does not preclude a
|
1581 |
|
|
// non-maskable interrupt...... but bottom line is that such an interrupt is
|
1582 |
|
|
// definately out of favor with current system thinking. Within an embedded system
|
1583 |
|
|
// ( the target application here ) a single interrupt controller capable of handeling
|
1584 |
|
|
// as many interrupts as desired is the best choice.
|
1585 |
|
|
// Therefore we enable only mode 2 interrupts and a single enable ff.
|
1586 |
|
|
//
|
1587 |
|
|
// This begs the question of what to do with the "RETI" instruction -- ED4D. We opt to
|
1588 |
|
|
// enable interrupts with this instruction (and all its "aliases").
|
1589 |
|
|
//
|
1590 |
|
|
always @(posedge clk or posedge rst)
|
1591 |
|
|
if (rst) int_en <= 1'b0;
|
1592 |
|
|
else if (wb_rdy_nhz)
|
1593 |
|
|
begin
|
1594 |
|
|
if ((dec_state == DEC_EXEC) & (DI== ir1)) int_en <= 1'b0;
|
1595 |
|
|
else if ((dec_state == DEC_EXEC) & en_int_next) int_en <= 1'b1;
|
1596 |
|
|
else if ((dec_state == DEC_ED) & ed_retn) int_en <= 1'b0;
|
1597 |
|
|
if (dec_state == DEC_INT1) int_en <= 1'b0;
|
1598 |
|
|
end
|
1599 |
|
|
|
1600 |
|
|
|
1601 |
|
|
always @(posedge clk or posedge rst)
|
1602 |
|
|
if (rst) en_int_next <=1'b0;
|
1603 |
|
|
else if (wb_rdy_nhz)
|
1604 |
|
|
begin
|
1605 |
|
|
if ((dec_state == DEC_EXEC) & (EI== ir1)) en_int_next <=1'b1;
|
1606 |
|
|
else if (dec_state == DEC_EXEC) en_int_next <=1'b0;
|
1607 |
|
|
end
|
1608 |
|
|
|
1609 |
|
|
always @(posedge clk)
|
1610 |
|
|
wb_irq_sync <= wb_int_rq;
|
1611 |
|
|
|
1612 |
|
|
assign wb_int = wb_irq_sync & int_en;
|
1613 |
|
|
|
1614 |
|
|
endmodule
|
1615 |
|
|
|