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Subversion Repositories test_project

[/] [test_project/] [trunk/] [backend/] [sim_lib.v] - Blame information for rev 25

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`timescale 1 ns / 100 ps
module GND
  (
   output Y
   );
   assign Y = 1'b0;
endmodule // GND
`timescale 1 ns / 100 ps
module VCC
  (
   output Y
   );
   assign Y = 1'b1;
endmodule // VCC
`timescale 1 ns / 100 ps
module CLKDLY
  (
   output GL,
   input CLK, DLYGL0, DLYGL1, DLYGL2,DLYGL3,DLYGL4
   );
   assign GL = ({DLYGL0,DLYGL1,DLYGL2,DLYGL3,DLYGL4}==5'b00000) ? CLK : 1'b0;
endmodule // CLKDLY
 
`timescale 1 ns / 100 ps
module AND2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = A & B;
 
endmodule // AND2
`timescale 1 ns / 100 ps
module AND2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A & B;
 
endmodule // AND2A
`timescale 1 ns / 100 ps
module AND2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A & !B;
 
endmodule // AND2B
`timescale 1 ns / 100 ps
module AND3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = A & B & C;
 
endmodule // AND3
`timescale 1 ns / 100 ps
module AND3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A & B & C;
 
endmodule // AND3A
`timescale 1 ns / 100 ps
`timescale 1 ns / 100 ps
module AND3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A & !B & C;
 
endmodule // AND3B
`timescale 1 ns / 100 ps
module AND3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A & !B & !C;
 
endmodule // AND3C
`timescale 1 ns / 100 ps
module NAND2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(A & B);
 
endmodule // NAND2
`timescale 1 ns / 100 ps
module NAND2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A & B);
 
endmodule // NAND2A
`timescale 1 ns / 100 ps
module NAND2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A & !B);
 
endmodule // NAND2B
`timescale 1 ns / 100 ps
module NAND3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(A & B & C);
 
endmodule // NAND3
`timescale 1 ns / 100 ps
module NAND3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A & B & C);
 
endmodule // NAND3A
`timescale 1 ns / 100 ps
module NAND3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A & !B & C);
 
endmodule // NAND3B
`timescale 1 ns / 100 ps
module NAND3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A & !B & !C);
 
endmodule // NAND3C
`timescale 1 ns / 100 ps
module OR2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = A | B;
 
endmodule // OR2
`timescale 1 ns / 100 ps
module OR2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A | B;
 
endmodule // OR2A
`timescale 1 ns / 100 ps
module OR2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A | !B;
 
endmodule // OR2B
`timescale 1 ns / 100 ps
module OR3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = A | B | C;
 
endmodule // OR3
`timescale 1 ns / 100 ps
module OR3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A | B | C;
 
endmodule // OR3A
`timescale 1 ns / 100 ps
module OR3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A | !B | C;
 
endmodule // OR3B
`timescale 1 ns / 100 ps
module OR3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A | !B | !C;
 
endmodule // OR3C
`timescale 1 ns / 100 ps
module NOR2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(A | B);
 
endmodule // NOR2
`timescale 1 ns / 100 ps
module NOR2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A | B);
 
endmodule // NOR2A
module NOR2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A | !B);
 
endmodule // NOR2B
`timescale 1 ns / 100 ps
module NOR3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(A | B | C);
 
endmodule // NOR2
`timescale 1 ns / 100 ps
module NOR3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A | B | C);
 
endmodule // NOR3A
`timescale 1 ns / 100 ps
module NOR3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A | !B | C);
 
endmodule // NOR3B
`timescale 1 ns / 100 ps
module NOR3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A | !B | !C);
 
endmodule // NOR3C
`timescale 1 ns / 100 ps
module XOR2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = A ^ B;
 
endmodule // XOR2
`timescale 1 ns / 100 ps
module XOR2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A ^ B;
 
endmodule // XOR2A
`timescale 1 ns / 100 ps
module XOR2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !A ^ !B;
 
endmodule // XOR2B
`timescale 1 ns / 100 ps
module XOR3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = A ^ B ^ C;
 
endmodule // XOR3
`timescale 1 ns / 100 ps
module XOR3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A ^ B ^ C;
 
endmodule // XOR3A
module XOR3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A ^ !B ^ C;
 
endmodule // XOR3B
`timescale 1 ns / 100 ps
module XOR3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !A ^ !B ^ !C;
 
endmodule // XOR3C
`timescale 1 ns / 100 ps
module XNOR2
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(A ^ B);
 
endmodule // XNOR2
`timescale 1 ns / 100 ps
module XNOR2A
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A ^ B);
 
endmodule // XNOR2A
`timescale 1 ns / 100 ps
module XNOR2B
  (
   input  A,B,
   output Y
   );
 
   assign #1 Y = !(!A ^ !B);
 
endmodule // XNOR2B
`timescale 1 ns / 100 ps
module XNOR3
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(A ^ B ^ C);
 
endmodule // XNOR3
`timescale 1 ns / 100 ps
module XNOR3A
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A ^ B ^ C);
 
endmodule // XNOR3A
`timescale 1 ns / 100 ps
module XNOR3B
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A ^ !B ^ C);
 
endmodule // XNOR3B
`timescale 1 ns / 100 ps
module XNOR3C
  (
   input  A,B,C,
   output Y
   );
 
   assign #1 Y = !(!A ^ !B ^ !C);
 
endmodule // XNOR3C
`timescale 1 ns / 100 ps
module MX2
  (
   input A,B,S,
   output Y
   );
   assign #1 Y = !S ? A : B;
endmodule // MX2
module MX2A
  (
   input A,B,S,
   output Y
   );
   assign #1 Y = !S ? !A : B;
endmodule // MX2A
`timescale 1 ns / 100 ps
module MX2B
  (
   input A,B,S,
   output Y
   );
   assign #1 Y = !S ? A : !B;
endmodule // MX2B
`timescale 1 ns / 100 ps
module MX2C
  (
   input A,B,S,
   output Y
   );
   assign #1 Y = !S ? !A : !B;
endmodule // MX2C
`timescale 1 ns / 100 ps
module AO1
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (A & B) | C;
endmodule // AO1
`timescale 1 ns / 100 ps
module AO1A
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & B) | C;
endmodule // AO1A
`timescale 1 ns / 100 ps
module AO1B
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (A & B) | !C;
endmodule // AO1B
`timescale 1 ns / 100 ps
module AO1C
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & B) | !C;
endmodule // AO1C
`timescale 1 ns / 100 ps
module AO1D
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & !B) | C;
endmodule // AO1D
`timescale 1 ns / 100 ps
module AO1E
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & !B) | !C;
endmodule // AO1E
`timescale 1 ns / 100 ps
module AOI1
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((A & B) | C);
endmodule // AOI1
`timescale 1 ns / 100 ps
module AOI1A
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & B) | C);
endmodule // AOI1A
`timescale 1 ns / 100 ps
module AOI1B
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((A & B) | !C);
endmodule // AOI1B
`timescale 1 ns / 100 ps
module AOI1C
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & B) | !C);
endmodule // AOI1C
module AOI1D
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & !B) | C);
endmodule // AOI1D
`timescale 1 ns / 100 ps
module AOI1E
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & !B) | !C);
endmodule // AOI1E
`timescale 1 ns / 100 ps
module AX1
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & B) ^ C;
endmodule // AX1
`timescale 1 ns / 100 ps
module AX1A
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & B) ^ C);
endmodule // AX1A
module AX1B
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (!A & !B) ^ C;
endmodule // AX1B
`timescale 1 ns / 100 ps
module AX1C
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (A & B) ^ C;
endmodule // AX1C
`timescale 1 ns / 100 ps
module AX1D
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((!A & !B) ^ C);
endmodule // AX1D
`timescale 1 ns / 100 ps
module AX1E
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((A & B) ^ C);
endmodule // AX1E
`timescale 1 ns / 100 ps
module OA1
  (
   input A,B,C,
   output Y
   );
  assign #1 Y = (A | B) & C;
endmodule // OA1
`timescale 1 ns / 100 ps
module OA1A
  (
   input A,B,C,
   output Y
   );
  assign #1 Y = (!A | B) & C;
endmodule // OA1A
`timescale 1 ns / 100 ps
module OA1B
  (
   input A,B,C,
   output Y
   );
  assign #1 Y = (A | B) & !C;
endmodule // OA1B
`timescale 1 ns / 100 ps
module OA1C
  (
   input A,B,C,
   output Y
   );
  assign #1 Y = (!A | B) & !C;
endmodule // OA1C
`timescale 1 ns / 100 ps
module CLKINT
  (
   input A,
   output Y
   );
   assign #1 Y = A;
endmodule // CLKINT
`timescale 1 ns / 100 ps
module OAI1
  (
   input A,B,C,
   output Y
   );
  assign #1 Y = !((A | B) & C);
endmodule // OAI1
`timescale 1 ns / 100 ps
module XA1B
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = (A ^ B) & !C;
endmodule // XA1B
`timescale 1 ns / 100 ps
module XAI1
  (
   input A,B,C,
   output Y
   );
   assign #1 Y = !((A ^ B) & C);
endmodule // XAI1
/////////////////////////////////////////////////////////////////////////////////
// DFF
`timescale 1 ns / 100 ps
module DFN1C0
  (
   output reg Q,
   input D,CLR,CLK
   );
   always @ (posedge CLK or negedge CLR)
     if (!CLR)
       Q <= #1 1'b0;
     else
       Q <= #1 D;
endmodule // DFN1C0
`timescale 1 ns / 100 ps
module DFN1C1
  (
   output reg Q,
   input D,CLR,CLK
   );
   always @ (posedge CLK or posedge CLR)
     if (CLR)
       Q <= #1 1'b0;
     else
       Q <= #1 D;
endmodule // DFN1C1
`timescale 1 ns / 100 ps
module DFN1P0
  (
   output reg Q,
   input D,PRE,CLK
   );
   always @ (posedge CLK or negedge PRE)
     if (!PRE)
       Q <= #1 1'b1;
     else
       Q <= #1 D;
endmodule // DFN1P1
`timescale 1 ns / 100 ps
module DFN1P1
  (
   output reg Q,
   input D,PRE,CLK
   );
   always @ (posedge CLK or posedge PRE)
     if (PRE)
       Q <= #1 1'b1;
     else
       Q <= #1 D;
endmodule // DFN1P1
`timescale 1 ns / 100 ps
module DFN1E0C1
  (
   output reg Q,
   input D,E,CLR,CLK
   );
   always @ (posedge CLK or posedge CLR)
     if (CLR)
       Q <= #1 1'b0;
     else if (!E)
       Q <= #1 D;
endmodule // DFN1E0C1
`timescale 1 ns / 100 ps
module DFN1E1C1
  (
   output reg Q,
   input D,E,CLR,CLK
   );
   always @ (posedge CLK or posedge CLR)
     if (CLR)
       Q <= #1 1'b0;
     else if (E)
       Q <= #1 D;
endmodule // DFN1E0C1
`timescale 1 ns / 100 ps
module DFN1E0P1
  (
   output reg Q,
   input D,E,PRE,CLK
   );
   always @ (posedge CLK or posedge PRE)
     if (PRE)
       Q <= #1 1'b1;
     else if (!E)
       Q <= #1 D;
endmodule // DFN1E0P1
`timescale 1 ns / 100 ps
module DFN1E1P1
  (
   output reg Q,
   input D,E,PRE,CLK
   );
   always @ (posedge CLK or posedge PRE)
     if (PRE)
       Q <= #1 1'b1;
     else if (E)
       Q <= #1 D;
endmodule // DFN1E1P1

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Subversion Repositories test_project

[/] [test_project/] [trunk/] [backend/] [sim_lib.v] - Blame information for rev 25

Line No.	Rev	Author	Line
1	16	unneback	`timescale 1 ns / 100 ps
2			`module GND`
3			`(`
4			`output Y`
5			`);`
6			`assign Y = 1'b0;`
7			`endmodule // GND`
8			`timescale 1 ns / 100 ps
9			`module VCC`
10			`(`
11			`output Y`
12			`);`
13			`assign Y = 1'b1;`
14	22	julius	`endmodule // VCC`
15	16	unneback	`timescale 1 ns / 100 ps
16			`module CLKDLY`
17			`(`
18			`output GL,`
19			`input CLK, DLYGL0, DLYGL1, DLYGL2,DLYGL3,DLYGL4`
20			`);`
21			`assign GL = ({DLYGL0,DLYGL1,DLYGL2,DLYGL3,DLYGL4}==5'b00000) ? CLK : 1'b0;`
22			`endmodule // CLKDLY`
23
24			`timescale 1 ns / 100 ps
25			`module AND2`
26			`(`
27			`input A,B,`
28			`output Y`
29			`);`
30
31			`assign #1 Y = A & B;`
32
33			`endmodule // AND2`
34			`timescale 1 ns / 100 ps
35			`module AND2A`
36			`(`
37			`input A,B,`
38			`output Y`
39			`);`
40
41			`assign #1 Y = !A & B;`
42
43			`endmodule // AND2A`
44			`timescale 1 ns / 100 ps
45			`module AND2B`
46			`(`
47			`input A,B,`
48			`output Y`
49			`);`
50
51			`assign #1 Y = !A & !B;`
52
53			`endmodule // AND2B`
54			`timescale 1 ns / 100 ps
55			`module AND3`
56			`(`
57			`input A,B,C,`
58			`output Y`
59			`);`
60
61			`assign #1 Y = A & B & C;`
62
63			`endmodule // AND3`
64			`timescale 1 ns / 100 ps
65			`module AND3A`
66			`(`
67			`input A,B,C,`
68			`output Y`
69			`);`
70
71			`assign #1 Y = !A & B & C;`
72
73			`endmodule // AND3A`
74			`timescale 1 ns / 100 ps
75			`timescale 1 ns / 100 ps
76			`module AND3B`
77			`(`
78			`input A,B,C,`
79			`output Y`
80			`);`
81
82			`assign #1 Y = !A & !B & C;`
83
84			`endmodule // AND3B`
85			`timescale 1 ns / 100 ps
86			`module AND3C`
87			`(`
88			`input A,B,C,`
89			`output Y`
90			`);`
91
92			`assign #1 Y = !A & !B & !C;`
93
94			`endmodule // AND3C`
95			`timescale 1 ns / 100 ps
96			`module NAND2`
97			`(`
98			`input A,B,`
99			`output Y`
100			`);`
101
102			`assign #1 Y = !(A & B);`
103
104			`endmodule // NAND2`
105			`timescale 1 ns / 100 ps
106			`module NAND2A`
107			`(`
108			`input A,B,`
109			`output Y`
110			`);`
111
112			`assign #1 Y = !(!A & B);`
113
114			`endmodule // NAND2A`
115			`timescale 1 ns / 100 ps
116			`module NAND2B`
117			`(`
118			`input A,B,`
119			`output Y`
120			`);`
121
122			`assign #1 Y = !(!A & !B);`
123
124			`endmodule // NAND2B`
125			`timescale 1 ns / 100 ps
126			`module NAND3`
127			`(`
128			`input A,B,C,`
129			`output Y`
130			`);`
131
132			`assign #1 Y = !(A & B & C);`
133
134			`endmodule // NAND3`
135			`timescale 1 ns / 100 ps
136			`module NAND3A`
137			`(`
138			`input A,B,C,`
139			`output Y`
140			`);`
141
142			`assign #1 Y = !(!A & B & C);`
143
144			`endmodule // NAND3A`
145			`timescale 1 ns / 100 ps
146			`module NAND3B`
147			`(`
148			`input A,B,C,`
149			`output Y`
150			`);`
151
152			`assign #1 Y = !(!A & !B & C);`
153
154			`endmodule // NAND3B`
155			`timescale 1 ns / 100 ps
156			`module NAND3C`
157			`(`
158			`input A,B,C,`
159			`output Y`
160			`);`
161
162			`assign #1 Y = !(!A & !B & !C);`
163
164			`endmodule // NAND3C`
165			`timescale 1 ns / 100 ps
166			`module OR2`
167			`(`
168			`input A,B,`
169			`output Y`
170			`);`
171
172			`assign #1 Y = A \| B;`
173
174			`endmodule // OR2`
175			`timescale 1 ns / 100 ps
176			`module OR2A`
177			`(`
178			`input A,B,`
179			`output Y`
180			`);`
181
182			`assign #1 Y = !A \| B;`
183
184			`endmodule // OR2A`
185			`timescale 1 ns / 100 ps
186			`module OR2B`
187			`(`
188			`input A,B,`
189			`output Y`
190			`);`
191
192			`assign #1 Y = !A \| !B;`
193
194			`endmodule // OR2B`
195			`timescale 1 ns / 100 ps
196			`module OR3`
197			`(`
198			`input A,B,C,`
199			`output Y`
200			`);`
201
202			`assign #1 Y = A \| B \| C;`
203
204			`endmodule // OR3`
205			`timescale 1 ns / 100 ps
206			`module OR3A`
207			`(`
208			`input A,B,C,`
209			`output Y`
210			`);`
211
212			`assign #1 Y = !A \| B \| C;`
213
214			`endmodule // OR3A`
215			`timescale 1 ns / 100 ps
216			`module OR3B`
217			`(`
218			`input A,B,C,`
219			`output Y`
220			`);`
221
222			`assign #1 Y = !A \| !B \| C;`
223
224			`endmodule // OR3B`
225			`timescale 1 ns / 100 ps
226			`module OR3C`
227			`(`
228			`input A,B,C,`
229			`output Y`
230			`);`
231
232			`assign #1 Y = !A \| !B \| !C;`
233
234			`endmodule // OR3C`
235			`timescale 1 ns / 100 ps
236			`module NOR2`
237			`(`
238			`input A,B,`
239			`output Y`
240			`);`
241
242			`assign #1 Y = !(A \| B);`
243
244			`endmodule // NOR2`
245			`timescale 1 ns / 100 ps
246			`module NOR2A`
247			`(`
248			`input A,B,`
249			`output Y`
250			`);`
251
252			`assign #1 Y = !(!A \| B);`
253
254			`endmodule // NOR2A`
255			`module NOR2B`
256			`(`
257			`input A,B,`
258			`output Y`
259			`);`
260
261			`assign #1 Y = !(!A \| !B);`
262
263			`endmodule // NOR2B`
264			`timescale 1 ns / 100 ps
265			`module NOR3`
266			`(`
267			`input A,B,C,`
268			`output Y`
269			`);`
270
271			`assign #1 Y = !(A \| B \| C);`
272
273			`endmodule // NOR2`
274			`timescale 1 ns / 100 ps
275			`module NOR3A`
276			`(`
277			`input A,B,C,`
278			`output Y`
279			`);`
280
281			`assign #1 Y = !(!A \| B \| C);`
282
283			`endmodule // NOR3A`
284			`timescale 1 ns / 100 ps
285			`module NOR3B`
286			`(`
287			`input A,B,C,`
288			`output Y`
289			`);`
290
291			`assign #1 Y = !(!A \| !B \| C);`
292
293			`endmodule // NOR3B`
294			`timescale 1 ns / 100 ps
295			`module NOR3C`
296			`(`
297			`input A,B,C,`
298			`output Y`
299			`);`
300
301			`assign #1 Y = !(!A \| !B \| !C);`
302
303			`endmodule // NOR3C`
304			`timescale 1 ns / 100 ps
305			`module XOR2`
306			`(`
307			`input A,B,`
308			`output Y`
309			`);`
310
311			`assign #1 Y = A ^ B;`
312
313			`endmodule // XOR2`
314			`timescale 1 ns / 100 ps
315			`module XOR2A`
316			`(`
317			`input A,B,`
318			`output Y`
319			`);`
320
321			`assign #1 Y = !A ^ B;`
322
323			`endmodule // XOR2A`
324			`timescale 1 ns / 100 ps
325			`module XOR2B`
326			`(`
327			`input A,B,`
328			`output Y`
329			`);`
330
331			`assign #1 Y = !A ^ !B;`
332
333			`endmodule // XOR2B`
334			`timescale 1 ns / 100 ps
335			`module XOR3`
336			`(`
337			`input A,B,C,`
338			`output Y`
339			`);`
340
341			`assign #1 Y = A ^ B ^ C;`
342
343			`endmodule // XOR3`
344			`timescale 1 ns / 100 ps
345			`module XOR3A`
346			`(`
347			`input A,B,C,`
348			`output Y`
349			`);`
350
351			`assign #1 Y = !A ^ B ^ C;`
352
353			`endmodule // XOR3A`
354			`module XOR3B`
355			`(`
356			`input A,B,C,`
357			`output Y`
358			`);`
359
360			`assign #1 Y = !A ^ !B ^ C;`
361
362			`endmodule // XOR3B`
363			`timescale 1 ns / 100 ps
364			`module XOR3C`
365			`(`
366			`input A,B,C,`
367			`output Y`
368			`);`
369
370			`assign #1 Y = !A ^ !B ^ !C;`
371
372			`endmodule // XOR3C`
373			`timescale 1 ns / 100 ps
374			`module XNOR2`
375			`(`
376			`input A,B,`
377			`output Y`
378			`);`
379
380			`assign #1 Y = !(A ^ B);`
381
382			`endmodule // XNOR2`
383			`timescale 1 ns / 100 ps
384			`module XNOR2A`
385			`(`
386			`input A,B,`
387			`output Y`
388			`);`
389
390			`assign #1 Y = !(!A ^ B);`
391
392			`endmodule // XNOR2A`
393			`timescale 1 ns / 100 ps
394			`module XNOR2B`
395			`(`
396			`input A,B,`
397			`output Y`
398			`);`
399
400			`assign #1 Y = !(!A ^ !B);`
401
402			`endmodule // XNOR2B`
403			`timescale 1 ns / 100 ps
404			`module XNOR3`
405			`(`
406			`input A,B,C,`
407			`output Y`
408			`);`
409
410			`assign #1 Y = !(A ^ B ^ C);`
411
412			`endmodule // XNOR3`
413			`timescale 1 ns / 100 ps
414			`module XNOR3A`
415			`(`
416			`input A,B,C,`
417			`output Y`
418			`);`
419
420			`assign #1 Y = !(!A ^ B ^ C);`
421
422			`endmodule // XNOR3A`
423			`timescale 1 ns / 100 ps
424			`module XNOR3B`
425			`(`
426			`input A,B,C,`
427			`output Y`
428			`);`
429
430			`assign #1 Y = !(!A ^ !B ^ C);`
431
432			`endmodule // XNOR3B`
433			`timescale 1 ns / 100 ps
434			`module XNOR3C`
435			`(`
436			`input A,B,C,`
437			`output Y`
438			`);`
439
440			`assign #1 Y = !(!A ^ !B ^ !C);`
441
442			`endmodule // XNOR3C`
443			`timescale 1 ns / 100 ps
444			`module MX2`
445			`(`
446			`input A,B,S,`
447			`output Y`
448			`);`
449			`assign #1 Y = !S ? A : B;`
450			`endmodule // MX2`
451			`module MX2A`
452			`(`
453			`input A,B,S,`
454			`output Y`
455			`);`
456			`assign #1 Y = !S ? !A : B;`
457			`endmodule // MX2A`
458			`timescale 1 ns / 100 ps
459			`module MX2B`
460			`(`
461			`input A,B,S,`
462			`output Y`
463			`);`
464			`assign #1 Y = !S ? A : !B;`
465			`endmodule // MX2B`
466			`timescale 1 ns / 100 ps
467			`module MX2C`
468			`(`
469			`input A,B,S,`
470			`output Y`
471			`);`
472			`assign #1 Y = !S ? !A : !B;`
473			`endmodule // MX2C`
474			`timescale 1 ns / 100 ps
475			`module AO1`
476			`(`
477			`input A,B,C,`
478			`output Y`
479			`);`
480			`assign #1 Y = (A & B) \| C;`
481			`endmodule // AO1`
482			`timescale 1 ns / 100 ps
483			`module AO1A`
484			`(`
485			`input A,B,C,`
486			`output Y`
487			`);`
488			`assign #1 Y = (!A & B) \| C;`
489			`endmodule // AO1A`
490			`timescale 1 ns / 100 ps
491			`module AO1B`
492			`(`
493			`input A,B,C,`
494			`output Y`
495			`);`
496			`assign #1 Y = (A & B) \| !C;`
497			`endmodule // AO1B`
498			`timescale 1 ns / 100 ps
499			`module AO1C`
500			`(`
501			`input A,B,C,`
502			`output Y`
503			`);`
504			`assign #1 Y = (!A & B) \| !C;`
505			`endmodule // AO1C`
506			`timescale 1 ns / 100 ps
507			`module AO1D`
508			`(`
509			`input A,B,C,`
510			`output Y`
511			`);`
512			`assign #1 Y = (!A & !B) \| C;`
513			`endmodule // AO1D`
514			`timescale 1 ns / 100 ps
515			`module AO1E`
516			`(`
517			`input A,B,C,`
518			`output Y`
519			`);`
520			`assign #1 Y = (!A & !B) \| !C;`
521			`endmodule // AO1E`
522			`timescale 1 ns / 100 ps
523			`module AOI1`
524			`(`
525			`input A,B,C,`
526			`output Y`
527			`);`
528			`assign #1 Y = !((A & B) \| C);`
529			`endmodule // AOI1`
530			`timescale 1 ns / 100 ps
531			`module AOI1A`
532			`(`
533			`input A,B,C,`
534			`output Y`
535			`);`
536			`assign #1 Y = !((!A & B) \| C);`
537			`endmodule // AOI1A`
538			`timescale 1 ns / 100 ps
539			`module AOI1B`
540			`(`
541			`input A,B,C,`
542			`output Y`
543			`);`
544			`assign #1 Y = !((A & B) \| !C);`
545			`endmodule // AOI1B`
546			`timescale 1 ns / 100 ps
547			`module AOI1C`
548			`(`
549			`input A,B,C,`
550			`output Y`
551			`);`
552			`assign #1 Y = !((!A & B) \| !C);`
553			`endmodule // AOI1C`
554			`module AOI1D`
555			`(`
556			`input A,B,C,`
557			`output Y`
558			`);`
559			`assign #1 Y = !((!A & !B) \| C);`
560			`endmodule // AOI1D`
561			`timescale 1 ns / 100 ps
562			`module AOI1E`
563			`(`
564			`input A,B,C,`
565			`output Y`
566			`);`
567			`assign #1 Y = !((!A & !B) \| !C);`
568			`endmodule // AOI1E`
569			`timescale 1 ns / 100 ps
570			`module AX1`
571			`(`
572			`input A,B,C,`
573			`output Y`
574			`);`
575			`assign #1 Y = (!A & B) ^ C;`
576			`endmodule // AX1`
577			`timescale 1 ns / 100 ps
578			`module AX1A`
579			`(`
580			`input A,B,C,`
581			`output Y`
582			`);`
583			`assign #1 Y = !((!A & B) ^ C);`
584			`endmodule // AX1A`
585			`module AX1B`
586			`(`
587			`input A,B,C,`
588			`output Y`
589			`);`
590			`assign #1 Y = (!A & !B) ^ C;`
591			`endmodule // AX1B`
592			`timescale 1 ns / 100 ps
593			`module AX1C`
594			`(`
595			`input A,B,C,`
596			`output Y`
597			`);`
598			`assign #1 Y = (A & B) ^ C;`
599			`endmodule // AX1C`
600			`timescale 1 ns / 100 ps
601			`module AX1D`
602			`(`
603			`input A,B,C,`
604			`output Y`
605			`);`
606			`assign #1 Y = !((!A & !B) ^ C);`
607			`endmodule // AX1D`
608			`timescale 1 ns / 100 ps
609			`module AX1E`
610			`(`
611			`input A,B,C,`
612			`output Y`
613			`);`
614			`assign #1 Y = !((A & B) ^ C);`
615			`endmodule // AX1E`
616			`timescale 1 ns / 100 ps
617			`module OA1`
618			`(`
619			`input A,B,C,`
620			`output Y`
621			`);`
622			`assign #1 Y = (A \| B) & C;`
623			`endmodule // OA1`
624			`timescale 1 ns / 100 ps
625			`module OA1A`
626			`(`
627			`input A,B,C,`
628			`output Y`
629			`);`
630			`assign #1 Y = (!A \| B) & C;`
631			`endmodule // OA1A`
632			`timescale 1 ns / 100 ps
633			`module OA1B`
634			`(`
635			`input A,B,C,`
636			`output Y`
637			`);`
638			`assign #1 Y = (A \| B) & !C;`
639			`endmodule // OA1B`
640			`timescale 1 ns / 100 ps
641			`module OA1C`
642			`(`
643			`input A,B,C,`
644			`output Y`
645			`);`
646			`assign #1 Y = (!A \| B) & !C;`
647			`endmodule // OA1C`
648			`timescale 1 ns / 100 ps
649			`module CLKINT`
650			`(`
651			`input A,`
652			`output Y`
653			`);`
654			`assign #1 Y = A;`
655			`endmodule // CLKINT`
656			`timescale 1 ns / 100 ps
657			`module OAI1`
658			`(`
659			`input A,B,C,`
660			`output Y`
661			`);`
662			`assign #1 Y = !((A \| B) & C);`
663			`endmodule // OAI1`
664			`timescale 1 ns / 100 ps
665			`module XA1B`
666			`(`
667			`input A,B,C,`
668			`output Y`
669			`);`
670			`assign #1 Y = (A ^ B) & !C;`
671			`endmodule // XA1B`
672			`timescale 1 ns / 100 ps
673			`module XAI1`
674			`(`
675			`input A,B,C,`
676			`output Y`
677			`);`
678			`assign #1 Y = !((A ^ B) & C);`
679			`endmodule // XAI1`
680			`/////////////////////////////////////////////////////////////////////////////////`
681			`// DFF`
682			`timescale 1 ns / 100 ps
683			`module DFN1C0`
684			`(`
685			`output reg Q,`
686			`input D,CLR,CLK`
687			`);`
688			`always @ (posedge CLK or negedge CLR)`
689			`if (!CLR)`
690			`Q <= #1 1'b0;`
691			`else`
692			`Q <= #1 D;`
693			`endmodule // DFN1C0`
694			`timescale 1 ns / 100 ps
695			`module DFN1C1`
696			`(`
697			`output reg Q,`
698			`input D,CLR,CLK`
699			`);`
700			`always @ (posedge CLK or posedge CLR)`
701			`if (CLR)`
702			`Q <= #1 1'b0;`
703			`else`
704			`Q <= #1 D;`
705			`endmodule // DFN1C1`
706			`timescale 1 ns / 100 ps
707			`module DFN1P0`
708			`(`
709			`output reg Q,`
710			`input D,PRE,CLK`
711			`);`
712			`always @ (posedge CLK or negedge PRE)`
713			`if (!PRE)`
714			`Q <= #1 1'b1;`
715			`else`
716			`Q <= #1 D;`
717			`endmodule // DFN1P1`
718			`timescale 1 ns / 100 ps
719			`module DFN1P1`
720			`(`
721			`output reg Q,`
722			`input D,PRE,CLK`
723			`);`
724			`always @ (posedge CLK or posedge PRE)`
725			`if (PRE)`
726			`Q <= #1 1'b1;`
727			`else`
728			`Q <= #1 D;`
729			`endmodule // DFN1P1`
730			`timescale 1 ns / 100 ps
731			`module DFN1E0C1`
732			`(`
733			`output reg Q,`
734			`input D,E,CLR,CLK`
735			`);`
736			`always @ (posedge CLK or posedge CLR)`
737			`if (CLR)`
738			`Q <= #1 1'b0;`
739			`else if (!E)`
740			`Q <= #1 D;`
741			`endmodule // DFN1E0C1`
742			`timescale 1 ns / 100 ps
743			`module DFN1E1C1`
744			`(`
745			`output reg Q,`
746			`input D,E,CLR,CLK`
747			`);`
748			`always @ (posedge CLK or posedge CLR)`
749			`if (CLR)`
750			`Q <= #1 1'b0;`
751			`else if (E)`
752			`Q <= #1 D;`
753			`endmodule // DFN1E0C1`
754			`timescale 1 ns / 100 ps
755			`module DFN1E0P1`
756			`(`
757			`output reg Q,`
758			`input D,E,PRE,CLK`
759			`);`
760			`always @ (posedge CLK or posedge PRE)`
761			`if (PRE)`
762			`Q <= #1 1'b1;`
763			`else if (!E)`
764			`Q <= #1 D;`
765			`endmodule // DFN1E0P1`
766			`timescale 1 ns / 100 ps
767			`module DFN1E1P1`
768			`(`
769			`output reg Q,`
770			`input D,E,PRE,CLK`
771			`);`
772			`always @ (posedge CLK or posedge PRE)`
773			`if (PRE)`
774			`Q <= #1 1'b1;`
775			`else if (E)`
776			`Q <= #1 D;`
777			`endmodule // DFN1E1P1`