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[/] [test_project/] [trunk/] [bench/] [verilog/] [clk_gen.v] - Blame information for rev 22

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module clk_gen
  (
   input POWERDOWN,
   input CLKA,
   output LOCK,
   output GLA,
   output GLB,
   output GLC
   );
 
   assign LOCK = POWERDOWN;
   assign GLA = CLKA;
   assign GLB = 1'b0;
   assign GLC = 1'b0;
endmodule // clk_gen

Line No.	Rev	Author	Line
1	15	unneback	`module clk_gen`
2			`(`
3			`input POWERDOWN,`
4			`input CLKA,`
5			`output LOCK,`
6			`output GLA,`
7			`output GLB,`
8			`output GLC`
9			`);`
10
11			`assign LOCK = POWERDOWN;`
12			`assign GLA = CLKA;`
13			`assign GLB = 1'b0;`
14			`assign GLC = 1'b0;`
15			`endmodule // clk_gen`

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[/] [test_project/] [trunk/] [bench/] [verilog/] [clk_gen.v] - Blame information for rev 22