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[/] [test_project/] [trunk/] [bench/] [verilog/] [mt48lc16m16a2.v] - Blame information for rev 22

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1 22 julius 
/**************************************************************************
2 
*
3 
*    File Name:  MT48LC16M16A2.V
4 
*      Version:  2.1
5 
*         Date:  June 6th, 2002
6 
*        Model:  BUS Functional
7 
*    Simulator:  Model Technology
8 
*
9 
* Dependencies:  None
10 
*
11 
*        Email:  modelsupport@micron.com
12 
*      Company:  Micron Technology, Inc.
13 
*        Model:  MT48LC16M16A2 (4Meg x 16 x 4 Banks)
14 
*
15 
*  Description:  Micron 256Mb SDRAM Verilog model
16 
*
17 
*   Limitation:  - Doesn't check for 8192 cycle refresh
18 
*
19 
*         Note:  - Set simulator resolution to "ps" accuracy
20 
*                - Set Debug = 0 to disable $display messages
21 
*
22 
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
23 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
24 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
25 
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
26 
*
27 
*                Copyright © 2001 Micron Semiconductor Products, Inc.
28 
*                All rights researved
29 
*
30 
* Rev  Author          Date        Changes
31 
* ---  --------------------------  ---------------------------------------
32 
* 2.1  SH              06/06/2002  - Typo in bank multiplex
33 
*      Micron Technology Inc.
34 
*
35 
* 2.0  SH              04/30/2002  - Second release
36 
*      Micron Technology Inc.
37 
*
38 
**************************************************************************/
39 
 
40 15 unneback 
`timescale 1ns / 1ps
41 
 
42 22 julius 
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
43 
 
44 
    parameter addr_bits =      13;
45 
    parameter data_bits =      16;
46 
    parameter col_bits  =       9;
47 
    parameter mem_sizes = 4194303;
48 
 
49 
    inout     [data_bits - 1 : 0] Dq;
50 
    input     [addr_bits - 1 : 0] Addr;
51 
    input                 [1 : 0] Ba;
52 
    input                         Clk;
53 
    input                         Cke;
54 
    input                         Cs_n;
55 
    input                         Ras_n;
56 
    input                         Cas_n;
57 
    input                         We_n;
58 
    input                 [1 : 0] Dqm;
59 
 
60 
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
61 
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
62 
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
63 
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
64 
 
65 
    reg                   [1 : 0] Bank_addr [0 : 3];                // Bank Address Pipeline
66 
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];                 // Column Address Pipeline
67 
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
68 
    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;               // DQM Operation Pipeline
69 
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
70 
 
71 
    reg       [addr_bits - 1 : 0] Mode_reg;
72 
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
73 
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;
74 
 
75 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;   // Bank Activate
76 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;       // Bank Precharge
77 
 
78 
    reg                   [1 : 0] Bank_precharge       [0 : 3];     // Precharge Command
79 
    reg                           A10_precharge        [0 : 3];     // Addr[10] = 1 (All banks)
80 
    reg                           Auto_precharge       [0 : 3];     // RW Auto Precharge (Bank)
81 
    reg                           Read_precharge       [0 : 3];     // R  Auto Precharge
82 
    reg                           Write_precharge      [0 : 3];     //  W Auto Precharge
83 
    reg                           RW_interrupt_read    [0 : 3];     // RW Interrupt Read with Auto Precharge
84 
    reg                           RW_interrupt_write   [0 : 3];     // RW Interrupt Write with Auto Precharge
85 
    reg                   [1 : 0] RW_interrupt_bank;                // RW Interrupt Bank
86 
    integer                       RW_interrupt_counter [0 : 3];     // RW Interrupt Counter
87 
    integer                       Count_precharge      [0 : 3];     // RW Auto Precharge Counter
88 
 
89 
    reg                           Data_in_enable;
90 
    reg                           Data_out_enable;
91 
 
92 
    reg                   [1 : 0] Bank, Prev_bank;
93 
    reg       [addr_bits - 1 : 0] Row;
94 
    reg        [col_bits - 1 : 0] Col, Col_brst;
95 
 
96 
    // Internal system clock
97 
    reg                           CkeZ, Sys_clk;
98 
 
99 
    // Commands Decode
100 
    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
101 
    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
102 
    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
103 
    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
104 
    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
105 
    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
106 
    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
107 
 
108 
    // Burst Length Decode
109 
    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
110 
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
111 
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
112 
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
113 
    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
114 
 
115 
    // CAS Latency Decode
116 
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
117 
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
118 
 
119 
    // Write Burst Mode
120 
    wire      Write_burst_mode = Mode_reg[9];
121 
 
122 
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
123 
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
124 
 
125 
    assign    Dq               = Dq_reg;                        // DQ buffer
126 
 
127 
    // Commands Operation
128 
    `define   ACT       0
129 
    `define   NOP       1
130 
    `define   READ      2
131 
    `define   WRITE     3
132 
    `define   PRECH     4
133 
    `define   A_REF     5
134 
    `define   BST       6
135 
    `define   LMR       7
136 
 
137 
    // Timing Parameters for -7E PC133 CL2
138 
    parameter tAC  =   5.4;
139 
    parameter tHZ  =   5.4;
140 
    parameter tOH  =   3.0;
141 
    parameter tMRD =   2.0;     // 2 Clk Cycles
142 
    parameter tRAS =  37.0;
143 
    parameter tRC  =  60.0;
144 
    parameter tRCD =  15.0;
145 
    parameter tRFC =  66.0;
146 
    parameter tRP  =  15.0;
147 
    parameter tRRD =  14.0;
148 
    parameter tWRa =   7.0;     // A2 Version - Auto precharge mode (1 Clk + 7 ns)
149 
    parameter tWRm =  14.0;     // A2 Version - Manual precharge mode (14 ns)
150 
 
151 
    // Timing Check variable
152 
    time  MRD_chk;
153 
    time  WR_chkm [0 : 3];
154 
    time  RFC_chk, RRD_chk;
155 
    time  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
156 
    time  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
157 
    time  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
158 
    time  RP_chk0, RP_chk1, RP_chk2, RP_chk3;
159 
 
160 
    initial begin
161 
        Dq_reg = {data_bits{1'bz}};
162 
        Data_in_enable = 0; Data_out_enable = 0;
163 
        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
164 
        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
165 
        WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
166 
        RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
167 
        RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
168 
        MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
169 
        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
170 
        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
171 
        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
172 
        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
173 
        $timeformat (-9, 1, " ns", 12);
174 
    end
175 
 
176 
    // System clock generator
177 
    always begin
178 
        @ (posedge Clk) begin
179 
            Sys_clk = CkeZ;
180 
            CkeZ = Cke;
181 
        end
182 
        @ (negedge Clk) begin
183 
            Sys_clk = 1'b0;
184 
        end
185 
    end
186 
 
187 
    always @ (posedge Sys_clk) begin
188 
        // Internal Commamd Pipelined
189 
        Command[0] = Command[1];
190 
        Command[1] = Command[2];
191 
        Command[2] = Command[3];
192 
        Command[3] = `NOP;
193 
 
194 
        Col_addr[0] = Col_addr[1];
195 
        Col_addr[1] = Col_addr[2];
196 
        Col_addr[2] = Col_addr[3];
197 
        Col_addr[3] = {col_bits{1'b0}};
198 
 
199 
        Bank_addr[0] = Bank_addr[1];
200 
        Bank_addr[1] = Bank_addr[2];
201 
        Bank_addr[2] = Bank_addr[3];
202 
        Bank_addr[3] = 2'b0;
203 
 
204 
        Bank_precharge[0] = Bank_precharge[1];
205 
        Bank_precharge[1] = Bank_precharge[2];
206 
        Bank_precharge[2] = Bank_precharge[3];
207 
        Bank_precharge[3] = 2'b0;
208 
 
209 
        A10_precharge[0] = A10_precharge[1];
210 
        A10_precharge[1] = A10_precharge[2];
211 
        A10_precharge[2] = A10_precharge[3];
212 
        A10_precharge[3] = 1'b0;
213 
 
214 
        // Dqm pipeline for Read
215 
        Dqm_reg0 = Dqm_reg1;
216 
        Dqm_reg1 = Dqm;
217 
 
218 
        // Read or Write with Auto Precharge Counter
219 
        if (Auto_precharge[0] === 1'b1) begin
220 
            Count_precharge[0] = Count_precharge[0] + 1;
221 
        end
222 
        if (Auto_precharge[1] === 1'b1) begin
223 
            Count_precharge[1] = Count_precharge[1] + 1;
224 
        end
225 
        if (Auto_precharge[2] === 1'b1) begin
226 
            Count_precharge[2] = Count_precharge[2] + 1;
227 
        end
228 
        if (Auto_precharge[3] === 1'b1) begin
229 
            Count_precharge[3] = Count_precharge[3] + 1;
230 
        end
231 
 
232 
        // Read or Write Interrupt Counter
233 
        if (RW_interrupt_write[0] === 1'b1) begin
234 
            RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
235 
        end
236 
        if (RW_interrupt_write[1] === 1'b1) begin
237 
            RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
238 
        end
239 
        if (RW_interrupt_write[2] === 1'b1) begin
240 
            RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
241 
        end
242 
        if (RW_interrupt_write[3] === 1'b1) begin
243 
            RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
244 
        end
245 
 
246 
        // tMRD Counter
247 
        MRD_chk = MRD_chk + 1;
248 
 
249 
        // Auto Refresh
250 
        if (Aref_enable === 1'b1) begin
251 
            if (Debug) begin
252 
                $display ("%m : at time %t AREF : Auto Refresh", $time);
253 
            end
254 
 
255 
            // Auto Refresh to Auto Refresh
256 
            if ($time - RFC_chk < tRFC) begin
257 
                $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
258 
            end
259 
 
260 
            // Precharge to Auto Refresh
261 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
262 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
263 
                $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
264 
            end
265 
 
266 
            // Precharge to Refresh
267 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
268 
                $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
269 
            end
270 
 
271 
            // Load Mode Register to Auto Refresh
272 
            if (MRD_chk < tMRD) begin
273 
                $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
274 
            end
275 
 
276 
            // Record Current tRFC time
277 
            RFC_chk = $time;
278 
        end
279 
 
280 
        // Load Mode Register
281 
        if (Mode_reg_enable === 1'b1) begin
282 
            // Register Mode
283 
            Mode_reg = Addr;
284 
 
285 
            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
286 
            if (Debug) begin
287 
                $display ("%m : at time %t LMR  : Load Mode Register", $time);
288 
                // CAS Latency
289 
                case (Addr[6 : 4])
290 
                    3'b010  : $display ("%m :                             CAS Latency      = 2");
291 
                    3'b011  : $display ("%m :                             CAS Latency      = 3");
292 
                    default : $display ("%m :                             CAS Latency      = Reserved");
293 
                endcase
294 
 
295 
                // Burst Length
296 
                case (Addr[2 : 0])
297 
                    3'b000  : $display ("%m :                             Burst Length     = 1");
298 
                    3'b001  : $display ("%m :                             Burst Length     = 2");
299 
                    3'b010  : $display ("%m :                             Burst Length     = 4");
300 
                    3'b011  : $display ("%m :                             Burst Length     = 8");
301 
                    3'b111  : $display ("%m :                             Burst Length     = Full");
302 
                    default : $display ("%m :                             Burst Length     = Reserved");
303 
                endcase
304 
 
305 
                // Burst Type
306 
                if (Addr[3] === 1'b0) begin
307 
                    $display ("%m :                             Burst Type       = Sequential");
308 
                end else if (Addr[3] === 1'b1) begin
309 
                    $display ("%m :                             Burst Type       = Interleaved");
310 
                end else begin
311 
                    $display ("%m :                             Burst Type       = Reserved");
312 
                end
313 
 
314 
                // Write Burst Mode
315 
                if (Addr[9] === 1'b0) begin
316 
                    $display ("%m :                             Write Burst Mode = Programmed Burst Length");
317 
                end else if (Addr[9] === 1'b1) begin
318 
                    $display ("%m :                             Write Burst Mode = Single Location Access");
319 
                end else begin
320 
                    $display ("%m :                             Write Burst Mode = Reserved");
321 
                end
322 
            end
323 
 
324 
            // Precharge to Load Mode Register
325 
            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
326 
                $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
327 
            end
328 
 
329 
            // Precharge to Load Mode Register
330 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
331 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
332 
                $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
333 
            end
334 
 
335 
            // Auto Refresh to Load Mode Register
336 
            if ($time - RFC_chk < tRFC) begin
337 
                $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
338 
            end
339 
 
340 
            // Load Mode Register to Load Mode Register
341 
            if (MRD_chk < tMRD) begin
342 
                $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
343 
            end
344 
 
345 
            // Reset MRD Counter
346 
            MRD_chk = 0;
347 
        end
348 
 
349 
        // Active Block (Latch Bank Address and Row Address)
350 
        if (Active_enable === 1'b1) begin
351 
            // Activate an open bank can corrupt data
352 
            if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
353 
                (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
354 
                $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
355 
            end
356 
 
357 
            // Activate Bank 0
358 
            if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
359 
                // Debug Message
360 
                if (Debug) begin
361 
                    $display ("%m : at time %t ACT  : Bank = 0 Row = %h", $time, Addr);
362 
                end
363 
 
364 
                // ACTIVE to ACTIVE command period
365 
                if ($time - RC_chk0 < tRC) begin
366 
                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
367 
                end
368 
 
369 
                // Precharge to Activate Bank 0
370 
                if ($time - RP_chk0 < tRP) begin
371 
                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
372 
                end
373 
 
374 
                // Record variables
375 
                Act_b0 = 1'b1;
376 
                Pc_b0 = 1'b0;
377 
                B0_row_addr = Addr [addr_bits - 1 : 0];
378 
                RAS_chk0 = $time;
379 
                RC_chk0 = $time;
380 
                RCD_chk0 = $time;
381 
            end
382 
 
383 
            if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
384 
                // Debug Message
385 
                if (Debug) begin
386 
                    $display ("%m : at time %t ACT  : Bank = 1 Row = %h", $time, Addr);
387 
                end
388 
 
389 
                // ACTIVE to ACTIVE command period
390 
                if ($time - RC_chk1 < tRC) begin
391 
                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
392 
                end
393 
 
394 
                // Precharge to Activate Bank 1
395 
                if ($time - RP_chk1 < tRP) begin
396 
                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
397 
                end
398 
 
399 
                // Record variables
400 
                Act_b1 = 1'b1;
401 
                Pc_b1 = 1'b0;
402 
                B1_row_addr = Addr [addr_bits - 1 : 0];
403 
                RAS_chk1 = $time;
404 
                RC_chk1 = $time;
405 
                RCD_chk1 = $time;
406 
            end
407 
 
408 
            if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
409 
                // Debug Message
410 
                if (Debug) begin
411 
                    $display ("%m : at time %t ACT  : Bank = 2 Row = %h", $time, Addr);
412 
                end
413 
 
414 
                // ACTIVE to ACTIVE command period
415 
                if ($time - RC_chk2 < tRC) begin
416 
                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
417 
                end
418 
 
419 
                // Precharge to Activate Bank 2
420 
                if ($time - RP_chk2 < tRP) begin
421 
                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
422 
                end
423 
 
424 
                // Record variables
425 
                Act_b2 = 1'b1;
426 
                Pc_b2 = 1'b0;
427 
                B2_row_addr = Addr [addr_bits - 1 : 0];
428 
                RAS_chk2 = $time;
429 
                RC_chk2 = $time;
430 
                RCD_chk2 = $time;
431 
            end
432 
 
433 
            if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
434 
                // Debug Message
435 
                if (Debug) begin
436 
                    $display ("%m : at time %t ACT  : Bank = 3 Row = %h", $time, Addr);
437 
                end
438 
 
439 
                // ACTIVE to ACTIVE command period
440 
                if ($time - RC_chk3 < tRC) begin
441 
                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
442 
                end
443 
 
444 
                // Precharge to Activate Bank 3
445 
                if ($time - RP_chk3 < tRP) begin
446 
                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
447 
                end
448 
 
449 
                // Record variables
450 
                Act_b3 = 1'b1;
451 
                Pc_b3 = 1'b0;
452 
                B3_row_addr = Addr [addr_bits - 1 : 0];
453 
                RAS_chk3 = $time;
454 
                RC_chk3 = $time;
455 
                RCD_chk3 = $time;
456 
            end
457 
 
458 
            // Active Bank A to Active Bank B
459 
            if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
460 
                $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %h", $time, Ba);
461 
            end
462 
 
463 
            // Auto Refresh to Activate
464 
            if ($time - RFC_chk < tRFC) begin
465 
                $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %h", $time, Ba);
466 
            end
467 
 
468 
            // Load Mode Register to Active
469 
            if (MRD_chk < tMRD ) begin
470 
                $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %h", $time, Ba);
471 
            end
472 
 
473 
            // Record variables for checking violation
474 
            RRD_chk = $time;
475 
            Prev_bank = Ba;
476 
        end
477 
 
478 
        // Precharge Block
479 
        if (Prech_enable == 1'b1) begin
480 
            // Load Mode Register to Precharge
481 
            if ($time - MRD_chk < tMRD) begin
482 
                $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
483 
            end
484 
 
485 
            // Precharge Bank 0
486 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
487 
                Act_b0 = 1'b0;
488 
                Pc_b0 = 1'b1;
489 
                RP_chk0 = $time;
490 
 
491 
                // Activate to Precharge
492 
                if ($time - RAS_chk0 < tRAS) begin
493 
                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
494 
                end
495 
 
496 
                // tWR violation check for write
497 
                if ($time - WR_chkm[0] < tWRm) begin
498 
                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
499 
                end
500 
            end
501 
 
502 
            // Precharge Bank 1
503 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
504 
                Act_b1 = 1'b0;
505 
                Pc_b1 = 1'b1;
506 
                RP_chk1 = $time;
507 
 
508 
                // Activate to Precharge
509 
                if ($time - RAS_chk1 < tRAS) begin
510 
                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
511 
                end
512 
 
513 
                // tWR violation check for write
514 
                if ($time - WR_chkm[1] < tWRm) begin
515 
                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
516 
                end
517 
            end
518 
 
519 
            // Precharge Bank 2
520 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
521 
                Act_b2 = 1'b0;
522 
                Pc_b2 = 1'b1;
523 
                RP_chk2 = $time;
524 
 
525 
                // Activate to Precharge
526 
                if ($time - RAS_chk2 < tRAS) begin
527 
                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
528 
                end
529 
 
530 
                // tWR violation check for write
531 
                if ($time - WR_chkm[2] < tWRm) begin
532 
                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
533 
                end
534 
            end
535 
 
536 
            // Precharge Bank 3
537 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
538 
                Act_b3 = 1'b0;
539 
                Pc_b3 = 1'b1;
540 
                RP_chk3 = $time;
541 
 
542 
                // Activate to Precharge
543 
                if ($time - RAS_chk3 < tRAS) begin
544 
                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
545 
                end
546 
 
547 
                // tWR violation check for write
548 
                if ($time - WR_chkm[3] < tWRm) begin
549 
                    $display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
550 
                end
551 
            end
552 
 
553 
            // Terminate a Write Immediately (if same bank or all banks)
554 
            if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
555 
                Data_in_enable = 1'b0;
556 
            end
557 
 
558 
            // Precharge Command Pipeline for Read
559 
            if (Cas_latency_3 === 1'b1) begin
560 
                Command[2] = `PRECH;
561 
                Bank_precharge[2] = Ba;
562 
                A10_precharge[2] = Addr[10];
563 
            end else if (Cas_latency_2 === 1'b1) begin
564 
                Command[1] = `PRECH;
565 
                Bank_precharge[1] = Ba;
566 
                A10_precharge[1] = Addr[10];
567 
            end
568 
        end
569 
 
570 
        // Burst terminate
571 
        if (Burst_term === 1'b1) begin
572 
            // Terminate a Write Immediately
573 
            if (Data_in_enable == 1'b1) begin
574 
                Data_in_enable = 1'b0;
575 
            end
576 
 
577 
            // Terminate a Read Depend on CAS Latency
578 
            if (Cas_latency_3 === 1'b1) begin
579 
                Command[2] = `BST;
580 
            end else if (Cas_latency_2 == 1'b1) begin
581 
                Command[1] = `BST;
582 
            end
583 
 
584 
            // Display debug message
585 
            if (Debug) begin
586 
                $display ("%m : at time %t BST  : Burst Terminate",$time);
587 
            end
588 
        end
589 
 
590 
        // Read, Write, Column Latch
591 
        if (Read_enable === 1'b1) begin
592 
            // Check to see if bank is open (ACT)
593 
            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
594 
                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
595 
                $display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
596 
            end
597 
 
598 
            // Activate to Read or Write
599 
            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
600 
                (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
601 
                (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
602 
                (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
603 
                $display("%m : at time %t ERROR: tRCD violation during Read", $time);
604 
            end
605 
 
606 
            // CAS Latency pipeline
607 
            if (Cas_latency_3 == 1'b1) begin
608 
                Command[2] = `READ;
609 
                Col_addr[2] = Addr;
610 
                Bank_addr[2] = Ba;
611 
            end else if (Cas_latency_2 == 1'b1) begin
612 
                Command[1] = `READ;
613 
                Col_addr[1] = Addr;
614 
                Bank_addr[1] = Ba;
615 
            end
616 
 
617 
            // Read interrupt Write (terminate Write immediately)
618 
            if (Data_in_enable == 1'b1) begin
619 
                Data_in_enable = 1'b0;
620 
 
621 
                // Interrupting a Write with Autoprecharge
622 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
623 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
624 
                    RW_interrupt_counter[RW_interrupt_bank] = 0;
625 
 
626 
                    // Display debug message
627 
                    if (Debug) begin
628 
                        $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
629 
                    end
630 
                end
631 
            end
632 
 
633 
            // Write with Auto Precharge
634 
            if (Addr[10] == 1'b1) begin
635 
                Auto_precharge[Ba] = 1'b1;
636 
                Count_precharge[Ba] = 0;
637 
                RW_interrupt_bank = Ba;
638 
                Read_precharge[Ba] = 1'b1;
639 
            end
640 
        end
641 
 
642 
        // Write Command
643 
        if (Write_enable == 1'b1) begin
644 
            // Activate to Write
645 
            if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
646 
                (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
647 
                $display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
648 
            end
649 
 
650 
            // Activate to Read or Write
651 
            if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
652 
                (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
653 
                (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
654 
                (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
655 
                $display("%m : at time %t ERROR: tRCD violation during Read", $time);
656 
            end
657 
 
658 
            // Latch Write command, Bank, and Column
659 
            Command[0] = `WRITE;
660 
            Col_addr[0] = Addr;
661 
            Bank_addr[0] = Ba;
662 
 
663 
            // Write interrupt Write (terminate Write immediately)
664 
            if (Data_in_enable == 1'b1) begin
665 
                Data_in_enable = 1'b0;
666 
 
667 
                // Interrupting a Write with Autoprecharge
668 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
669 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
670 
 
671 
                    // Display debug message
672 
                    if (Debug) begin
673 
                        $display ("%m : at time %t NOTE : Read Bank %h interrupt Write Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank);
674 
                    end
675 
                end
676 
            end
677 
 
678 
            // Write interrupt Read (terminate Read immediately)
679 
            if (Data_out_enable == 1'b1) begin
680 
                Data_out_enable = 1'b0;
681 
 
682 
                // Interrupting a Read with Autoprecharge
683 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
684 
                    RW_interrupt_read[RW_interrupt_bank] = 1'b1;
685 
 
686 
                    // Display debug message
687 
                    if (Debug) begin
688 
                        $display ("%m : at time %t NOTE : Write Bank %h interrupt Read Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank);
689 
                    end
690 
                end
691 
            end
692 
 
693 
            // Write with Auto Precharge
694 
            if (Addr[10] == 1'b1) begin
695 
                Auto_precharge[Ba] = 1'b1;
696 
                Count_precharge[Ba] = 0;
697 
                RW_interrupt_bank = Ba;
698 
                Write_precharge[Ba] = 1'b1;
699 
            end
700 
        end
701 
 
702 
        /*
703 
            Write with Auto Precharge Calculation
704 
                The device start internal precharge when:
705 
                    1.  Meet minimum tRAS requirement
706 
                and 2.  tWR cycle(s) after last valid data
707 
                 or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
708 
 
709 
            Note: Model is starting the internal precharge 1 cycle after they meet all the
710 
                  requirement but tRP will be compensate for the time after the 1 cycle.
711 
        */
712 
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
713 
            if ((($time - RAS_chk0 >= tRAS) &&                                                          // Case 1
714 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||   // Case 2
715 
                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
716 
                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
717 
                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
718 
                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin                 // Case 3
719 
                    Auto_precharge[0] = 1'b0;
720 
                    Write_precharge[0] = 1'b0;
721 
                    RW_interrupt_write[0] = 1'b0;
722 
                    Pc_b0 = 1'b1;
723 
                    Act_b0 = 1'b0;
724 
                    RP_chk0 = $time + tWRa;
725 
                    if (Debug) begin
726 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
727 
                    end
728 
            end
729 
        end
730 
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
731 
            if ((($time - RAS_chk1 >= tRAS) &&                                                          // Case 1
732 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||   // Case 2
733 
                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
734 
                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
735 
                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
736 
                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin                 // Case 3
737 
                    Auto_precharge[1] = 1'b0;
738 
                    Write_precharge[1] = 1'b0;
739 
                    RW_interrupt_write[1] = 1'b0;
740 
                    Pc_b1 = 1'b1;
741 
                    Act_b1 = 1'b0;
742 
                    RP_chk1 = $time + tWRa;
743 
                    if (Debug) begin
744 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
745 
                    end
746 
            end
747 
        end
748 
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
749 
            if ((($time - RAS_chk2 >= tRAS) &&                                                          // Case 1
750 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||   // Case 2
751 
                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
752 
                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
753 
                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
754 
                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin                 // Case 3
755 
                    Auto_precharge[2] = 1'b0;
756 
                    Write_precharge[2] = 1'b0;
757 
                    RW_interrupt_write[2] = 1'b0;
758 
                    Pc_b2 = 1'b1;
759 
                    Act_b2 = 1'b0;
760 
                    RP_chk2 = $time + tWRa;
761 
                    if (Debug) begin
762 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
763 
                    end
764 
            end
765 
        end
766 
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
767 
            if ((($time - RAS_chk3 >= tRAS) &&                                                          // Case 1
768 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||   // Case 2
769 
                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
770 
                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
771 
                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
772 
                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin                 // Case 3
773 
                    Auto_precharge[3] = 1'b0;
774 
                    Write_precharge[3] = 1'b0;
775 
                    RW_interrupt_write[3] = 1'b0;
776 
                    Pc_b3 = 1'b1;
777 
                    Act_b3 = 1'b0;
778 
                    RP_chk3 = $time + tWRa;
779 
                    if (Debug) begin
780 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
781 
                    end
782 
            end
783 
        end
784 
 
785 
        //  Read with Auto Precharge Calculation
786 
        //      The device start internal precharge:
787 
        //          1.  Meet minimum tRAS requirement
788 
        //      and 2.  CAS Latency - 1 cycles before last burst
789 
        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
790 
        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
791 
            if ((($time - RAS_chk0 >= tRAS) &&                                                      // Case 1
792 
                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 2
793 
                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
794 
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
795 
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
796 
                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
797 
                    Pc_b0 = 1'b1;
798 
                    Act_b0 = 1'b0;
799 
                    RP_chk0 = $time;
800 
                    Auto_precharge[0] = 1'b0;
801 
                    Read_precharge[0] = 1'b0;
802 
                    RW_interrupt_read[0] = 1'b0;
803 
                    if (Debug) begin
804 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
805 
                    end
806 
            end
807 
        end
808 
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
809 
            if ((($time - RAS_chk1 >= tRAS) &&
810 
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
811 
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
812 
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
813 
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
814 
                 (RW_interrupt_read[1] == 1'b1)) begin
815 
                    Pc_b1 = 1'b1;
816 
                    Act_b1 = 1'b0;
817 
                    RP_chk1 = $time;
818 
                    Auto_precharge[1] = 1'b0;
819 
                    Read_precharge[1] = 1'b0;
820 
                    RW_interrupt_read[1] = 1'b0;
821 
                    if (Debug) begin
822 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
823 
                    end
824 
            end
825 
        end
826 
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
827 
            if ((($time - RAS_chk2 >= tRAS) &&
828 
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
829 
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
830 
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
831 
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
832 
                 (RW_interrupt_read[2] == 1'b1)) begin
833 
                    Pc_b2 = 1'b1;
834 
                    Act_b2 = 1'b0;
835 
                    RP_chk2 = $time;
836 
                    Auto_precharge[2] = 1'b0;
837 
                    Read_precharge[2] = 1'b0;
838 
                    RW_interrupt_read[2] = 1'b0;
839 
                    if (Debug) begin
840 
                        $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
841 
                    end
842 
            end
843 
        end
844 
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
845 
            if ((($time - RAS_chk3 >= tRAS) &&
846 
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
847 
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
848 
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
849 
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
850 
                 (RW_interrupt_read[3] == 1'b1)) begin
851 
                    Pc_b3 = 1'b1;
852 
                    Act_b3 = 1'b0;
853 
                    RP_chk3 = $time;
854 
                    Auto_precharge[3] = 1'b0;
855 
                    Read_precharge[3] = 1'b0;
856 
                    RW_interrupt_read[3] = 1'b0;
857 
                    if (Debug) begin
858 
                        $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
859 
                    end
860 
            end
861 
        end
862 
 
863 
        // Internal Precharge or Bst
864 
        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
865 
            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
866 
                if (Data_out_enable == 1'b1) begin
867 
                    Data_out_enable = 1'b0;
868 
                end
869 
            end
870 
        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
871 
            if (Data_out_enable == 1'b1) begin
872 
                Data_out_enable = 1'b0;
873 
            end
874 
        end
875 
 
876 
        if (Data_out_enable == 1'b0) begin
877 
            Dq_reg <= #tOH {data_bits{1'bz}};
878 
        end
879 
 
880 
        // Detect Read or Write command
881 
        if (Command[0] == `READ) begin
882 
            Bank = Bank_addr[0];
883 
            Col = Col_addr[0];
884 
            Col_brst = Col_addr[0];
885 
            case (Bank_addr[0])
886 
                2'b00 : Row = B0_row_addr;
887 
                2'b01 : Row = B1_row_addr;
888 
                2'b10 : Row = B2_row_addr;
889 
                2'b11 : Row = B3_row_addr;
890 
            endcase
891 
            Burst_counter = 0;
892 
            Data_in_enable = 1'b0;
893 
            Data_out_enable = 1'b1;
894 
        end else if (Command[0] == `WRITE) begin
895 
            Bank = Bank_addr[0];
896 
            Col = Col_addr[0];
897 
            Col_brst = Col_addr[0];
898 
            case (Bank_addr[0])
899 
                2'b00 : Row = B0_row_addr;
900 
                2'b01 : Row = B1_row_addr;
901 
                2'b10 : Row = B2_row_addr;
902 
                2'b11 : Row = B3_row_addr;
903 
            endcase
904 
            Burst_counter = 0;
905 
            Data_in_enable = 1'b1;
906 
            Data_out_enable = 1'b0;
907 
        end
908 
 
909 
        // DQ buffer (Driver/Receiver)
910 
        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
911 
            // Array buffer
912 
            case (Bank)
913 
                2'b00 : Dq_dqm = Bank0 [{Row, Col}];
914 
                2'b01 : Dq_dqm = Bank1 [{Row, Col}];
915 
                2'b10 : Dq_dqm = Bank2 [{Row, Col}];
916 
                2'b11 : Dq_dqm = Bank3 [{Row, Col}];
917 
            endcase
918 
 
919 
            // Dqm operation
920 
            if (Dqm[0] == 1'b0) begin
921 
                Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
922 
            end
923 
            if (Dqm[1] == 1'b0) begin
924 
                Dq_dqm [15 : 8] = Dq [15 : 8];
925 
            end
926 
 
927 
            // Write to memory
928 
            case (Bank)
929 
                2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
930 
                2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
931 
                2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
932 
                2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
933 
            endcase
934 
 
935 
            // Display debug message
936 
            if (Dqm !== 2'b11) begin
937 
                // Record tWR for manual precharge
938 
                WR_chkm [Bank] = $time;
939 
 
940 
                if (Debug) begin
941 
                    $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_dqm);
942 
                end
943 
            end else begin
944 
                if (Debug) begin
945 
                    $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
946 
                end
947 
            end
948 
 
949 
            // Advance burst counter subroutine
950 
            #tHZ Burst_decode;
951 
 
952 
        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
953 
            // Array buffer
954 
            case (Bank)
955 
                2'b00 : Dq_dqm = Bank0[{Row, Col}];
956 
                2'b01 : Dq_dqm = Bank1[{Row, Col}];
957 
                2'b10 : Dq_dqm = Bank2[{Row, Col}];
958 
                2'b11 : Dq_dqm = Bank3[{Row, Col}];
959 
            endcase
960 
 
961 
            // Dqm operation
962 
            if (Dqm_reg0 [0] == 1'b1) begin
963 
                Dq_dqm [ 7 : 0] = 8'bz;
964 
            end
965 
            if (Dqm_reg0 [1] == 1'b1) begin
966 
                Dq_dqm [15 : 8] = 8'bz;
967 
            end
968 
 
969 
            // Display debug message
970 
            if (Dqm_reg0 !== 2'b11) begin
971 
                Dq_reg = #tAC Dq_dqm;
972 
                if (Debug) begin
973 
                    $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_reg);
974 
                end
975 
            end else begin
976 
                Dq_reg = #tHZ {data_bits{1'bz}};
977 
                if (Debug) begin
978 
                    $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
979 
                end
980 
            end
981 
 
982 
            // Advance burst counter subroutine
983 
            Burst_decode;
984 
        end
985 
    end
986 
 
987 
    // Burst counter decode
988 
    task Burst_decode;
989 
        begin
990 
            // Advance Burst Counter
991 
            Burst_counter = Burst_counter + 1;
992 
 
993 
            // Burst Type
994 
            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
995 
                Col_temp = Col + 1;
996 
            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
997 
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
998 
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
999 
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
1000 
            end
1001 
 
1002 
            // Burst Length
1003 
            if (Burst_length_2) begin                                       // Burst Length = 2
1004 
                Col [0] = Col_temp [0];
1005 
            end else if (Burst_length_4) begin                              // Burst Length = 4
1006 
                Col [1 : 0] = Col_temp [1 : 0];
1007 
            end else if (Burst_length_8) begin                              // Burst Length = 8
1008 
                Col [2 : 0] = Col_temp [2 : 0];
1009 
            end else begin                                                  // Burst Length = FULL
1010 
                Col = Col_temp;
1011 
            end
1012 
 
1013 
            // Burst Read Single Write
1014 
            if (Write_burst_mode == 1'b1) begin
1015 
                Data_in_enable = 1'b0;
1016 
            end
1017 
 
1018 
            // Data Counter
1019 
            if (Burst_length_1 == 1'b1) begin
1020 
                if (Burst_counter >= 1) begin
1021 
                    Data_in_enable = 1'b0;
1022 
                    Data_out_enable = 1'b0;
1023 
                end
1024 
            end else if (Burst_length_2 == 1'b1) begin
1025 
                if (Burst_counter >= 2) begin
1026 
                    Data_in_enable = 1'b0;
1027 
                    Data_out_enable = 1'b0;
1028 
                end
1029 
            end else if (Burst_length_4 == 1'b1) begin
1030 
                if (Burst_counter >= 4) begin
1031 
                    Data_in_enable = 1'b0;
1032 
                    Data_out_enable = 1'b0;
1033 
                end
1034 
            end else if (Burst_length_8 == 1'b1) begin
1035 
                if (Burst_counter >= 8) begin
1036 
                    Data_in_enable = 1'b0;
1037 
                    Data_out_enable = 1'b0;
1038 
                end
1039 
            end
1040 
        end
1041 
    endtask
1042 
 
1043 
    // Timing Parameters for -7E (133 MHz @ CL2)
1044 
    specify
1045 
        specparam
1046 
            tAH  =  0.8,                                        // Addr, Ba Hold Time
1047 
            tAS  =  1.5,                                        // Addr, Ba Setup Time
1048 
            tCH  =  2.5,                                        // Clock High-Level Width
1049 
            tCL  =  2.5,                                        // Clock Low-Level Width
1050 
            tCK  =  7.0,                                        // Clock Cycle Time
1051 
            tDH  =  0.8,                                        // Data-in Hold Time
1052 
            tDS  =  1.5,                                        // Data-in Setup Time
1053 
            tCKH =  0.8,                                        // CKE Hold  Time
1054 
            tCKS =  1.5,                                        // CKE Setup Time
1055 
            tCMH =  0.8,                                        // CS#, RAS#, CAS#, WE#, DQM# Hold  Time
1056 
            tCMS =  1.5;                                        // CS#, RAS#, CAS#, WE#, DQM# Setup Time
1057 
        $width    (posedge Clk,           tCH);
1058 
        $width    (negedge Clk,           tCL);
1059 
        $period   (negedge Clk,           tCK);
1060 
        $period   (posedge Clk,           tCK);
1061 
        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
1062 
        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
1063 
        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
1064 
        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
1065 
        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
1066 
        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
1067 
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
1068 
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
1069 
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
1070 
    endspecify
1071 
 
1072 
endmodule

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