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marcus.erl |
/*
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* ahci.c - AHCI SATA support
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004-2005 Red Hat, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* AHCI hardware documentation:
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* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/dmi.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>
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#define DRV_NAME "ahci"
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#define DRV_VERSION "3.0"
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static int ahci_enable_alpm(struct ata_port *ap,
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enum link_pm policy);
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static void ahci_disable_alpm(struct ata_port *ap);
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enum {
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AHCI_PCI_BAR = 5,
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AHCI_MAX_PORTS = 32,
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AHCI_MAX_SG = 168, /* hardware max is 64K */
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AHCI_DMA_BOUNDARY = 0xffffffff,
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AHCI_USE_CLUSTERING = 1,
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AHCI_MAX_CMDS = 32,
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AHCI_CMD_SZ = 32,
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AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
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AHCI_RX_FIS_SZ = 256,
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AHCI_CMD_TBL_CDB = 0x40,
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AHCI_CMD_TBL_HDR_SZ = 0x80,
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AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
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AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
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AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
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AHCI_RX_FIS_SZ,
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AHCI_IRQ_ON_SG = (1 << 31),
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AHCI_CMD_ATAPI = (1 << 5),
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AHCI_CMD_WRITE = (1 << 6),
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AHCI_CMD_PREFETCH = (1 << 7),
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AHCI_CMD_RESET = (1 << 8),
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AHCI_CMD_CLR_BUSY = (1 << 10),
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RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
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RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
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RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
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board_ahci = 0,
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board_ahci_vt8251 = 1,
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board_ahci_ign_iferr = 2,
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board_ahci_sb600 = 3,
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board_ahci_mv = 4,
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/* global controller registers */
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HOST_CAP = 0x00, /* host capabilities */
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HOST_CTL = 0x04, /* global host control */
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HOST_IRQ_STAT = 0x08, /* interrupt status */
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HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
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HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
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/* HOST_CTL bits */
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HOST_RESET = (1 << 0), /* reset controller; self-clear */
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HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
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HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
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/* HOST_CAP bits */
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HOST_CAP_SSC = (1 << 14), /* Slumber capable */
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HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
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HOST_CAP_CLO = (1 << 24), /* Command List Override support */
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HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
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HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
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HOST_CAP_SNTF = (1 << 29), /* SNotification register */
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HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
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HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
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/* registers for each SATA port */
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PORT_LST_ADDR = 0x00, /* command list DMA addr */
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PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
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PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
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PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
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PORT_IRQ_STAT = 0x10, /* interrupt status */
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PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
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PORT_CMD = 0x18, /* port command */
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PORT_TFDATA = 0x20, /* taskfile data */
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PORT_SIG = 0x24, /* device TF signature */
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PORT_CMD_ISSUE = 0x38, /* command issue */
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PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
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PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
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PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
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PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
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PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
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/* PORT_IRQ_{STAT,MASK} bits */
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PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
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PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
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PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
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PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
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PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
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PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
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PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
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PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
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PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
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PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
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PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
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PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
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PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
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PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
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PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
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PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
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PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
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PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
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PORT_IRQ_IF_ERR |
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PORT_IRQ_CONNECT |
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PORT_IRQ_PHYRDY |
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PORT_IRQ_UNK_FIS |
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PORT_IRQ_BAD_PMP,
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PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
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PORT_IRQ_TF_ERR |
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PORT_IRQ_HBUS_DATA_ERR,
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DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
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PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
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PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
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/* PORT_CMD bits */
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PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
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PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
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PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
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PORT_CMD_PMP = (1 << 17), /* PMP attached */
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PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
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PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
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PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
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PORT_CMD_CLO = (1 << 3), /* Command list override */
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PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
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PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
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PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
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PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
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PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
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PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
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PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
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/* hpriv->flags bits */
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AHCI_HFLAG_NO_NCQ = (1 << 0),
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AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
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AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
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AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
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AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
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AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
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AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
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AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
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/* ap->flags bits */
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AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
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ATA_FLAG_IPM,
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AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
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ICH_MAP = 0x90, /* ICH MAP register */
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};
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struct ahci_cmd_hdr {
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u32 opts;
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u32 status;
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u32 tbl_addr;
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u32 tbl_addr_hi;
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u32 reserved[4];
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};
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struct ahci_sg {
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u32 addr;
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u32 addr_hi;
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u32 reserved;
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u32 flags_size;
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};
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struct ahci_host_priv {
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unsigned int flags; /* AHCI_HFLAG_* */
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u32 cap; /* cap to use */
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u32 port_map; /* port map to use */
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u32 saved_cap; /* saved initial cap */
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u32 saved_port_map; /* saved initial port_map */
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};
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struct ahci_port_priv {
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struct ata_link *active_link;
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struct ahci_cmd_hdr *cmd_slot;
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dma_addr_t cmd_slot_dma;
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void *cmd_tbl;
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dma_addr_t cmd_tbl_dma;
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void *rx_fis;
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dma_addr_t rx_fis_dma;
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/* for NCQ spurious interrupt analysis */
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unsigned int ncq_saw_d2h:1;
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unsigned int ncq_saw_dmas:1;
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unsigned int ncq_saw_sdb:1;
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u32 intr_mask; /* interrupts to enable */
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};
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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
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static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static void ahci_irq_clear(struct ata_port *ap);
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static int ahci_port_start(struct ata_port *ap);
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static void ahci_port_stop(struct ata_port *ap);
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static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
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static void ahci_qc_prep(struct ata_queued_cmd *qc);
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static u8 ahci_check_status(struct ata_port *ap);
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static void ahci_freeze(struct ata_port *ap);
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static void ahci_thaw(struct ata_port *ap);
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static void ahci_pmp_attach(struct ata_port *ap);
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static void ahci_pmp_detach(struct ata_port *ap);
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static void ahci_error_handler(struct ata_port *ap);
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static void ahci_vt8251_error_handler(struct ata_port *ap);
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static void ahci_p5wdh_error_handler(struct ata_port *ap);
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static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
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static int ahci_port_resume(struct ata_port *ap);
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
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static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
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u32 opts);
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#ifdef CONFIG_PM
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static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
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static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int ahci_pci_device_resume(struct pci_dev *pdev);
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#endif
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static struct class_device_attribute *ahci_shost_attrs[] = {
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&class_device_attr_link_power_management_policy,
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NULL
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};
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static struct scsi_host_template ahci_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.change_queue_depth = ata_scsi_change_queue_depth,
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.can_queue = AHCI_MAX_CMDS - 1,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = AHCI_MAX_SG,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = AHCI_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = AHCI_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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.shost_attrs = ahci_shost_attrs,
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};
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static const struct ata_port_operations ahci_ops = {
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.check_status = ahci_check_status,
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.check_altstatus = ahci_check_status,
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.dev_select = ata_noop_dev_select,
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296 |
|
|
.tf_read = ahci_tf_read,
|
297 |
|
|
|
298 |
|
|
.qc_defer = sata_pmp_qc_defer_cmd_switch,
|
299 |
|
|
.qc_prep = ahci_qc_prep,
|
300 |
|
|
.qc_issue = ahci_qc_issue,
|
301 |
|
|
|
302 |
|
|
.irq_clear = ahci_irq_clear,
|
303 |
|
|
|
304 |
|
|
.scr_read = ahci_scr_read,
|
305 |
|
|
.scr_write = ahci_scr_write,
|
306 |
|
|
|
307 |
|
|
.freeze = ahci_freeze,
|
308 |
|
|
.thaw = ahci_thaw,
|
309 |
|
|
|
310 |
|
|
.error_handler = ahci_error_handler,
|
311 |
|
|
.post_internal_cmd = ahci_post_internal_cmd,
|
312 |
|
|
|
313 |
|
|
.pmp_attach = ahci_pmp_attach,
|
314 |
|
|
.pmp_detach = ahci_pmp_detach,
|
315 |
|
|
|
316 |
|
|
#ifdef CONFIG_PM
|
317 |
|
|
.port_suspend = ahci_port_suspend,
|
318 |
|
|
.port_resume = ahci_port_resume,
|
319 |
|
|
#endif
|
320 |
|
|
.enable_pm = ahci_enable_alpm,
|
321 |
|
|
.disable_pm = ahci_disable_alpm,
|
322 |
|
|
|
323 |
|
|
.port_start = ahci_port_start,
|
324 |
|
|
.port_stop = ahci_port_stop,
|
325 |
|
|
};
|
326 |
|
|
|
327 |
|
|
static const struct ata_port_operations ahci_vt8251_ops = {
|
328 |
|
|
.check_status = ahci_check_status,
|
329 |
|
|
.check_altstatus = ahci_check_status,
|
330 |
|
|
.dev_select = ata_noop_dev_select,
|
331 |
|
|
|
332 |
|
|
.tf_read = ahci_tf_read,
|
333 |
|
|
|
334 |
|
|
.qc_defer = sata_pmp_qc_defer_cmd_switch,
|
335 |
|
|
.qc_prep = ahci_qc_prep,
|
336 |
|
|
.qc_issue = ahci_qc_issue,
|
337 |
|
|
|
338 |
|
|
.irq_clear = ahci_irq_clear,
|
339 |
|
|
|
340 |
|
|
.scr_read = ahci_scr_read,
|
341 |
|
|
.scr_write = ahci_scr_write,
|
342 |
|
|
|
343 |
|
|
.freeze = ahci_freeze,
|
344 |
|
|
.thaw = ahci_thaw,
|
345 |
|
|
|
346 |
|
|
.error_handler = ahci_vt8251_error_handler,
|
347 |
|
|
.post_internal_cmd = ahci_post_internal_cmd,
|
348 |
|
|
|
349 |
|
|
.pmp_attach = ahci_pmp_attach,
|
350 |
|
|
.pmp_detach = ahci_pmp_detach,
|
351 |
|
|
|
352 |
|
|
#ifdef CONFIG_PM
|
353 |
|
|
.port_suspend = ahci_port_suspend,
|
354 |
|
|
.port_resume = ahci_port_resume,
|
355 |
|
|
#endif
|
356 |
|
|
|
357 |
|
|
.port_start = ahci_port_start,
|
358 |
|
|
.port_stop = ahci_port_stop,
|
359 |
|
|
};
|
360 |
|
|
|
361 |
|
|
static const struct ata_port_operations ahci_p5wdh_ops = {
|
362 |
|
|
.check_status = ahci_check_status,
|
363 |
|
|
.check_altstatus = ahci_check_status,
|
364 |
|
|
.dev_select = ata_noop_dev_select,
|
365 |
|
|
|
366 |
|
|
.tf_read = ahci_tf_read,
|
367 |
|
|
|
368 |
|
|
.qc_defer = sata_pmp_qc_defer_cmd_switch,
|
369 |
|
|
.qc_prep = ahci_qc_prep,
|
370 |
|
|
.qc_issue = ahci_qc_issue,
|
371 |
|
|
|
372 |
|
|
.irq_clear = ahci_irq_clear,
|
373 |
|
|
|
374 |
|
|
.scr_read = ahci_scr_read,
|
375 |
|
|
.scr_write = ahci_scr_write,
|
376 |
|
|
|
377 |
|
|
.freeze = ahci_freeze,
|
378 |
|
|
.thaw = ahci_thaw,
|
379 |
|
|
|
380 |
|
|
.error_handler = ahci_p5wdh_error_handler,
|
381 |
|
|
.post_internal_cmd = ahci_post_internal_cmd,
|
382 |
|
|
|
383 |
|
|
.pmp_attach = ahci_pmp_attach,
|
384 |
|
|
.pmp_detach = ahci_pmp_detach,
|
385 |
|
|
|
386 |
|
|
#ifdef CONFIG_PM
|
387 |
|
|
.port_suspend = ahci_port_suspend,
|
388 |
|
|
.port_resume = ahci_port_resume,
|
389 |
|
|
#endif
|
390 |
|
|
|
391 |
|
|
.port_start = ahci_port_start,
|
392 |
|
|
.port_stop = ahci_port_stop,
|
393 |
|
|
};
|
394 |
|
|
|
395 |
|
|
#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
|
396 |
|
|
|
397 |
|
|
static const struct ata_port_info ahci_port_info[] = {
|
398 |
|
|
/* board_ahci */
|
399 |
|
|
{
|
400 |
|
|
.flags = AHCI_FLAG_COMMON,
|
401 |
|
|
.link_flags = AHCI_LFLAG_COMMON,
|
402 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
403 |
|
|
.udma_mask = ATA_UDMA6,
|
404 |
|
|
.port_ops = &ahci_ops,
|
405 |
|
|
},
|
406 |
|
|
/* board_ahci_vt8251 */
|
407 |
|
|
{
|
408 |
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
|
409 |
|
|
.flags = AHCI_FLAG_COMMON,
|
410 |
|
|
.link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
|
411 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
412 |
|
|
.udma_mask = ATA_UDMA6,
|
413 |
|
|
.port_ops = &ahci_vt8251_ops,
|
414 |
|
|
},
|
415 |
|
|
/* board_ahci_ign_iferr */
|
416 |
|
|
{
|
417 |
|
|
AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
|
418 |
|
|
.flags = AHCI_FLAG_COMMON,
|
419 |
|
|
.link_flags = AHCI_LFLAG_COMMON,
|
420 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
421 |
|
|
.udma_mask = ATA_UDMA6,
|
422 |
|
|
.port_ops = &ahci_ops,
|
423 |
|
|
},
|
424 |
|
|
/* board_ahci_sb600 */
|
425 |
|
|
{
|
426 |
|
|
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
|
427 |
|
|
AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
|
428 |
|
|
.flags = AHCI_FLAG_COMMON,
|
429 |
|
|
.link_flags = AHCI_LFLAG_COMMON,
|
430 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
431 |
|
|
.udma_mask = ATA_UDMA6,
|
432 |
|
|
.port_ops = &ahci_ops,
|
433 |
|
|
},
|
434 |
|
|
/* board_ahci_mv */
|
435 |
|
|
{
|
436 |
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
|
437 |
|
|
AHCI_HFLAG_MV_PATA),
|
438 |
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
|
439 |
|
|
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
|
440 |
|
|
.link_flags = AHCI_LFLAG_COMMON,
|
441 |
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
442 |
|
|
.udma_mask = ATA_UDMA6,
|
443 |
|
|
.port_ops = &ahci_ops,
|
444 |
|
|
},
|
445 |
|
|
};
|
446 |
|
|
|
447 |
|
|
static const struct pci_device_id ahci_pci_tbl[] = {
|
448 |
|
|
/* Intel */
|
449 |
|
|
{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
|
450 |
|
|
{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
|
451 |
|
|
{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
|
452 |
|
|
{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
|
453 |
|
|
{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
|
454 |
|
|
{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
|
455 |
|
|
{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
|
456 |
|
|
{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
|
457 |
|
|
{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
|
458 |
|
|
{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
|
459 |
|
|
{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
|
460 |
|
|
{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
|
461 |
|
|
{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
|
462 |
|
|
{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
|
463 |
|
|
{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
|
464 |
|
|
{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
|
465 |
|
|
{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
|
466 |
|
|
{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
|
467 |
|
|
{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
|
468 |
|
|
{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
|
469 |
|
|
{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
|
470 |
|
|
{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
|
471 |
|
|
{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
|
472 |
|
|
{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
|
473 |
|
|
{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
|
474 |
|
|
{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
|
475 |
|
|
{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
|
476 |
|
|
{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
|
477 |
|
|
{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
|
478 |
|
|
|
479 |
|
|
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
|
480 |
|
|
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
481 |
|
|
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
|
482 |
|
|
|
483 |
|
|
/* ATI */
|
484 |
|
|
{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
|
485 |
|
|
{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
|
486 |
|
|
{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
|
487 |
|
|
{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
|
488 |
|
|
{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
|
489 |
|
|
{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
|
490 |
|
|
{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
|
491 |
|
|
|
492 |
|
|
/* VIA */
|
493 |
|
|
{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
|
494 |
|
|
{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
|
495 |
|
|
|
496 |
|
|
/* NVIDIA */
|
497 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
|
498 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
|
499 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
|
500 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
|
501 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
|
502 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
|
503 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
|
504 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
|
505 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
|
506 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
|
507 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
|
508 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
|
509 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
|
510 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
|
511 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
|
512 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
|
513 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
|
514 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
|
515 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
|
516 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
|
517 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
|
518 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
|
519 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
|
520 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
|
521 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
|
522 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
|
523 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
|
524 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
|
525 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
|
526 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
|
527 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
|
528 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
|
529 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
|
530 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
|
531 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
|
532 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
|
533 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
|
534 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
|
535 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
|
536 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
|
537 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
|
538 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
|
539 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
|
540 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
|
541 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
|
542 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
|
543 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
|
544 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
|
545 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
|
546 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
|
547 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
|
548 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
|
549 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
|
550 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
|
551 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
|
552 |
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
|
553 |
|
|
|
554 |
|
|
/* SiS */
|
555 |
|
|
{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
|
556 |
|
|
{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
|
557 |
|
|
{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
|
558 |
|
|
|
559 |
|
|
/* Marvell */
|
560 |
|
|
{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
|
561 |
|
|
|
562 |
|
|
/* Generic, PCI class code for AHCI */
|
563 |
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
564 |
|
|
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
|
565 |
|
|
|
566 |
|
|
{ } /* terminate list */
|
567 |
|
|
};
|
568 |
|
|
|
569 |
|
|
|
570 |
|
|
static struct pci_driver ahci_pci_driver = {
|
571 |
|
|
.name = DRV_NAME,
|
572 |
|
|
.id_table = ahci_pci_tbl,
|
573 |
|
|
.probe = ahci_init_one,
|
574 |
|
|
.remove = ata_pci_remove_one,
|
575 |
|
|
#ifdef CONFIG_PM
|
576 |
|
|
.suspend = ahci_pci_device_suspend,
|
577 |
|
|
.resume = ahci_pci_device_resume,
|
578 |
|
|
#endif
|
579 |
|
|
};
|
580 |
|
|
|
581 |
|
|
|
582 |
|
|
static inline int ahci_nr_ports(u32 cap)
|
583 |
|
|
{
|
584 |
|
|
return (cap & 0x1f) + 1;
|
585 |
|
|
}
|
586 |
|
|
|
587 |
|
|
static inline void __iomem *__ahci_port_base(struct ata_host *host,
|
588 |
|
|
unsigned int port_no)
|
589 |
|
|
{
|
590 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
591 |
|
|
|
592 |
|
|
return mmio + 0x100 + (port_no * 0x80);
|
593 |
|
|
}
|
594 |
|
|
|
595 |
|
|
static inline void __iomem *ahci_port_base(struct ata_port *ap)
|
596 |
|
|
{
|
597 |
|
|
return __ahci_port_base(ap->host, ap->port_no);
|
598 |
|
|
}
|
599 |
|
|
|
600 |
|
|
/**
|
601 |
|
|
* ahci_save_initial_config - Save and fixup initial config values
|
602 |
|
|
* @pdev: target PCI device
|
603 |
|
|
* @hpriv: host private area to store config values
|
604 |
|
|
*
|
605 |
|
|
* Some registers containing configuration info might be setup by
|
606 |
|
|
* BIOS and might be cleared on reset. This function saves the
|
607 |
|
|
* initial values of those registers into @hpriv such that they
|
608 |
|
|
* can be restored after controller reset.
|
609 |
|
|
*
|
610 |
|
|
* If inconsistent, config values are fixed up by this function.
|
611 |
|
|
*
|
612 |
|
|
* LOCKING:
|
613 |
|
|
* None.
|
614 |
|
|
*/
|
615 |
|
|
static void ahci_save_initial_config(struct pci_dev *pdev,
|
616 |
|
|
struct ahci_host_priv *hpriv)
|
617 |
|
|
{
|
618 |
|
|
void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
|
619 |
|
|
u32 cap, port_map;
|
620 |
|
|
int i;
|
621 |
|
|
|
622 |
|
|
/* Values prefixed with saved_ are written back to host after
|
623 |
|
|
* reset. Values without are used for driver operation.
|
624 |
|
|
*/
|
625 |
|
|
hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
|
626 |
|
|
hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
|
627 |
|
|
|
628 |
|
|
/* some chips have errata preventing 64bit use */
|
629 |
|
|
if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
|
630 |
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
631 |
|
|
"controller can't do 64bit DMA, forcing 32bit\n");
|
632 |
|
|
cap &= ~HOST_CAP_64;
|
633 |
|
|
}
|
634 |
|
|
|
635 |
|
|
if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
|
636 |
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
637 |
|
|
"controller can't do NCQ, turning off CAP_NCQ\n");
|
638 |
|
|
cap &= ~HOST_CAP_NCQ;
|
639 |
|
|
}
|
640 |
|
|
|
641 |
|
|
if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
|
642 |
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
643 |
|
|
"controller can't do PMP, turning off CAP_PMP\n");
|
644 |
|
|
cap &= ~HOST_CAP_PMP;
|
645 |
|
|
}
|
646 |
|
|
|
647 |
|
|
/*
|
648 |
|
|
* Temporary Marvell 6145 hack: PATA port presence
|
649 |
|
|
* is asserted through the standard AHCI port
|
650 |
|
|
* presence register, as bit 4 (counting from 0)
|
651 |
|
|
*/
|
652 |
|
|
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
|
653 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
654 |
|
|
"MV_AHCI HACK: port_map %x -> %x\n",
|
655 |
|
|
hpriv->port_map,
|
656 |
|
|
hpriv->port_map & 0xf);
|
657 |
|
|
|
658 |
|
|
port_map &= 0xf;
|
659 |
|
|
}
|
660 |
|
|
|
661 |
|
|
/* cross check port_map and cap.n_ports */
|
662 |
|
|
if (port_map) {
|
663 |
|
|
u32 tmp_port_map = port_map;
|
664 |
|
|
int n_ports = ahci_nr_ports(cap);
|
665 |
|
|
|
666 |
|
|
for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
|
667 |
|
|
if (tmp_port_map & (1 << i)) {
|
668 |
|
|
n_ports--;
|
669 |
|
|
tmp_port_map &= ~(1 << i);
|
670 |
|
|
}
|
671 |
|
|
}
|
672 |
|
|
|
673 |
|
|
/* If n_ports and port_map are inconsistent, whine and
|
674 |
|
|
* clear port_map and let it be generated from n_ports.
|
675 |
|
|
*/
|
676 |
|
|
if (n_ports || tmp_port_map) {
|
677 |
|
|
dev_printk(KERN_WARNING, &pdev->dev,
|
678 |
|
|
"nr_ports (%u) and implemented port map "
|
679 |
|
|
"(0x%x) don't match, using nr_ports\n",
|
680 |
|
|
ahci_nr_ports(cap), port_map);
|
681 |
|
|
port_map = 0;
|
682 |
|
|
}
|
683 |
|
|
}
|
684 |
|
|
|
685 |
|
|
/* fabricate port_map from cap.nr_ports */
|
686 |
|
|
if (!port_map) {
|
687 |
|
|
port_map = (1 << ahci_nr_ports(cap)) - 1;
|
688 |
|
|
dev_printk(KERN_WARNING, &pdev->dev,
|
689 |
|
|
"forcing PORTS_IMPL to 0x%x\n", port_map);
|
690 |
|
|
|
691 |
|
|
/* write the fixed up value to the PI register */
|
692 |
|
|
hpriv->saved_port_map = port_map;
|
693 |
|
|
}
|
694 |
|
|
|
695 |
|
|
/* record values to use during operation */
|
696 |
|
|
hpriv->cap = cap;
|
697 |
|
|
hpriv->port_map = port_map;
|
698 |
|
|
}
|
699 |
|
|
|
700 |
|
|
/**
|
701 |
|
|
* ahci_restore_initial_config - Restore initial config
|
702 |
|
|
* @host: target ATA host
|
703 |
|
|
*
|
704 |
|
|
* Restore initial config stored by ahci_save_initial_config().
|
705 |
|
|
*
|
706 |
|
|
* LOCKING:
|
707 |
|
|
* None.
|
708 |
|
|
*/
|
709 |
|
|
static void ahci_restore_initial_config(struct ata_host *host)
|
710 |
|
|
{
|
711 |
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
712 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
713 |
|
|
|
714 |
|
|
writel(hpriv->saved_cap, mmio + HOST_CAP);
|
715 |
|
|
writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
|
716 |
|
|
(void) readl(mmio + HOST_PORTS_IMPL); /* flush */
|
717 |
|
|
}
|
718 |
|
|
|
719 |
|
|
static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
|
720 |
|
|
{
|
721 |
|
|
static const int offset[] = {
|
722 |
|
|
[SCR_STATUS] = PORT_SCR_STAT,
|
723 |
|
|
[SCR_CONTROL] = PORT_SCR_CTL,
|
724 |
|
|
[SCR_ERROR] = PORT_SCR_ERR,
|
725 |
|
|
[SCR_ACTIVE] = PORT_SCR_ACT,
|
726 |
|
|
[SCR_NOTIFICATION] = PORT_SCR_NTF,
|
727 |
|
|
};
|
728 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
729 |
|
|
|
730 |
|
|
if (sc_reg < ARRAY_SIZE(offset) &&
|
731 |
|
|
(sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
|
732 |
|
|
return offset[sc_reg];
|
733 |
|
|
return 0;
|
734 |
|
|
}
|
735 |
|
|
|
736 |
|
|
static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
|
737 |
|
|
{
|
738 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
739 |
|
|
int offset = ahci_scr_offset(ap, sc_reg);
|
740 |
|
|
|
741 |
|
|
if (offset) {
|
742 |
|
|
*val = readl(port_mmio + offset);
|
743 |
|
|
return 0;
|
744 |
|
|
}
|
745 |
|
|
return -EINVAL;
|
746 |
|
|
}
|
747 |
|
|
|
748 |
|
|
static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
|
749 |
|
|
{
|
750 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
751 |
|
|
int offset = ahci_scr_offset(ap, sc_reg);
|
752 |
|
|
|
753 |
|
|
if (offset) {
|
754 |
|
|
writel(val, port_mmio + offset);
|
755 |
|
|
return 0;
|
756 |
|
|
}
|
757 |
|
|
return -EINVAL;
|
758 |
|
|
}
|
759 |
|
|
|
760 |
|
|
static void ahci_start_engine(struct ata_port *ap)
|
761 |
|
|
{
|
762 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
763 |
|
|
u32 tmp;
|
764 |
|
|
|
765 |
|
|
/* start DMA */
|
766 |
|
|
tmp = readl(port_mmio + PORT_CMD);
|
767 |
|
|
tmp |= PORT_CMD_START;
|
768 |
|
|
writel(tmp, port_mmio + PORT_CMD);
|
769 |
|
|
readl(port_mmio + PORT_CMD); /* flush */
|
770 |
|
|
}
|
771 |
|
|
|
772 |
|
|
static int ahci_stop_engine(struct ata_port *ap)
|
773 |
|
|
{
|
774 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
775 |
|
|
u32 tmp;
|
776 |
|
|
|
777 |
|
|
tmp = readl(port_mmio + PORT_CMD);
|
778 |
|
|
|
779 |
|
|
/* check if the HBA is idle */
|
780 |
|
|
if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
|
781 |
|
|
return 0;
|
782 |
|
|
|
783 |
|
|
/* setting HBA to idle */
|
784 |
|
|
tmp &= ~PORT_CMD_START;
|
785 |
|
|
writel(tmp, port_mmio + PORT_CMD);
|
786 |
|
|
|
787 |
|
|
/* wait for engine to stop. This could be as long as 500 msec */
|
788 |
|
|
tmp = ata_wait_register(port_mmio + PORT_CMD,
|
789 |
|
|
PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
|
790 |
|
|
if (tmp & PORT_CMD_LIST_ON)
|
791 |
|
|
return -EIO;
|
792 |
|
|
|
793 |
|
|
return 0;
|
794 |
|
|
}
|
795 |
|
|
|
796 |
|
|
static void ahci_start_fis_rx(struct ata_port *ap)
|
797 |
|
|
{
|
798 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
799 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
800 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
801 |
|
|
u32 tmp;
|
802 |
|
|
|
803 |
|
|
/* set FIS registers */
|
804 |
|
|
if (hpriv->cap & HOST_CAP_64)
|
805 |
|
|
writel((pp->cmd_slot_dma >> 16) >> 16,
|
806 |
|
|
port_mmio + PORT_LST_ADDR_HI);
|
807 |
|
|
writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
|
808 |
|
|
|
809 |
|
|
if (hpriv->cap & HOST_CAP_64)
|
810 |
|
|
writel((pp->rx_fis_dma >> 16) >> 16,
|
811 |
|
|
port_mmio + PORT_FIS_ADDR_HI);
|
812 |
|
|
writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
|
813 |
|
|
|
814 |
|
|
/* enable FIS reception */
|
815 |
|
|
tmp = readl(port_mmio + PORT_CMD);
|
816 |
|
|
tmp |= PORT_CMD_FIS_RX;
|
817 |
|
|
writel(tmp, port_mmio + PORT_CMD);
|
818 |
|
|
|
819 |
|
|
/* flush */
|
820 |
|
|
readl(port_mmio + PORT_CMD);
|
821 |
|
|
}
|
822 |
|
|
|
823 |
|
|
static int ahci_stop_fis_rx(struct ata_port *ap)
|
824 |
|
|
{
|
825 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
826 |
|
|
u32 tmp;
|
827 |
|
|
|
828 |
|
|
/* disable FIS reception */
|
829 |
|
|
tmp = readl(port_mmio + PORT_CMD);
|
830 |
|
|
tmp &= ~PORT_CMD_FIS_RX;
|
831 |
|
|
writel(tmp, port_mmio + PORT_CMD);
|
832 |
|
|
|
833 |
|
|
/* wait for completion, spec says 500ms, give it 1000 */
|
834 |
|
|
tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
|
835 |
|
|
PORT_CMD_FIS_ON, 10, 1000);
|
836 |
|
|
if (tmp & PORT_CMD_FIS_ON)
|
837 |
|
|
return -EBUSY;
|
838 |
|
|
|
839 |
|
|
return 0;
|
840 |
|
|
}
|
841 |
|
|
|
842 |
|
|
static void ahci_power_up(struct ata_port *ap)
|
843 |
|
|
{
|
844 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
845 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
846 |
|
|
u32 cmd;
|
847 |
|
|
|
848 |
|
|
cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
|
849 |
|
|
|
850 |
|
|
/* spin up device */
|
851 |
|
|
if (hpriv->cap & HOST_CAP_SSS) {
|
852 |
|
|
cmd |= PORT_CMD_SPIN_UP;
|
853 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
854 |
|
|
}
|
855 |
|
|
|
856 |
|
|
/* wake up link */
|
857 |
|
|
writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
|
858 |
|
|
}
|
859 |
|
|
|
860 |
|
|
static void ahci_disable_alpm(struct ata_port *ap)
|
861 |
|
|
{
|
862 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
863 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
864 |
|
|
u32 cmd;
|
865 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
866 |
|
|
|
867 |
|
|
/* IPM bits should be disabled by libata-core */
|
868 |
|
|
/* get the existing command bits */
|
869 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
870 |
|
|
|
871 |
|
|
/* disable ALPM and ASP */
|
872 |
|
|
cmd &= ~PORT_CMD_ASP;
|
873 |
|
|
cmd &= ~PORT_CMD_ALPE;
|
874 |
|
|
|
875 |
|
|
/* force the interface back to active */
|
876 |
|
|
cmd |= PORT_CMD_ICC_ACTIVE;
|
877 |
|
|
|
878 |
|
|
/* write out new cmd value */
|
879 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
880 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
881 |
|
|
|
882 |
|
|
/* wait 10ms to be sure we've come out of any low power state */
|
883 |
|
|
msleep(10);
|
884 |
|
|
|
885 |
|
|
/* clear out any PhyRdy stuff from interrupt status */
|
886 |
|
|
writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
|
887 |
|
|
|
888 |
|
|
/* go ahead and clean out PhyRdy Change from Serror too */
|
889 |
|
|
ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
|
890 |
|
|
|
891 |
|
|
/*
|
892 |
|
|
* Clear flag to indicate that we should ignore all PhyRdy
|
893 |
|
|
* state changes
|
894 |
|
|
*/
|
895 |
|
|
hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
|
896 |
|
|
|
897 |
|
|
/*
|
898 |
|
|
* Enable interrupts on Phy Ready.
|
899 |
|
|
*/
|
900 |
|
|
pp->intr_mask |= PORT_IRQ_PHYRDY;
|
901 |
|
|
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
|
902 |
|
|
|
903 |
|
|
/*
|
904 |
|
|
* don't change the link pm policy - we can be called
|
905 |
|
|
* just to turn of link pm temporarily
|
906 |
|
|
*/
|
907 |
|
|
}
|
908 |
|
|
|
909 |
|
|
static int ahci_enable_alpm(struct ata_port *ap,
|
910 |
|
|
enum link_pm policy)
|
911 |
|
|
{
|
912 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
913 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
914 |
|
|
u32 cmd;
|
915 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
916 |
|
|
u32 asp;
|
917 |
|
|
|
918 |
|
|
/* Make sure the host is capable of link power management */
|
919 |
|
|
if (!(hpriv->cap & HOST_CAP_ALPM))
|
920 |
|
|
return -EINVAL;
|
921 |
|
|
|
922 |
|
|
switch (policy) {
|
923 |
|
|
case MAX_PERFORMANCE:
|
924 |
|
|
case NOT_AVAILABLE:
|
925 |
|
|
/*
|
926 |
|
|
* if we came here with NOT_AVAILABLE,
|
927 |
|
|
* it just means this is the first time we
|
928 |
|
|
* have tried to enable - default to max performance,
|
929 |
|
|
* and let the user go to lower power modes on request.
|
930 |
|
|
*/
|
931 |
|
|
ahci_disable_alpm(ap);
|
932 |
|
|
return 0;
|
933 |
|
|
case MIN_POWER:
|
934 |
|
|
/* configure HBA to enter SLUMBER */
|
935 |
|
|
asp = PORT_CMD_ASP;
|
936 |
|
|
break;
|
937 |
|
|
case MEDIUM_POWER:
|
938 |
|
|
/* configure HBA to enter PARTIAL */
|
939 |
|
|
asp = 0;
|
940 |
|
|
break;
|
941 |
|
|
default:
|
942 |
|
|
return -EINVAL;
|
943 |
|
|
}
|
944 |
|
|
|
945 |
|
|
/*
|
946 |
|
|
* Disable interrupts on Phy Ready. This keeps us from
|
947 |
|
|
* getting woken up due to spurious phy ready interrupts
|
948 |
|
|
* TBD - Hot plug should be done via polling now, is
|
949 |
|
|
* that even supported?
|
950 |
|
|
*/
|
951 |
|
|
pp->intr_mask &= ~PORT_IRQ_PHYRDY;
|
952 |
|
|
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
|
953 |
|
|
|
954 |
|
|
/*
|
955 |
|
|
* Set a flag to indicate that we should ignore all PhyRdy
|
956 |
|
|
* state changes since these can happen now whenever we
|
957 |
|
|
* change link state
|
958 |
|
|
*/
|
959 |
|
|
hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
|
960 |
|
|
|
961 |
|
|
/* get the existing command bits */
|
962 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
963 |
|
|
|
964 |
|
|
/*
|
965 |
|
|
* Set ASP based on Policy
|
966 |
|
|
*/
|
967 |
|
|
cmd |= asp;
|
968 |
|
|
|
969 |
|
|
/*
|
970 |
|
|
* Setting this bit will instruct the HBA to aggressively
|
971 |
|
|
* enter a lower power link state when it's appropriate and
|
972 |
|
|
* based on the value set above for ASP
|
973 |
|
|
*/
|
974 |
|
|
cmd |= PORT_CMD_ALPE;
|
975 |
|
|
|
976 |
|
|
/* write out new cmd value */
|
977 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
978 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
979 |
|
|
|
980 |
|
|
/* IPM bits should be set by libata-core */
|
981 |
|
|
return 0;
|
982 |
|
|
}
|
983 |
|
|
|
984 |
|
|
#ifdef CONFIG_PM
|
985 |
|
|
static void ahci_power_down(struct ata_port *ap)
|
986 |
|
|
{
|
987 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
988 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
989 |
|
|
u32 cmd, scontrol;
|
990 |
|
|
|
991 |
|
|
if (!(hpriv->cap & HOST_CAP_SSS))
|
992 |
|
|
return;
|
993 |
|
|
|
994 |
|
|
/* put device into listen mode, first set PxSCTL.DET to 0 */
|
995 |
|
|
scontrol = readl(port_mmio + PORT_SCR_CTL);
|
996 |
|
|
scontrol &= ~0xf;
|
997 |
|
|
writel(scontrol, port_mmio + PORT_SCR_CTL);
|
998 |
|
|
|
999 |
|
|
/* then set PxCMD.SUD to 0 */
|
1000 |
|
|
cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
|
1001 |
|
|
cmd &= ~PORT_CMD_SPIN_UP;
|
1002 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
1003 |
|
|
}
|
1004 |
|
|
#endif
|
1005 |
|
|
|
1006 |
|
|
static void ahci_start_port(struct ata_port *ap)
|
1007 |
|
|
{
|
1008 |
|
|
/* enable FIS reception */
|
1009 |
|
|
ahci_start_fis_rx(ap);
|
1010 |
|
|
|
1011 |
|
|
/* enable DMA */
|
1012 |
|
|
ahci_start_engine(ap);
|
1013 |
|
|
}
|
1014 |
|
|
|
1015 |
|
|
static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
|
1016 |
|
|
{
|
1017 |
|
|
int rc;
|
1018 |
|
|
|
1019 |
|
|
/* disable DMA */
|
1020 |
|
|
rc = ahci_stop_engine(ap);
|
1021 |
|
|
if (rc) {
|
1022 |
|
|
*emsg = "failed to stop engine";
|
1023 |
|
|
return rc;
|
1024 |
|
|
}
|
1025 |
|
|
|
1026 |
|
|
/* disable FIS reception */
|
1027 |
|
|
rc = ahci_stop_fis_rx(ap);
|
1028 |
|
|
if (rc) {
|
1029 |
|
|
*emsg = "failed stop FIS RX";
|
1030 |
|
|
return rc;
|
1031 |
|
|
}
|
1032 |
|
|
|
1033 |
|
|
return 0;
|
1034 |
|
|
}
|
1035 |
|
|
|
1036 |
|
|
static int ahci_reset_controller(struct ata_host *host)
|
1037 |
|
|
{
|
1038 |
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
1039 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
1040 |
|
|
u32 tmp;
|
1041 |
|
|
|
1042 |
|
|
/* we must be in AHCI mode, before using anything
|
1043 |
|
|
* AHCI-specific, such as HOST_RESET.
|
1044 |
|
|
*/
|
1045 |
|
|
tmp = readl(mmio + HOST_CTL);
|
1046 |
|
|
if (!(tmp & HOST_AHCI_EN)) {
|
1047 |
|
|
tmp |= HOST_AHCI_EN;
|
1048 |
|
|
writel(tmp, mmio + HOST_CTL);
|
1049 |
|
|
}
|
1050 |
|
|
|
1051 |
|
|
/* global controller reset */
|
1052 |
|
|
if ((tmp & HOST_RESET) == 0) {
|
1053 |
|
|
writel(tmp | HOST_RESET, mmio + HOST_CTL);
|
1054 |
|
|
readl(mmio + HOST_CTL); /* flush */
|
1055 |
|
|
}
|
1056 |
|
|
|
1057 |
|
|
/* reset must complete within 1 second, or
|
1058 |
|
|
* the hardware should be considered fried.
|
1059 |
|
|
*/
|
1060 |
|
|
ssleep(1);
|
1061 |
|
|
|
1062 |
|
|
tmp = readl(mmio + HOST_CTL);
|
1063 |
|
|
if (tmp & HOST_RESET) {
|
1064 |
|
|
dev_printk(KERN_ERR, host->dev,
|
1065 |
|
|
"controller reset failed (0x%x)\n", tmp);
|
1066 |
|
|
return -EIO;
|
1067 |
|
|
}
|
1068 |
|
|
|
1069 |
|
|
/* turn on AHCI mode */
|
1070 |
|
|
writel(HOST_AHCI_EN, mmio + HOST_CTL);
|
1071 |
|
|
(void) readl(mmio + HOST_CTL); /* flush */
|
1072 |
|
|
|
1073 |
|
|
/* some registers might be cleared on reset. restore initial values */
|
1074 |
|
|
ahci_restore_initial_config(host);
|
1075 |
|
|
|
1076 |
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
|
1077 |
|
|
u16 tmp16;
|
1078 |
|
|
|
1079 |
|
|
/* configure PCS */
|
1080 |
|
|
pci_read_config_word(pdev, 0x92, &tmp16);
|
1081 |
|
|
tmp16 |= 0xf;
|
1082 |
|
|
pci_write_config_word(pdev, 0x92, tmp16);
|
1083 |
|
|
}
|
1084 |
|
|
|
1085 |
|
|
return 0;
|
1086 |
|
|
}
|
1087 |
|
|
|
1088 |
|
|
static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
|
1089 |
|
|
int port_no, void __iomem *mmio,
|
1090 |
|
|
void __iomem *port_mmio)
|
1091 |
|
|
{
|
1092 |
|
|
const char *emsg = NULL;
|
1093 |
|
|
int rc;
|
1094 |
|
|
u32 tmp;
|
1095 |
|
|
|
1096 |
|
|
/* make sure port is not active */
|
1097 |
|
|
rc = ahci_deinit_port(ap, &emsg);
|
1098 |
|
|
if (rc)
|
1099 |
|
|
dev_printk(KERN_WARNING, &pdev->dev,
|
1100 |
|
|
"%s (%d)\n", emsg, rc);
|
1101 |
|
|
|
1102 |
|
|
/* clear SError */
|
1103 |
|
|
tmp = readl(port_mmio + PORT_SCR_ERR);
|
1104 |
|
|
VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
|
1105 |
|
|
writel(tmp, port_mmio + PORT_SCR_ERR);
|
1106 |
|
|
|
1107 |
|
|
/* clear port IRQ */
|
1108 |
|
|
tmp = readl(port_mmio + PORT_IRQ_STAT);
|
1109 |
|
|
VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
|
1110 |
|
|
if (tmp)
|
1111 |
|
|
writel(tmp, port_mmio + PORT_IRQ_STAT);
|
1112 |
|
|
|
1113 |
|
|
writel(1 << port_no, mmio + HOST_IRQ_STAT);
|
1114 |
|
|
}
|
1115 |
|
|
|
1116 |
|
|
static void ahci_init_controller(struct ata_host *host)
|
1117 |
|
|
{
|
1118 |
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
1119 |
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
1120 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
1121 |
|
|
int i;
|
1122 |
|
|
void __iomem *port_mmio;
|
1123 |
|
|
u32 tmp;
|
1124 |
|
|
|
1125 |
|
|
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
|
1126 |
|
|
port_mmio = __ahci_port_base(host, 4);
|
1127 |
|
|
|
1128 |
|
|
writel(0, port_mmio + PORT_IRQ_MASK);
|
1129 |
|
|
|
1130 |
|
|
/* clear port IRQ */
|
1131 |
|
|
tmp = readl(port_mmio + PORT_IRQ_STAT);
|
1132 |
|
|
VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
|
1133 |
|
|
if (tmp)
|
1134 |
|
|
writel(tmp, port_mmio + PORT_IRQ_STAT);
|
1135 |
|
|
}
|
1136 |
|
|
|
1137 |
|
|
for (i = 0; i < host->n_ports; i++) {
|
1138 |
|
|
struct ata_port *ap = host->ports[i];
|
1139 |
|
|
|
1140 |
|
|
port_mmio = ahci_port_base(ap);
|
1141 |
|
|
if (ata_port_is_dummy(ap))
|
1142 |
|
|
continue;
|
1143 |
|
|
|
1144 |
|
|
ahci_port_init(pdev, ap, i, mmio, port_mmio);
|
1145 |
|
|
}
|
1146 |
|
|
|
1147 |
|
|
tmp = readl(mmio + HOST_CTL);
|
1148 |
|
|
VPRINTK("HOST_CTL 0x%x\n", tmp);
|
1149 |
|
|
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
|
1150 |
|
|
tmp = readl(mmio + HOST_CTL);
|
1151 |
|
|
VPRINTK("HOST_CTL 0x%x\n", tmp);
|
1152 |
|
|
}
|
1153 |
|
|
|
1154 |
|
|
static unsigned int ahci_dev_classify(struct ata_port *ap)
|
1155 |
|
|
{
|
1156 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1157 |
|
|
struct ata_taskfile tf;
|
1158 |
|
|
u32 tmp;
|
1159 |
|
|
|
1160 |
|
|
tmp = readl(port_mmio + PORT_SIG);
|
1161 |
|
|
tf.lbah = (tmp >> 24) & 0xff;
|
1162 |
|
|
tf.lbam = (tmp >> 16) & 0xff;
|
1163 |
|
|
tf.lbal = (tmp >> 8) & 0xff;
|
1164 |
|
|
tf.nsect = (tmp) & 0xff;
|
1165 |
|
|
|
1166 |
|
|
return ata_dev_classify(&tf);
|
1167 |
|
|
}
|
1168 |
|
|
|
1169 |
|
|
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
|
1170 |
|
|
u32 opts)
|
1171 |
|
|
{
|
1172 |
|
|
dma_addr_t cmd_tbl_dma;
|
1173 |
|
|
|
1174 |
|
|
cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
|
1175 |
|
|
|
1176 |
|
|
pp->cmd_slot[tag].opts = cpu_to_le32(opts);
|
1177 |
|
|
pp->cmd_slot[tag].status = 0;
|
1178 |
|
|
pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
|
1179 |
|
|
pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
|
1180 |
|
|
}
|
1181 |
|
|
|
1182 |
|
|
static int ahci_kick_engine(struct ata_port *ap, int force_restart)
|
1183 |
|
|
{
|
1184 |
|
|
void __iomem *port_mmio = ap->ioaddr.cmd_addr;
|
1185 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
1186 |
|
|
u32 tmp;
|
1187 |
|
|
int busy, rc;
|
1188 |
|
|
|
1189 |
|
|
/* do we need to kick the port? */
|
1190 |
|
|
busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
|
1191 |
|
|
if (!busy && !force_restart)
|
1192 |
|
|
return 0;
|
1193 |
|
|
|
1194 |
|
|
/* stop engine */
|
1195 |
|
|
rc = ahci_stop_engine(ap);
|
1196 |
|
|
if (rc)
|
1197 |
|
|
goto out_restart;
|
1198 |
|
|
|
1199 |
|
|
/* need to do CLO? */
|
1200 |
|
|
if (!busy) {
|
1201 |
|
|
rc = 0;
|
1202 |
|
|
goto out_restart;
|
1203 |
|
|
}
|
1204 |
|
|
|
1205 |
|
|
if (!(hpriv->cap & HOST_CAP_CLO)) {
|
1206 |
|
|
rc = -EOPNOTSUPP;
|
1207 |
|
|
goto out_restart;
|
1208 |
|
|
}
|
1209 |
|
|
|
1210 |
|
|
/* perform CLO */
|
1211 |
|
|
tmp = readl(port_mmio + PORT_CMD);
|
1212 |
|
|
tmp |= PORT_CMD_CLO;
|
1213 |
|
|
writel(tmp, port_mmio + PORT_CMD);
|
1214 |
|
|
|
1215 |
|
|
rc = 0;
|
1216 |
|
|
tmp = ata_wait_register(port_mmio + PORT_CMD,
|
1217 |
|
|
PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
|
1218 |
|
|
if (tmp & PORT_CMD_CLO)
|
1219 |
|
|
rc = -EIO;
|
1220 |
|
|
|
1221 |
|
|
/* restart engine */
|
1222 |
|
|
out_restart:
|
1223 |
|
|
ahci_start_engine(ap);
|
1224 |
|
|
return rc;
|
1225 |
|
|
}
|
1226 |
|
|
|
1227 |
|
|
static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
|
1228 |
|
|
struct ata_taskfile *tf, int is_cmd, u16 flags,
|
1229 |
|
|
unsigned long timeout_msec)
|
1230 |
|
|
{
|
1231 |
|
|
const u32 cmd_fis_len = 5; /* five dwords */
|
1232 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1233 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1234 |
|
|
u8 *fis = pp->cmd_tbl;
|
1235 |
|
|
u32 tmp;
|
1236 |
|
|
|
1237 |
|
|
/* prep the command */
|
1238 |
|
|
ata_tf_to_fis(tf, pmp, is_cmd, fis);
|
1239 |
|
|
ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
|
1240 |
|
|
|
1241 |
|
|
/* issue & wait */
|
1242 |
|
|
writel(1, port_mmio + PORT_CMD_ISSUE);
|
1243 |
|
|
|
1244 |
|
|
if (timeout_msec) {
|
1245 |
|
|
tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
|
1246 |
|
|
1, timeout_msec);
|
1247 |
|
|
if (tmp & 0x1) {
|
1248 |
|
|
ahci_kick_engine(ap, 1);
|
1249 |
|
|
return -EBUSY;
|
1250 |
|
|
}
|
1251 |
|
|
} else
|
1252 |
|
|
readl(port_mmio + PORT_CMD_ISSUE); /* flush */
|
1253 |
|
|
|
1254 |
|
|
return 0;
|
1255 |
|
|
}
|
1256 |
|
|
|
1257 |
|
|
static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
|
1258 |
|
|
int pmp, unsigned long deadline)
|
1259 |
|
|
{
|
1260 |
|
|
struct ata_port *ap = link->ap;
|
1261 |
|
|
const char *reason = NULL;
|
1262 |
|
|
unsigned long now, msecs;
|
1263 |
|
|
struct ata_taskfile tf;
|
1264 |
|
|
int rc;
|
1265 |
|
|
|
1266 |
|
|
DPRINTK("ENTER\n");
|
1267 |
|
|
|
1268 |
|
|
if (ata_link_offline(link)) {
|
1269 |
|
|
DPRINTK("PHY reports no device\n");
|
1270 |
|
|
*class = ATA_DEV_NONE;
|
1271 |
|
|
return 0;
|
1272 |
|
|
}
|
1273 |
|
|
|
1274 |
|
|
/* prepare for SRST (AHCI-1.1 10.4.1) */
|
1275 |
|
|
rc = ahci_kick_engine(ap, 1);
|
1276 |
|
|
if (rc && rc != -EOPNOTSUPP)
|
1277 |
|
|
ata_link_printk(link, KERN_WARNING,
|
1278 |
|
|
"failed to reset engine (errno=%d)\n", rc);
|
1279 |
|
|
|
1280 |
|
|
ata_tf_init(link->device, &tf);
|
1281 |
|
|
|
1282 |
|
|
/* issue the first D2H Register FIS */
|
1283 |
|
|
msecs = 0;
|
1284 |
|
|
now = jiffies;
|
1285 |
|
|
if (time_after(now, deadline))
|
1286 |
|
|
msecs = jiffies_to_msecs(deadline - now);
|
1287 |
|
|
|
1288 |
|
|
tf.ctl |= ATA_SRST;
|
1289 |
|
|
if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
|
1290 |
|
|
AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
|
1291 |
|
|
rc = -EIO;
|
1292 |
|
|
reason = "1st FIS failed";
|
1293 |
|
|
goto fail;
|
1294 |
|
|
}
|
1295 |
|
|
|
1296 |
|
|
/* spec says at least 5us, but be generous and sleep for 1ms */
|
1297 |
|
|
msleep(1);
|
1298 |
|
|
|
1299 |
|
|
/* issue the second D2H Register FIS */
|
1300 |
|
|
tf.ctl &= ~ATA_SRST;
|
1301 |
|
|
ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
|
1302 |
|
|
|
1303 |
|
|
/* wait a while before checking status */
|
1304 |
|
|
ata_wait_after_reset(ap, deadline);
|
1305 |
|
|
|
1306 |
|
|
rc = ata_wait_ready(ap, deadline);
|
1307 |
|
|
/* link occupied, -ENODEV too is an error */
|
1308 |
|
|
if (rc) {
|
1309 |
|
|
reason = "device not ready";
|
1310 |
|
|
goto fail;
|
1311 |
|
|
}
|
1312 |
|
|
*class = ahci_dev_classify(ap);
|
1313 |
|
|
|
1314 |
|
|
DPRINTK("EXIT, class=%u\n", *class);
|
1315 |
|
|
return 0;
|
1316 |
|
|
|
1317 |
|
|
fail:
|
1318 |
|
|
ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
|
1319 |
|
|
return rc;
|
1320 |
|
|
}
|
1321 |
|
|
|
1322 |
|
|
static int ahci_softreset(struct ata_link *link, unsigned int *class,
|
1323 |
|
|
unsigned long deadline)
|
1324 |
|
|
{
|
1325 |
|
|
int pmp = 0;
|
1326 |
|
|
|
1327 |
|
|
if (link->ap->flags & ATA_FLAG_PMP)
|
1328 |
|
|
pmp = SATA_PMP_CTRL_PORT;
|
1329 |
|
|
|
1330 |
|
|
return ahci_do_softreset(link, class, pmp, deadline);
|
1331 |
|
|
}
|
1332 |
|
|
|
1333 |
|
|
static int ahci_hardreset(struct ata_link *link, unsigned int *class,
|
1334 |
|
|
unsigned long deadline)
|
1335 |
|
|
{
|
1336 |
|
|
struct ata_port *ap = link->ap;
|
1337 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1338 |
|
|
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
|
1339 |
|
|
struct ata_taskfile tf;
|
1340 |
|
|
int rc;
|
1341 |
|
|
|
1342 |
|
|
DPRINTK("ENTER\n");
|
1343 |
|
|
|
1344 |
|
|
ahci_stop_engine(ap);
|
1345 |
|
|
|
1346 |
|
|
/* clear D2H reception area to properly wait for D2H FIS */
|
1347 |
|
|
ata_tf_init(link->device, &tf);
|
1348 |
|
|
tf.command = 0x80;
|
1349 |
|
|
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
|
1350 |
|
|
|
1351 |
|
|
rc = sata_std_hardreset(link, class, deadline);
|
1352 |
|
|
|
1353 |
|
|
ahci_start_engine(ap);
|
1354 |
|
|
|
1355 |
|
|
if (rc == 0 && ata_link_online(link))
|
1356 |
|
|
*class = ahci_dev_classify(ap);
|
1357 |
|
|
if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
|
1358 |
|
|
*class = ATA_DEV_NONE;
|
1359 |
|
|
|
1360 |
|
|
DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
|
1361 |
|
|
return rc;
|
1362 |
|
|
}
|
1363 |
|
|
|
1364 |
|
|
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
|
1365 |
|
|
unsigned long deadline)
|
1366 |
|
|
{
|
1367 |
|
|
struct ata_port *ap = link->ap;
|
1368 |
|
|
u32 serror;
|
1369 |
|
|
int rc;
|
1370 |
|
|
|
1371 |
|
|
DPRINTK("ENTER\n");
|
1372 |
|
|
|
1373 |
|
|
ahci_stop_engine(ap);
|
1374 |
|
|
|
1375 |
|
|
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
|
1376 |
|
|
deadline);
|
1377 |
|
|
|
1378 |
|
|
/* vt8251 needs SError cleared for the port to operate */
|
1379 |
|
|
ahci_scr_read(ap, SCR_ERROR, &serror);
|
1380 |
|
|
ahci_scr_write(ap, SCR_ERROR, serror);
|
1381 |
|
|
|
1382 |
|
|
ahci_start_engine(ap);
|
1383 |
|
|
|
1384 |
|
|
DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
|
1385 |
|
|
|
1386 |
|
|
/* vt8251 doesn't clear BSY on signature FIS reception,
|
1387 |
|
|
* request follow-up softreset.
|
1388 |
|
|
*/
|
1389 |
|
|
return rc ?: -EAGAIN;
|
1390 |
|
|
}
|
1391 |
|
|
|
1392 |
|
|
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
|
1393 |
|
|
unsigned long deadline)
|
1394 |
|
|
{
|
1395 |
|
|
struct ata_port *ap = link->ap;
|
1396 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1397 |
|
|
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
|
1398 |
|
|
struct ata_taskfile tf;
|
1399 |
|
|
int rc;
|
1400 |
|
|
|
1401 |
|
|
ahci_stop_engine(ap);
|
1402 |
|
|
|
1403 |
|
|
/* clear D2H reception area to properly wait for D2H FIS */
|
1404 |
|
|
ata_tf_init(link->device, &tf);
|
1405 |
|
|
tf.command = 0x80;
|
1406 |
|
|
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
|
1407 |
|
|
|
1408 |
|
|
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
|
1409 |
|
|
deadline);
|
1410 |
|
|
|
1411 |
|
|
ahci_start_engine(ap);
|
1412 |
|
|
|
1413 |
|
|
if (rc || ata_link_offline(link))
|
1414 |
|
|
return rc;
|
1415 |
|
|
|
1416 |
|
|
/* spec mandates ">= 2ms" before checking status */
|
1417 |
|
|
msleep(150);
|
1418 |
|
|
|
1419 |
|
|
/* The pseudo configuration device on SIMG4726 attached to
|
1420 |
|
|
* ASUS P5W-DH Deluxe doesn't send signature FIS after
|
1421 |
|
|
* hardreset if no device is attached to the first downstream
|
1422 |
|
|
* port && the pseudo device locks up on SRST w/ PMP==0. To
|
1423 |
|
|
* work around this, wait for !BSY only briefly. If BSY isn't
|
1424 |
|
|
* cleared, perform CLO and proceed to IDENTIFY (achieved by
|
1425 |
|
|
* ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
|
1426 |
|
|
*
|
1427 |
|
|
* Wait for two seconds. Devices attached to downstream port
|
1428 |
|
|
* which can't process the following IDENTIFY after this will
|
1429 |
|
|
* have to be reset again. For most cases, this should
|
1430 |
|
|
* suffice while making probing snappish enough.
|
1431 |
|
|
*/
|
1432 |
|
|
rc = ata_wait_ready(ap, jiffies + 2 * HZ);
|
1433 |
|
|
if (rc)
|
1434 |
|
|
ahci_kick_engine(ap, 0);
|
1435 |
|
|
|
1436 |
|
|
return 0;
|
1437 |
|
|
}
|
1438 |
|
|
|
1439 |
|
|
static void ahci_postreset(struct ata_link *link, unsigned int *class)
|
1440 |
|
|
{
|
1441 |
|
|
struct ata_port *ap = link->ap;
|
1442 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1443 |
|
|
u32 new_tmp, tmp;
|
1444 |
|
|
|
1445 |
|
|
ata_std_postreset(link, class);
|
1446 |
|
|
|
1447 |
|
|
/* Make sure port's ATAPI bit is set appropriately */
|
1448 |
|
|
new_tmp = tmp = readl(port_mmio + PORT_CMD);
|
1449 |
|
|
if (*class == ATA_DEV_ATAPI)
|
1450 |
|
|
new_tmp |= PORT_CMD_ATAPI;
|
1451 |
|
|
else
|
1452 |
|
|
new_tmp &= ~PORT_CMD_ATAPI;
|
1453 |
|
|
if (new_tmp != tmp) {
|
1454 |
|
|
writel(new_tmp, port_mmio + PORT_CMD);
|
1455 |
|
|
readl(port_mmio + PORT_CMD); /* flush */
|
1456 |
|
|
}
|
1457 |
|
|
}
|
1458 |
|
|
|
1459 |
|
|
static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
|
1460 |
|
|
unsigned long deadline)
|
1461 |
|
|
{
|
1462 |
|
|
return ahci_do_softreset(link, class, link->pmp, deadline);
|
1463 |
|
|
}
|
1464 |
|
|
|
1465 |
|
|
static u8 ahci_check_status(struct ata_port *ap)
|
1466 |
|
|
{
|
1467 |
|
|
void __iomem *mmio = ap->ioaddr.cmd_addr;
|
1468 |
|
|
|
1469 |
|
|
return readl(mmio + PORT_TFDATA) & 0xFF;
|
1470 |
|
|
}
|
1471 |
|
|
|
1472 |
|
|
static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
1473 |
|
|
{
|
1474 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1475 |
|
|
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
|
1476 |
|
|
|
1477 |
|
|
ata_tf_from_fis(d2h_fis, tf);
|
1478 |
|
|
}
|
1479 |
|
|
|
1480 |
|
|
static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
|
1481 |
|
|
{
|
1482 |
|
|
struct scatterlist *sg;
|
1483 |
|
|
struct ahci_sg *ahci_sg;
|
1484 |
|
|
unsigned int n_sg = 0;
|
1485 |
|
|
|
1486 |
|
|
VPRINTK("ENTER\n");
|
1487 |
|
|
|
1488 |
|
|
/*
|
1489 |
|
|
* Next, the S/G list.
|
1490 |
|
|
*/
|
1491 |
|
|
ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
|
1492 |
|
|
ata_for_each_sg(sg, qc) {
|
1493 |
|
|
dma_addr_t addr = sg_dma_address(sg);
|
1494 |
|
|
u32 sg_len = sg_dma_len(sg);
|
1495 |
|
|
|
1496 |
|
|
ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
|
1497 |
|
|
ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
|
1498 |
|
|
ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
|
1499 |
|
|
|
1500 |
|
|
ahci_sg++;
|
1501 |
|
|
n_sg++;
|
1502 |
|
|
}
|
1503 |
|
|
|
1504 |
|
|
return n_sg;
|
1505 |
|
|
}
|
1506 |
|
|
|
1507 |
|
|
static void ahci_qc_prep(struct ata_queued_cmd *qc)
|
1508 |
|
|
{
|
1509 |
|
|
struct ata_port *ap = qc->ap;
|
1510 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1511 |
|
|
int is_atapi = is_atapi_taskfile(&qc->tf);
|
1512 |
|
|
void *cmd_tbl;
|
1513 |
|
|
u32 opts;
|
1514 |
|
|
const u32 cmd_fis_len = 5; /* five dwords */
|
1515 |
|
|
unsigned int n_elem;
|
1516 |
|
|
|
1517 |
|
|
/*
|
1518 |
|
|
* Fill in command table information. First, the header,
|
1519 |
|
|
* a SATA Register - Host to Device command FIS.
|
1520 |
|
|
*/
|
1521 |
|
|
cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
|
1522 |
|
|
|
1523 |
|
|
ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
|
1524 |
|
|
if (is_atapi) {
|
1525 |
|
|
memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
|
1526 |
|
|
memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
|
1527 |
|
|
}
|
1528 |
|
|
|
1529 |
|
|
n_elem = 0;
|
1530 |
|
|
if (qc->flags & ATA_QCFLAG_DMAMAP)
|
1531 |
|
|
n_elem = ahci_fill_sg(qc, cmd_tbl);
|
1532 |
|
|
|
1533 |
|
|
/*
|
1534 |
|
|
* Fill in command slot information.
|
1535 |
|
|
*/
|
1536 |
|
|
opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
|
1537 |
|
|
if (qc->tf.flags & ATA_TFLAG_WRITE)
|
1538 |
|
|
opts |= AHCI_CMD_WRITE;
|
1539 |
|
|
if (is_atapi)
|
1540 |
|
|
opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
|
1541 |
|
|
|
1542 |
|
|
ahci_fill_cmd_slot(pp, qc->tag, opts);
|
1543 |
|
|
}
|
1544 |
|
|
|
1545 |
|
|
static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
|
1546 |
|
|
{
|
1547 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
1548 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1549 |
|
|
struct ata_eh_info *host_ehi = &ap->link.eh_info;
|
1550 |
|
|
struct ata_link *link = NULL;
|
1551 |
|
|
struct ata_queued_cmd *active_qc;
|
1552 |
|
|
struct ata_eh_info *active_ehi;
|
1553 |
|
|
u32 serror;
|
1554 |
|
|
|
1555 |
|
|
/* determine active link */
|
1556 |
|
|
ata_port_for_each_link(link, ap)
|
1557 |
|
|
if (ata_link_active(link))
|
1558 |
|
|
break;
|
1559 |
|
|
if (!link)
|
1560 |
|
|
link = &ap->link;
|
1561 |
|
|
|
1562 |
|
|
active_qc = ata_qc_from_tag(ap, link->active_tag);
|
1563 |
|
|
active_ehi = &link->eh_info;
|
1564 |
|
|
|
1565 |
|
|
/* record irq stat */
|
1566 |
|
|
ata_ehi_clear_desc(host_ehi);
|
1567 |
|
|
ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
|
1568 |
|
|
|
1569 |
|
|
/* AHCI needs SError cleared; otherwise, it might lock up */
|
1570 |
|
|
ahci_scr_read(ap, SCR_ERROR, &serror);
|
1571 |
|
|
ahci_scr_write(ap, SCR_ERROR, serror);
|
1572 |
|
|
host_ehi->serror |= serror;
|
1573 |
|
|
|
1574 |
|
|
/* some controllers set IRQ_IF_ERR on device errors, ignore it */
|
1575 |
|
|
if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
|
1576 |
|
|
irq_stat &= ~PORT_IRQ_IF_ERR;
|
1577 |
|
|
|
1578 |
|
|
if (irq_stat & PORT_IRQ_TF_ERR) {
|
1579 |
|
|
/* If qc is active, charge it; otherwise, the active
|
1580 |
|
|
* link. There's no active qc on NCQ errors. It will
|
1581 |
|
|
* be determined by EH by reading log page 10h.
|
1582 |
|
|
*/
|
1583 |
|
|
if (active_qc)
|
1584 |
|
|
active_qc->err_mask |= AC_ERR_DEV;
|
1585 |
|
|
else
|
1586 |
|
|
active_ehi->err_mask |= AC_ERR_DEV;
|
1587 |
|
|
|
1588 |
|
|
if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
|
1589 |
|
|
host_ehi->serror &= ~SERR_INTERNAL;
|
1590 |
|
|
}
|
1591 |
|
|
|
1592 |
|
|
if (irq_stat & PORT_IRQ_UNK_FIS) {
|
1593 |
|
|
u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
|
1594 |
|
|
|
1595 |
|
|
active_ehi->err_mask |= AC_ERR_HSM;
|
1596 |
|
|
active_ehi->action |= ATA_EH_SOFTRESET;
|
1597 |
|
|
ata_ehi_push_desc(active_ehi,
|
1598 |
|
|
"unknown FIS %08x %08x %08x %08x" ,
|
1599 |
|
|
unk[0], unk[1], unk[2], unk[3]);
|
1600 |
|
|
}
|
1601 |
|
|
|
1602 |
|
|
if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
|
1603 |
|
|
active_ehi->err_mask |= AC_ERR_HSM;
|
1604 |
|
|
active_ehi->action |= ATA_EH_SOFTRESET;
|
1605 |
|
|
ata_ehi_push_desc(active_ehi, "incorrect PMP");
|
1606 |
|
|
}
|
1607 |
|
|
|
1608 |
|
|
if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
|
1609 |
|
|
host_ehi->err_mask |= AC_ERR_HOST_BUS;
|
1610 |
|
|
host_ehi->action |= ATA_EH_SOFTRESET;
|
1611 |
|
|
ata_ehi_push_desc(host_ehi, "host bus error");
|
1612 |
|
|
}
|
1613 |
|
|
|
1614 |
|
|
if (irq_stat & PORT_IRQ_IF_ERR) {
|
1615 |
|
|
host_ehi->err_mask |= AC_ERR_ATA_BUS;
|
1616 |
|
|
host_ehi->action |= ATA_EH_SOFTRESET;
|
1617 |
|
|
ata_ehi_push_desc(host_ehi, "interface fatal error");
|
1618 |
|
|
}
|
1619 |
|
|
|
1620 |
|
|
if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
|
1621 |
|
|
ata_ehi_hotplugged(host_ehi);
|
1622 |
|
|
ata_ehi_push_desc(host_ehi, "%s",
|
1623 |
|
|
irq_stat & PORT_IRQ_CONNECT ?
|
1624 |
|
|
"connection status changed" : "PHY RDY changed");
|
1625 |
|
|
}
|
1626 |
|
|
|
1627 |
|
|
/* okay, let's hand over to EH */
|
1628 |
|
|
|
1629 |
|
|
if (irq_stat & PORT_IRQ_FREEZE)
|
1630 |
|
|
ata_port_freeze(ap);
|
1631 |
|
|
else
|
1632 |
|
|
ata_port_abort(ap);
|
1633 |
|
|
}
|
1634 |
|
|
|
1635 |
|
|
static void ahci_port_intr(struct ata_port *ap)
|
1636 |
|
|
{
|
1637 |
|
|
void __iomem *port_mmio = ap->ioaddr.cmd_addr;
|
1638 |
|
|
struct ata_eh_info *ehi = &ap->link.eh_info;
|
1639 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1640 |
|
|
struct ahci_host_priv *hpriv = ap->host->private_data;
|
1641 |
|
|
int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
|
1642 |
|
|
u32 status, qc_active;
|
1643 |
|
|
int rc;
|
1644 |
|
|
|
1645 |
|
|
status = readl(port_mmio + PORT_IRQ_STAT);
|
1646 |
|
|
writel(status, port_mmio + PORT_IRQ_STAT);
|
1647 |
|
|
|
1648 |
|
|
/* ignore BAD_PMP while resetting */
|
1649 |
|
|
if (unlikely(resetting))
|
1650 |
|
|
status &= ~PORT_IRQ_BAD_PMP;
|
1651 |
|
|
|
1652 |
|
|
/* If we are getting PhyRdy, this is
|
1653 |
|
|
* just a power state change, we should
|
1654 |
|
|
* clear out this, plus the PhyRdy/Comm
|
1655 |
|
|
* Wake bits from Serror
|
1656 |
|
|
*/
|
1657 |
|
|
if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
|
1658 |
|
|
(status & PORT_IRQ_PHYRDY)) {
|
1659 |
|
|
status &= ~PORT_IRQ_PHYRDY;
|
1660 |
|
|
ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
|
1661 |
|
|
}
|
1662 |
|
|
|
1663 |
|
|
if (unlikely(status & PORT_IRQ_ERROR)) {
|
1664 |
|
|
ahci_error_intr(ap, status);
|
1665 |
|
|
return;
|
1666 |
|
|
}
|
1667 |
|
|
|
1668 |
|
|
if (status & PORT_IRQ_SDB_FIS) {
|
1669 |
|
|
/* If SNotification is available, leave notification
|
1670 |
|
|
* handling to sata_async_notification(). If not,
|
1671 |
|
|
* emulate it by snooping SDB FIS RX area.
|
1672 |
|
|
*
|
1673 |
|
|
* Snooping FIS RX area is probably cheaper than
|
1674 |
|
|
* poking SNotification but some constrollers which
|
1675 |
|
|
* implement SNotification, ICH9 for example, don't
|
1676 |
|
|
* store AN SDB FIS into receive area.
|
1677 |
|
|
*/
|
1678 |
|
|
if (hpriv->cap & HOST_CAP_SNTF)
|
1679 |
|
|
sata_async_notification(ap);
|
1680 |
|
|
else {
|
1681 |
|
|
/* If the 'N' bit in word 0 of the FIS is set,
|
1682 |
|
|
* we just received asynchronous notification.
|
1683 |
|
|
* Tell libata about it.
|
1684 |
|
|
*/
|
1685 |
|
|
const __le32 *f = pp->rx_fis + RX_FIS_SDB;
|
1686 |
|
|
u32 f0 = le32_to_cpu(f[0]);
|
1687 |
|
|
|
1688 |
|
|
if (f0 & (1 << 15))
|
1689 |
|
|
sata_async_notification(ap);
|
1690 |
|
|
}
|
1691 |
|
|
}
|
1692 |
|
|
|
1693 |
|
|
/* pp->active_link is valid iff any command is in flight */
|
1694 |
|
|
if (ap->qc_active && pp->active_link->sactive)
|
1695 |
|
|
qc_active = readl(port_mmio + PORT_SCR_ACT);
|
1696 |
|
|
else
|
1697 |
|
|
qc_active = readl(port_mmio + PORT_CMD_ISSUE);
|
1698 |
|
|
|
1699 |
|
|
rc = ata_qc_complete_multiple(ap, qc_active, NULL);
|
1700 |
|
|
|
1701 |
|
|
/* while resetting, invalid completions are expected */
|
1702 |
|
|
if (unlikely(rc < 0 && !resetting)) {
|
1703 |
|
|
ehi->err_mask |= AC_ERR_HSM;
|
1704 |
|
|
ehi->action |= ATA_EH_SOFTRESET;
|
1705 |
|
|
ata_port_freeze(ap);
|
1706 |
|
|
}
|
1707 |
|
|
}
|
1708 |
|
|
|
1709 |
|
|
static void ahci_irq_clear(struct ata_port *ap)
|
1710 |
|
|
{
|
1711 |
|
|
/* TODO */
|
1712 |
|
|
}
|
1713 |
|
|
|
1714 |
|
|
static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
|
1715 |
|
|
{
|
1716 |
|
|
struct ata_host *host = dev_instance;
|
1717 |
|
|
struct ahci_host_priv *hpriv;
|
1718 |
|
|
unsigned int i, handled = 0;
|
1719 |
|
|
void __iomem *mmio;
|
1720 |
|
|
u32 irq_stat, irq_ack = 0;
|
1721 |
|
|
|
1722 |
|
|
VPRINTK("ENTER\n");
|
1723 |
|
|
|
1724 |
|
|
hpriv = host->private_data;
|
1725 |
|
|
mmio = host->iomap[AHCI_PCI_BAR];
|
1726 |
|
|
|
1727 |
|
|
/* sigh. 0xffffffff is a valid return from h/w */
|
1728 |
|
|
irq_stat = readl(mmio + HOST_IRQ_STAT);
|
1729 |
|
|
irq_stat &= hpriv->port_map;
|
1730 |
|
|
if (!irq_stat)
|
1731 |
|
|
return IRQ_NONE;
|
1732 |
|
|
|
1733 |
|
|
spin_lock(&host->lock);
|
1734 |
|
|
|
1735 |
|
|
for (i = 0; i < host->n_ports; i++) {
|
1736 |
|
|
struct ata_port *ap;
|
1737 |
|
|
|
1738 |
|
|
if (!(irq_stat & (1 << i)))
|
1739 |
|
|
continue;
|
1740 |
|
|
|
1741 |
|
|
ap = host->ports[i];
|
1742 |
|
|
if (ap) {
|
1743 |
|
|
ahci_port_intr(ap);
|
1744 |
|
|
VPRINTK("port %u\n", i);
|
1745 |
|
|
} else {
|
1746 |
|
|
VPRINTK("port %u (no irq)\n", i);
|
1747 |
|
|
if (ata_ratelimit())
|
1748 |
|
|
dev_printk(KERN_WARNING, host->dev,
|
1749 |
|
|
"interrupt on disabled port %u\n", i);
|
1750 |
|
|
}
|
1751 |
|
|
|
1752 |
|
|
irq_ack |= (1 << i);
|
1753 |
|
|
}
|
1754 |
|
|
|
1755 |
|
|
if (irq_ack) {
|
1756 |
|
|
writel(irq_ack, mmio + HOST_IRQ_STAT);
|
1757 |
|
|
handled = 1;
|
1758 |
|
|
}
|
1759 |
|
|
|
1760 |
|
|
spin_unlock(&host->lock);
|
1761 |
|
|
|
1762 |
|
|
VPRINTK("EXIT\n");
|
1763 |
|
|
|
1764 |
|
|
return IRQ_RETVAL(handled);
|
1765 |
|
|
}
|
1766 |
|
|
|
1767 |
|
|
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
|
1768 |
|
|
{
|
1769 |
|
|
struct ata_port *ap = qc->ap;
|
1770 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1771 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1772 |
|
|
|
1773 |
|
|
/* Keep track of the currently active link. It will be used
|
1774 |
|
|
* in completion path to determine whether NCQ phase is in
|
1775 |
|
|
* progress.
|
1776 |
|
|
*/
|
1777 |
|
|
pp->active_link = qc->dev->link;
|
1778 |
|
|
|
1779 |
|
|
if (qc->tf.protocol == ATA_PROT_NCQ)
|
1780 |
|
|
writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
|
1781 |
|
|
writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
|
1782 |
|
|
readl(port_mmio + PORT_CMD_ISSUE); /* flush */
|
1783 |
|
|
|
1784 |
|
|
return 0;
|
1785 |
|
|
}
|
1786 |
|
|
|
1787 |
|
|
static void ahci_freeze(struct ata_port *ap)
|
1788 |
|
|
{
|
1789 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1790 |
|
|
|
1791 |
|
|
/* turn IRQ off */
|
1792 |
|
|
writel(0, port_mmio + PORT_IRQ_MASK);
|
1793 |
|
|
}
|
1794 |
|
|
|
1795 |
|
|
static void ahci_thaw(struct ata_port *ap)
|
1796 |
|
|
{
|
1797 |
|
|
void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
|
1798 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1799 |
|
|
u32 tmp;
|
1800 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1801 |
|
|
|
1802 |
|
|
/* clear IRQ */
|
1803 |
|
|
tmp = readl(port_mmio + PORT_IRQ_STAT);
|
1804 |
|
|
writel(tmp, port_mmio + PORT_IRQ_STAT);
|
1805 |
|
|
writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
|
1806 |
|
|
|
1807 |
|
|
/* turn IRQ back on */
|
1808 |
|
|
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
|
1809 |
|
|
}
|
1810 |
|
|
|
1811 |
|
|
static void ahci_error_handler(struct ata_port *ap)
|
1812 |
|
|
{
|
1813 |
|
|
if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
|
1814 |
|
|
/* restart engine */
|
1815 |
|
|
ahci_stop_engine(ap);
|
1816 |
|
|
ahci_start_engine(ap);
|
1817 |
|
|
}
|
1818 |
|
|
|
1819 |
|
|
/* perform recovery */
|
1820 |
|
|
sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
|
1821 |
|
|
ahci_hardreset, ahci_postreset,
|
1822 |
|
|
sata_pmp_std_prereset, ahci_pmp_softreset,
|
1823 |
|
|
sata_pmp_std_hardreset, sata_pmp_std_postreset);
|
1824 |
|
|
}
|
1825 |
|
|
|
1826 |
|
|
static void ahci_vt8251_error_handler(struct ata_port *ap)
|
1827 |
|
|
{
|
1828 |
|
|
if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
|
1829 |
|
|
/* restart engine */
|
1830 |
|
|
ahci_stop_engine(ap);
|
1831 |
|
|
ahci_start_engine(ap);
|
1832 |
|
|
}
|
1833 |
|
|
|
1834 |
|
|
/* perform recovery */
|
1835 |
|
|
ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
|
1836 |
|
|
ahci_postreset);
|
1837 |
|
|
}
|
1838 |
|
|
|
1839 |
|
|
static void ahci_p5wdh_error_handler(struct ata_port *ap)
|
1840 |
|
|
{
|
1841 |
|
|
if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
|
1842 |
|
|
/* restart engine */
|
1843 |
|
|
ahci_stop_engine(ap);
|
1844 |
|
|
ahci_start_engine(ap);
|
1845 |
|
|
}
|
1846 |
|
|
|
1847 |
|
|
/* perform recovery */
|
1848 |
|
|
ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
|
1849 |
|
|
ahci_postreset);
|
1850 |
|
|
}
|
1851 |
|
|
|
1852 |
|
|
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
|
1853 |
|
|
{
|
1854 |
|
|
struct ata_port *ap = qc->ap;
|
1855 |
|
|
|
1856 |
|
|
/* make DMA engine forget about the failed command */
|
1857 |
|
|
if (qc->flags & ATA_QCFLAG_FAILED)
|
1858 |
|
|
ahci_kick_engine(ap, 1);
|
1859 |
|
|
}
|
1860 |
|
|
|
1861 |
|
|
static void ahci_pmp_attach(struct ata_port *ap)
|
1862 |
|
|
{
|
1863 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1864 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1865 |
|
|
u32 cmd;
|
1866 |
|
|
|
1867 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
1868 |
|
|
cmd |= PORT_CMD_PMP;
|
1869 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
1870 |
|
|
|
1871 |
|
|
pp->intr_mask |= PORT_IRQ_BAD_PMP;
|
1872 |
|
|
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
|
1873 |
|
|
}
|
1874 |
|
|
|
1875 |
|
|
static void ahci_pmp_detach(struct ata_port *ap)
|
1876 |
|
|
{
|
1877 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
1878 |
|
|
struct ahci_port_priv *pp = ap->private_data;
|
1879 |
|
|
u32 cmd;
|
1880 |
|
|
|
1881 |
|
|
cmd = readl(port_mmio + PORT_CMD);
|
1882 |
|
|
cmd &= ~PORT_CMD_PMP;
|
1883 |
|
|
writel(cmd, port_mmio + PORT_CMD);
|
1884 |
|
|
|
1885 |
|
|
pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
|
1886 |
|
|
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
|
1887 |
|
|
}
|
1888 |
|
|
|
1889 |
|
|
static int ahci_port_resume(struct ata_port *ap)
|
1890 |
|
|
{
|
1891 |
|
|
ahci_power_up(ap);
|
1892 |
|
|
ahci_start_port(ap);
|
1893 |
|
|
|
1894 |
|
|
if (ap->nr_pmp_links)
|
1895 |
|
|
ahci_pmp_attach(ap);
|
1896 |
|
|
else
|
1897 |
|
|
ahci_pmp_detach(ap);
|
1898 |
|
|
|
1899 |
|
|
return 0;
|
1900 |
|
|
}
|
1901 |
|
|
|
1902 |
|
|
#ifdef CONFIG_PM
|
1903 |
|
|
static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
|
1904 |
|
|
{
|
1905 |
|
|
const char *emsg = NULL;
|
1906 |
|
|
int rc;
|
1907 |
|
|
|
1908 |
|
|
rc = ahci_deinit_port(ap, &emsg);
|
1909 |
|
|
if (rc == 0)
|
1910 |
|
|
ahci_power_down(ap);
|
1911 |
|
|
else {
|
1912 |
|
|
ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
|
1913 |
|
|
ahci_start_port(ap);
|
1914 |
|
|
}
|
1915 |
|
|
|
1916 |
|
|
return rc;
|
1917 |
|
|
}
|
1918 |
|
|
|
1919 |
|
|
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
|
1920 |
|
|
{
|
1921 |
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
1922 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
1923 |
|
|
u32 ctl;
|
1924 |
|
|
|
1925 |
|
|
if (mesg.event == PM_EVENT_SUSPEND) {
|
1926 |
|
|
/* AHCI spec rev1.1 section 8.3.3:
|
1927 |
|
|
* Software must disable interrupts prior to requesting a
|
1928 |
|
|
* transition of the HBA to D3 state.
|
1929 |
|
|
*/
|
1930 |
|
|
ctl = readl(mmio + HOST_CTL);
|
1931 |
|
|
ctl &= ~HOST_IRQ_EN;
|
1932 |
|
|
writel(ctl, mmio + HOST_CTL);
|
1933 |
|
|
readl(mmio + HOST_CTL); /* flush */
|
1934 |
|
|
}
|
1935 |
|
|
|
1936 |
|
|
return ata_pci_device_suspend(pdev, mesg);
|
1937 |
|
|
}
|
1938 |
|
|
|
1939 |
|
|
static int ahci_pci_device_resume(struct pci_dev *pdev)
|
1940 |
|
|
{
|
1941 |
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
1942 |
|
|
int rc;
|
1943 |
|
|
|
1944 |
|
|
rc = ata_pci_device_do_resume(pdev);
|
1945 |
|
|
if (rc)
|
1946 |
|
|
return rc;
|
1947 |
|
|
|
1948 |
|
|
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
|
1949 |
|
|
rc = ahci_reset_controller(host);
|
1950 |
|
|
if (rc)
|
1951 |
|
|
return rc;
|
1952 |
|
|
|
1953 |
|
|
ahci_init_controller(host);
|
1954 |
|
|
}
|
1955 |
|
|
|
1956 |
|
|
ata_host_resume(host);
|
1957 |
|
|
|
1958 |
|
|
return 0;
|
1959 |
|
|
}
|
1960 |
|
|
#endif
|
1961 |
|
|
|
1962 |
|
|
static int ahci_port_start(struct ata_port *ap)
|
1963 |
|
|
{
|
1964 |
|
|
struct device *dev = ap->host->dev;
|
1965 |
|
|
struct ahci_port_priv *pp;
|
1966 |
|
|
void *mem;
|
1967 |
|
|
dma_addr_t mem_dma;
|
1968 |
|
|
int rc;
|
1969 |
|
|
|
1970 |
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
1971 |
|
|
if (!pp)
|
1972 |
|
|
return -ENOMEM;
|
1973 |
|
|
|
1974 |
|
|
rc = ata_pad_alloc(ap, dev);
|
1975 |
|
|
if (rc)
|
1976 |
|
|
return rc;
|
1977 |
|
|
|
1978 |
|
|
mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
|
1979 |
|
|
GFP_KERNEL);
|
1980 |
|
|
if (!mem)
|
1981 |
|
|
return -ENOMEM;
|
1982 |
|
|
memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
|
1983 |
|
|
|
1984 |
|
|
/*
|
1985 |
|
|
* First item in chunk of DMA memory: 32-slot command table,
|
1986 |
|
|
* 32 bytes each in size
|
1987 |
|
|
*/
|
1988 |
|
|
pp->cmd_slot = mem;
|
1989 |
|
|
pp->cmd_slot_dma = mem_dma;
|
1990 |
|
|
|
1991 |
|
|
mem += AHCI_CMD_SLOT_SZ;
|
1992 |
|
|
mem_dma += AHCI_CMD_SLOT_SZ;
|
1993 |
|
|
|
1994 |
|
|
/*
|
1995 |
|
|
* Second item: Received-FIS area
|
1996 |
|
|
*/
|
1997 |
|
|
pp->rx_fis = mem;
|
1998 |
|
|
pp->rx_fis_dma = mem_dma;
|
1999 |
|
|
|
2000 |
|
|
mem += AHCI_RX_FIS_SZ;
|
2001 |
|
|
mem_dma += AHCI_RX_FIS_SZ;
|
2002 |
|
|
|
2003 |
|
|
/*
|
2004 |
|
|
* Third item: data area for storing a single command
|
2005 |
|
|
* and its scatter-gather table
|
2006 |
|
|
*/
|
2007 |
|
|
pp->cmd_tbl = mem;
|
2008 |
|
|
pp->cmd_tbl_dma = mem_dma;
|
2009 |
|
|
|
2010 |
|
|
/*
|
2011 |
|
|
* Save off initial list of interrupts to be enabled.
|
2012 |
|
|
* This could be changed later
|
2013 |
|
|
*/
|
2014 |
|
|
pp->intr_mask = DEF_PORT_IRQ;
|
2015 |
|
|
|
2016 |
|
|
ap->private_data = pp;
|
2017 |
|
|
|
2018 |
|
|
/* engage engines, captain */
|
2019 |
|
|
return ahci_port_resume(ap);
|
2020 |
|
|
}
|
2021 |
|
|
|
2022 |
|
|
static void ahci_port_stop(struct ata_port *ap)
|
2023 |
|
|
{
|
2024 |
|
|
const char *emsg = NULL;
|
2025 |
|
|
int rc;
|
2026 |
|
|
|
2027 |
|
|
/* de-initialize port */
|
2028 |
|
|
rc = ahci_deinit_port(ap, &emsg);
|
2029 |
|
|
if (rc)
|
2030 |
|
|
ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
|
2031 |
|
|
}
|
2032 |
|
|
|
2033 |
|
|
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
|
2034 |
|
|
{
|
2035 |
|
|
int rc;
|
2036 |
|
|
|
2037 |
|
|
if (using_dac &&
|
2038 |
|
|
!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
|
2039 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
|
2040 |
|
|
if (rc) {
|
2041 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
2042 |
|
|
if (rc) {
|
2043 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
2044 |
|
|
"64-bit DMA enable failed\n");
|
2045 |
|
|
return rc;
|
2046 |
|
|
}
|
2047 |
|
|
}
|
2048 |
|
|
} else {
|
2049 |
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
2050 |
|
|
if (rc) {
|
2051 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
2052 |
|
|
"32-bit DMA enable failed\n");
|
2053 |
|
|
return rc;
|
2054 |
|
|
}
|
2055 |
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
2056 |
|
|
if (rc) {
|
2057 |
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
2058 |
|
|
"32-bit consistent DMA enable failed\n");
|
2059 |
|
|
return rc;
|
2060 |
|
|
}
|
2061 |
|
|
}
|
2062 |
|
|
return 0;
|
2063 |
|
|
}
|
2064 |
|
|
|
2065 |
|
|
static void ahci_print_info(struct ata_host *host)
|
2066 |
|
|
{
|
2067 |
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
2068 |
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
2069 |
|
|
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
|
2070 |
|
|
u32 vers, cap, impl, speed;
|
2071 |
|
|
const char *speed_s;
|
2072 |
|
|
u16 cc;
|
2073 |
|
|
const char *scc_s;
|
2074 |
|
|
|
2075 |
|
|
vers = readl(mmio + HOST_VERSION);
|
2076 |
|
|
cap = hpriv->cap;
|
2077 |
|
|
impl = hpriv->port_map;
|
2078 |
|
|
|
2079 |
|
|
speed = (cap >> 20) & 0xf;
|
2080 |
|
|
if (speed == 1)
|
2081 |
|
|
speed_s = "1.5";
|
2082 |
|
|
else if (speed == 2)
|
2083 |
|
|
speed_s = "3";
|
2084 |
|
|
else
|
2085 |
|
|
speed_s = "?";
|
2086 |
|
|
|
2087 |
|
|
pci_read_config_word(pdev, 0x0a, &cc);
|
2088 |
|
|
if (cc == PCI_CLASS_STORAGE_IDE)
|
2089 |
|
|
scc_s = "IDE";
|
2090 |
|
|
else if (cc == PCI_CLASS_STORAGE_SATA)
|
2091 |
|
|
scc_s = "SATA";
|
2092 |
|
|
else if (cc == PCI_CLASS_STORAGE_RAID)
|
2093 |
|
|
scc_s = "RAID";
|
2094 |
|
|
else
|
2095 |
|
|
scc_s = "unknown";
|
2096 |
|
|
|
2097 |
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
2098 |
|
|
"AHCI %02x%02x.%02x%02x "
|
2099 |
|
|
"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
|
2100 |
|
|
,
|
2101 |
|
|
|
2102 |
|
|
(vers >> 24) & 0xff,
|
2103 |
|
|
(vers >> 16) & 0xff,
|
2104 |
|
|
(vers >> 8) & 0xff,
|
2105 |
|
|
vers & 0xff,
|
2106 |
|
|
|
2107 |
|
|
((cap >> 8) & 0x1f) + 1,
|
2108 |
|
|
(cap & 0x1f) + 1,
|
2109 |
|
|
speed_s,
|
2110 |
|
|
impl,
|
2111 |
|
|
scc_s);
|
2112 |
|
|
|
2113 |
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
2114 |
|
|
"flags: "
|
2115 |
|
|
"%s%s%s%s%s%s%s"
|
2116 |
|
|
"%s%s%s%s%s%s%s\n"
|
2117 |
|
|
,
|
2118 |
|
|
|
2119 |
|
|
cap & (1 << 31) ? "64bit " : "",
|
2120 |
|
|
cap & (1 << 30) ? "ncq " : "",
|
2121 |
|
|
cap & (1 << 29) ? "sntf " : "",
|
2122 |
|
|
cap & (1 << 28) ? "ilck " : "",
|
2123 |
|
|
cap & (1 << 27) ? "stag " : "",
|
2124 |
|
|
cap & (1 << 26) ? "pm " : "",
|
2125 |
|
|
cap & (1 << 25) ? "led " : "",
|
2126 |
|
|
|
2127 |
|
|
cap & (1 << 24) ? "clo " : "",
|
2128 |
|
|
cap & (1 << 19) ? "nz " : "",
|
2129 |
|
|
cap & (1 << 18) ? "only " : "",
|
2130 |
|
|
cap & (1 << 17) ? "pmp " : "",
|
2131 |
|
|
cap & (1 << 15) ? "pio " : "",
|
2132 |
|
|
cap & (1 << 14) ? "slum " : "",
|
2133 |
|
|
cap & (1 << 13) ? "part " : ""
|
2134 |
|
|
);
|
2135 |
|
|
}
|
2136 |
|
|
|
2137 |
|
|
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
|
2138 |
|
|
* hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
|
2139 |
|
|
* support PMP and the 4726 either directly exports the device
|
2140 |
|
|
* attached to the first downstream port or acts as a hardware storage
|
2141 |
|
|
* controller and emulate a single ATA device (can be RAID 0/1 or some
|
2142 |
|
|
* other configuration).
|
2143 |
|
|
*
|
2144 |
|
|
* When there's no device attached to the first downstream port of the
|
2145 |
|
|
* 4726, "Config Disk" appears, which is a pseudo ATA device to
|
2146 |
|
|
* configure the 4726. However, ATA emulation of the device is very
|
2147 |
|
|
* lame. It doesn't send signature D2H Reg FIS after the initial
|
2148 |
|
|
* hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
|
2149 |
|
|
*
|
2150 |
|
|
* The following function works around the problem by always using
|
2151 |
|
|
* hardreset on the port and not depending on receiving signature FIS
|
2152 |
|
|
* afterward. If signature FIS isn't received soon, ATA class is
|
2153 |
|
|
* assumed without follow-up softreset.
|
2154 |
|
|
*/
|
2155 |
|
|
static void ahci_p5wdh_workaround(struct ata_host *host)
|
2156 |
|
|
{
|
2157 |
|
|
static struct dmi_system_id sysids[] = {
|
2158 |
|
|
{
|
2159 |
|
|
.ident = "P5W DH Deluxe",
|
2160 |
|
|
.matches = {
|
2161 |
|
|
DMI_MATCH(DMI_SYS_VENDOR,
|
2162 |
|
|
"ASUSTEK COMPUTER INC"),
|
2163 |
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
|
2164 |
|
|
},
|
2165 |
|
|
},
|
2166 |
|
|
{ }
|
2167 |
|
|
};
|
2168 |
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
2169 |
|
|
|
2170 |
|
|
if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
|
2171 |
|
|
dmi_check_system(sysids)) {
|
2172 |
|
|
struct ata_port *ap = host->ports[1];
|
2173 |
|
|
|
2174 |
|
|
dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
|
2175 |
|
|
"Deluxe on-board SIMG4726 workaround\n");
|
2176 |
|
|
|
2177 |
|
|
ap->ops = &ahci_p5wdh_ops;
|
2178 |
|
|
ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
|
2179 |
|
|
}
|
2180 |
|
|
}
|
2181 |
|
|
|
2182 |
|
|
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
2183 |
|
|
{
|
2184 |
|
|
static int printed_version;
|
2185 |
|
|
struct ata_port_info pi = ahci_port_info[ent->driver_data];
|
2186 |
|
|
const struct ata_port_info *ppi[] = { &pi, NULL };
|
2187 |
|
|
struct device *dev = &pdev->dev;
|
2188 |
|
|
struct ahci_host_priv *hpriv;
|
2189 |
|
|
struct ata_host *host;
|
2190 |
|
|
int i, rc;
|
2191 |
|
|
|
2192 |
|
|
VPRINTK("ENTER\n");
|
2193 |
|
|
|
2194 |
|
|
WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
|
2195 |
|
|
|
2196 |
|
|
if (!printed_version++)
|
2197 |
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
2198 |
|
|
|
2199 |
|
|
/* acquire resources */
|
2200 |
|
|
rc = pcim_enable_device(pdev);
|
2201 |
|
|
if (rc)
|
2202 |
|
|
return rc;
|
2203 |
|
|
|
2204 |
|
|
rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
|
2205 |
|
|
if (rc == -EBUSY)
|
2206 |
|
|
pcim_pin_device(pdev);
|
2207 |
|
|
if (rc)
|
2208 |
|
|
return rc;
|
2209 |
|
|
|
2210 |
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
|
2211 |
|
|
(pdev->device == 0x2652 || pdev->device == 0x2653)) {
|
2212 |
|
|
u8 map;
|
2213 |
|
|
|
2214 |
|
|
/* ICH6s share the same PCI ID for both piix and ahci
|
2215 |
|
|
* modes. Enabling ahci mode while MAP indicates
|
2216 |
|
|
* combined mode is a bad idea. Yield to ata_piix.
|
2217 |
|
|
*/
|
2218 |
|
|
pci_read_config_byte(pdev, ICH_MAP, &map);
|
2219 |
|
|
if (map & 0x3) {
|
2220 |
|
|
dev_printk(KERN_INFO, &pdev->dev, "controller is in "
|
2221 |
|
|
"combined mode, can't enable AHCI mode\n");
|
2222 |
|
|
return -ENODEV;
|
2223 |
|
|
}
|
2224 |
|
|
}
|
2225 |
|
|
|
2226 |
|
|
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
|
2227 |
|
|
if (!hpriv)
|
2228 |
|
|
return -ENOMEM;
|
2229 |
|
|
hpriv->flags |= (unsigned long)pi.private_data;
|
2230 |
|
|
|
2231 |
|
|
if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
|
2232 |
|
|
pci_intx(pdev, 1);
|
2233 |
|
|
|
2234 |
|
|
/* save initial config */
|
2235 |
|
|
ahci_save_initial_config(pdev, hpriv);
|
2236 |
|
|
|
2237 |
|
|
/* prepare host */
|
2238 |
|
|
if (hpriv->cap & HOST_CAP_NCQ)
|
2239 |
|
|
pi.flags |= ATA_FLAG_NCQ;
|
2240 |
|
|
|
2241 |
|
|
if (hpriv->cap & HOST_CAP_PMP)
|
2242 |
|
|
pi.flags |= ATA_FLAG_PMP;
|
2243 |
|
|
|
2244 |
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
|
2245 |
|
|
if (!host)
|
2246 |
|
|
return -ENOMEM;
|
2247 |
|
|
host->iomap = pcim_iomap_table(pdev);
|
2248 |
|
|
host->private_data = hpriv;
|
2249 |
|
|
|
2250 |
|
|
for (i = 0; i < host->n_ports; i++) {
|
2251 |
|
|
struct ata_port *ap = host->ports[i];
|
2252 |
|
|
void __iomem *port_mmio = ahci_port_base(ap);
|
2253 |
|
|
|
2254 |
|
|
ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
|
2255 |
|
|
ata_port_pbar_desc(ap, AHCI_PCI_BAR,
|
2256 |
|
|
0x100 + ap->port_no * 0x80, "port");
|
2257 |
|
|
|
2258 |
|
|
/* set initial link pm policy */
|
2259 |
|
|
ap->pm_policy = NOT_AVAILABLE;
|
2260 |
|
|
|
2261 |
|
|
/* standard SATA port setup */
|
2262 |
|
|
if (hpriv->port_map & (1 << i))
|
2263 |
|
|
ap->ioaddr.cmd_addr = port_mmio;
|
2264 |
|
|
|
2265 |
|
|
/* disabled/not-implemented port */
|
2266 |
|
|
else
|
2267 |
|
|
ap->ops = &ata_dummy_port_ops;
|
2268 |
|
|
}
|
2269 |
|
|
|
2270 |
|
|
/* apply workaround for ASUS P5W DH Deluxe mainboard */
|
2271 |
|
|
ahci_p5wdh_workaround(host);
|
2272 |
|
|
|
2273 |
|
|
/* initialize adapter */
|
2274 |
|
|
rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
|
2275 |
|
|
if (rc)
|
2276 |
|
|
return rc;
|
2277 |
|
|
|
2278 |
|
|
rc = ahci_reset_controller(host);
|
2279 |
|
|
if (rc)
|
2280 |
|
|
return rc;
|
2281 |
|
|
|
2282 |
|
|
ahci_init_controller(host);
|
2283 |
|
|
ahci_print_info(host);
|
2284 |
|
|
|
2285 |
|
|
pci_set_master(pdev);
|
2286 |
|
|
return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
|
2287 |
|
|
&ahci_sht);
|
2288 |
|
|
}
|
2289 |
|
|
|
2290 |
|
|
static int __init ahci_init(void)
|
2291 |
|
|
{
|
2292 |
|
|
return pci_register_driver(&ahci_pci_driver);
|
2293 |
|
|
}
|
2294 |
|
|
|
2295 |
|
|
static void __exit ahci_exit(void)
|
2296 |
|
|
{
|
2297 |
|
|
pci_unregister_driver(&ahci_pci_driver);
|
2298 |
|
|
}
|
2299 |
|
|
|
2300 |
|
|
|
2301 |
|
|
MODULE_AUTHOR("Jeff Garzik");
|
2302 |
|
|
MODULE_DESCRIPTION("AHCI SATA low-level driver");
|
2303 |
|
|
MODULE_LICENSE("GPL");
|
2304 |
|
|
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
|
2305 |
|
|
MODULE_VERSION(DRV_VERSION);
|
2306 |
|
|
|
2307 |
|
|
module_init(ahci_init);
|
2308 |
|
|
module_exit(ahci_exit);
|